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16
H8/3006, H8/3007
Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series H8/3006 H8/3007 HD6413006 HD6413007
Rev.5.00 Revision date: Sep. 12, 2007
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
Rev.5.00 Sep. 12, 2007 Page ii of xxviii REJ09B0396-0500
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev.5.00 Sep. 12, 2007 Page iii of xxviii REJ09B0396-0500
Rev.5.00 Sep. 12, 2007 Page iv of xxviii REJ09B0396-0500
Preface
The H8/3006 and H8/3007 are a series of high-performance microcontrollers that integrate system supporting functions together with an H8/300H CPU core. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. The on-chip supporting functions include RAM, 16-bit timers, 8-bit timers, a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, and a DMA controller (DMAC). The address space is divided into eight areas. The data bus width and access cycle length can be selected independently in each area, simplifying the connection of different types of memory. Four MCU operating modes (modes 1 to 4) are provided, offering a choice of data bus width initial value and address space. With these features, the H8/3006 and H8/3007 offer easy implementation of compact, highperformance systems. This manual describes the H8/3006 and H8/3007 Group hardware. For details of the instruction set, refer to the H8/300H Series Software Manual.
Rev.5.00 Sep. 12, 2007 Page v of xxviii REJ09B0396-0500
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Main Revisions for This Edition
Item All 5.4.2 Interrupt Sequence Figure 5.7 Interrupt Sequence 8.7.2 Register Configuration Table 8.14 Port A Pin Functions (Modes 1 to 4) PA3/TP3/TIOCB0/TCLKD 274 Description and note amended Bit PWM0 in TMDR, bits IOB2 to IOB0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR2 of the 8-bit timer, bit NDER3 in NDERA, and bit PA3DDR select the pin function as follows. Notes: 2. TCLKD input when TPSC2 = TPSC1 = TPSC0 = 1 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR2 are as shown in (3) in the table below. Table amended
Pin PA2/TP2/ TIOCA0/ TCLKC Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOA2 to IOA0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR0 of the 8-bit timer, bit NDER2 in NDERA, and bit PA2DDR select the pin function as follows. 16-bit timer channel 0 settings PA2DDR NDER2 Pin function (1) in table below TIOCA0 output 0 PA2 input
2
Page 102
Revision (See Manual for Details) Company name and brand names amended (Before) Hitachi, Ltd. (After) Renesas Technology Corp. Figure amended D15 to D0
PA2/TP2/TIOCA0/TCLKC 275
(2) in table below 1 0 PA2 output TIOCA0 input* TCLKC input*
1
1 1 TP2 output
Notes: 1. TIOCA0 input when IOA2 = 1. 2. TCLKC input when TPSC2 = TPSC1 = 1 and TPSC0 = 0 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR0 are as shown in (3) in the table below. 16-bit timer channel 0 settings PWM0 IOA2 IOA1 IOA0 8-bit timer channel 0 settings CKS2 CKS1 CKS0 0 0 0 1 0 0 0 0 1 1 (2) (1) 0 1 (2) (1) 1
(4) 1
(3)
1
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Item 8.7.2 Register Configuration Table 8.14 Port A Pin Functions (Modes 1 to 4) PA1/TP1/TCLKB/TEND1
Page 276
Revision (See Manual for Details) Table amended
Pin PA1/TP1/ TCLKB/ TEND1 Pin Functions and Selection Method Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR3 of the 8-bit timer, bit NDER1 in NDERA, and bit PA1DDR select the pin function as follows. PA1DDR NDER1 Pin function 0 PA1 input 1 0 PA1 output TCLKB input*
1 2
1 1 TP1 output
TEND1 output*
Notes: 1. TCLKB input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0, and TPSC0 = 1 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR3 are as shown in (1) in the table below. 2. When an external request is specified as a DMAC activation source, TEND1 output regardless of bits PA1DDR and NDER1. 8-bit timer channel 3 settings CKS2 CKS1 CKS0 0 0 0 1 (2) 1 1 (1)
PA0/TP0/TCLKA/TEND0 277
Table amended
Pin PA0/TP0/ TCLKA/ TEND0 Pin Functions and Selection Method Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR1 of the 8-bit timer, bit NDER0 in NDERA, and bit PA0DDR select the pin function as follows. PA 0DDR NDER0 Pin function 0 PA0 input 0 PA0 output TCLKA input*
1 2
1 1 TP0 output
TEND0 output*
Notes: 1. TCLKA input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0 and TPSC0 = 0 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR0 are as shown in (1) in the table below. 2. When an external request is specified as a DMAC activation source, TEND0 output regardless of bits PA0DDR and NDER0. 8-bit timer channel 1 settings CKS2 CKS1 CKS0 0 0 0 1 (2) 1 1 (1)
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Item 8.8.2 Register Configuration Port B Data Register (PBDR): Table 8.16 Port B Pin Functions PB3/TP11/TMIO3/DREQ1/ CS4 PB2/TP10/TMO2/CS5
Page 281
Revision (See Manual for Details) Description amended The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in 8TCSR3, bits CCLR1 and CCLR0 in 8TCR3, bit CS4E in CSCR, bit NDER11 in NDERB, and bit PB3DDR select the pin function as follows.
282
Table amended
Pin PB2/TP10/ TMO2/CS5 Pin Functions and Selection Method The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in 8TCSR2, bit CS5E in CSCR, bit NDER10 in NDERB, and bit PB2DDR select the pin function as follows. DRAM interface settings OIS3/2 and OS1/0 CS5E PB2DDR NDER10 Pin function 0 PB2 input 0 1 0 PB2 output 1 1 TP10 output (1) in table below (2) in table below Not all 0 1 CS5 output TMO2 output CS5 output*
All 0
PB1/TP9/TMIO1/DREQ0/ CS6
Description amended Bits OIS3/2 and OS1/0 in 8TCSR1, bits CCLR1 and CCLR0 in 8TCR0, bit CS6E in CSCR, bit NDER9 in NDERB, and bit PB1DDR select the pin function as follows. 283 Description amended Bits OIS3/2 and OS1/0 in 8TCSR0, bit CS7E in CSCR, bit NDER8 in NDERB, and bit PB0DDR select the pin function as follows.
PB0/TP8/TMO0/CS7
9.1.4 Register Configuration Table 9.3 16-bit timer Registers
291
Table amended
Channel Common Address* H'FFF64
1
Name Timer interrupt status register A
Abbreviation TISRA
R/W
2
Initial Value
R/(W)* H'88
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Item 9.4.6 Setting Initial Value of 16-Bit Timer Output Figure 9.32 Example of Timing for Setting Initial Value of 16-Bit Timer Output by Writing to TOLR
Page 333
Revision (See Manual for Details) Figure amended
T1 T2 T3
Address bus
TOLR address
TOLR
N
16-bit timer output pin
N
10.2.3 Time Constant 357 Registers B (TCORB)
Note added Note: * When channel 1 and channel 3 are designated for TCORB input capture, the CMFB flag is not set by a channel 0 or channel 2 compare match B. Note added Note: When input capture B is set as the 8TCNT1 and 8TCNT3 counter clear source, 8TCNT0 and 8TCNT2 are not cleared by compare match B. Description replaced
10.2.4 Timer Control Register (8TCR) Bits 4 and 3Counter Clear 1 and 0 (CCLR1, CCLR0): Bits 2 to 0Clock Select 2 to 0 (CSK2 to CSK0):
359
10.2.5 Timer 362 Control/Status Registers (8TCSR) Bit 7Compare Match/Input Capture Flag B (CMFB): Bit 6Compare Match Flag A (CMFA): Bit 4Reserved (In 8TCSR1): Bit 4Input Capture Enable (ICE) (In 8TCSR1 and 8TCSR3): 363
Note added Note: * When bit ICE is set to 1 in 8TCSR1 and 8TCSR3, the CMFB flag is not set when 8TCNT0 = TCORB0 or 8TCNT2 = TCORB2.
Description amended Status flag that indicates the occurrence of a TCORA compare match . Description replaced
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Item 10.4.5 Operation with Cascaded Connection
Page 373
Revision (See Manual for Details) Description amended ...In this case, the timer operates as below. Similarly, if bits CKS2 to CKS0 are set to (100) in either 8TCR2 or 8TCR3, the 8-bit timers of channels 2 and 3 are cascaded. ...
375
Description amended * The OVF flag is set to 1 in 8TCSR3 when the 8-bit counter (8TCNT3) overflows (from H'FF to H'00).
10.4.6 Input Capture Setting
376
Note added Note: When TCORB1 in channel 1 is used for input capture, TCORB0 in channel 0 cannot be used as a compare match register. Similarly, when TCORB3 in channel 3 is used for input capture, TCORB2 in channel 2 cannot be used as a compare match register.
11.3.3 Normal TPC Output Figure 11.4 Setup Procedure for Normal TPC Output (Example) Figure 11.5 Normal TPC Output Example (Five-Phase Pulse Output)
406
Description amended 4. Enable the IMFA interrupt in TISRA. The DMAC can also be set up to transfer data to the next data register.
407
Description amended * The 16-bit timer channel to be used as the output trigger channel is set up so that GRA is an output compare register and the counter will be cleared by compare match A. The trigger period is set in GRA. The IMIEA bit is set to 1 in TISRA to enable the compare match A interrupt.
13.1 Overview
425
Description amended The H8/3006 and H8/3007 have a serial communication interface (SCI) with three independent channels. All three channels have identical functions. The SCI can communicate in both asynchronous and synchronous mode. It also has a multiprocessor communication function for serial communication among two or more processors.
13.2.3 Transmit Shift Register (TSR)
431
Description amended ... If the TDRE flag is set to 1 in SSR, however, the SCI does not load the TDR contents into TSR. The CPU cannot read or write TSR directly.
13.3.4 Synchronous Operation
478
Description amended * The SCI synchronizes with the serial clock input or output and performs receive operation.
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Item 14.3.4 Register Settings Smart Card Mode Register (SCMR) Settings: 14.4 Usage Notes Note on Block Transfer Mode Support:
Page 499
Revision (See Manual for Details) Description amended With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. In the example above, the first character data is H'3B. The parity bit is 1, following the even parity rule designated for smart cards.
511
Description added The smart card interface installed in the H8/3006 and H8/3007 support an IC card (smart card) interface with provision for ISO/IEC7816-3 T=0 (character transmission). Therefore, block transfer operations are not supported (error signal transmission, detection, and automatic data retransmission are not performed).
15.1 Overview
513
Description amended When the A/D converter is not used, it can be halted independently to conserve power. For details see section 19.6, Module Standby Function. The H8/3006 and H8/3007 support 70/134-state conversion as a high-speed conversion mode. Note that it differs in this respect from the H8/3048 Group, which supports 134/266-state conversion.
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) 16.1.3 Pin Configuration Table 16.1 D/A Converter Pins 20.2.2 AC Characteristics Table 20.7 Control Signal Timing 20.3.6 Timer Input/Output Timing
517
Description amended The CPU can always read the A/D data registers.
536
Table amended
Pin Name Analog power supply pin Abbreviation AVCC I/O Input Function Analog power supply and reference voltage
581
Table amended Item NMI, IRQ pulse width (in recovery from software standby mode) Symbol tNMIW
603
Description amended The timings of 16-bit and 8-bit timer are shown as follows: Notes amended Notes: 1. Not available in the H8/3006 and H8/3007. 2. n is the value set in register R4L or R4. The source and destination are accessed n + 1 times each.
A.3 Number of States 633 Required for Execution Table A.4 Number of Cycles per Instruction
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Item C.3 Port 7 Block Diagrams Figure C.3 (b) Port 7 Block Diagram (Pins P76 and P77)
Page 724
Revision (See Manual for Details) Figure amended
P7 n
C.7 Port B Block Diagrams Figure C.7 (e) Port B Block Diagram (Pin PB6)
742
Figure amended
PB6
Figure C.7 (f) Port B 743 Block Diagram (Pin PB7)
Figure amended
RPB
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Item
Page
Revision (See Manual for Details) Table amended
Item 9 H8/3067, H8/3062 Group H8/3048 Group External trigger 134/266 H8/3006, H8/3007 External trigger/8-bit timer compare match 70/134 H8/3002 External trigger 134/266
759 Appendix H Comparison of H8/300H Series Product Specifications H.1 Differences between H8/3067 and H8/3062 Group, H8/3048 Group, H8/3006 and H8/3007, and H8/3002
A/D Conversion start External trigger/8-bit converter trigger input timer compare match Conversion states 70/134
All trademarks and registered trademarks are the property of their respective owners.
Rev.5.00 Sep. 12, 2007 Page xiv of xxviii REJ09B0396-0500
Contents
Section 1 Overview.............................................................................................................
1.1 1.2 1.3 Overview........................................................................................................................... Internal Block Diagram..................................................................................................... Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions ....................................................................................................... 1.3.3 Pin Assignments in Each Mode ........................................................................... 1 1 6 7 7 9 14
Section 2 CPU ...................................................................................................................... 19
2.1 Overview........................................................................................................................... 2.1.1 Features................................................................................................................ 2.1.2 Differences from H8/300 CPU............................................................................. CPU Operating Modes ...................................................................................................... Address Space ................................................................................................................... Register Configuration ...................................................................................................... 2.4.1 Overview.............................................................................................................. 2.4.2 General Registers ................................................................................................. 2.4.3 Control Registers ................................................................................................. 2.4.4 Initial CPU Register Values ................................................................................. Data Formats ..................................................................................................................... 2.5.1 General Register Data Formats ............................................................................ 2.5.2 Memory Data Formats ......................................................................................... Instruction Set ................................................................................................................... 2.6.1 Instruction Set Overview ..................................................................................... 2.6.2 Instructions and Addressing Modes ..................................................................... 2.6.3 Tables of Instructions Classified by Function...................................................... 2.6.4 Basic Instruction Formats .................................................................................... 2.6.5 Notes on Use of Bit Manipulation Instructions.................................................... Addressing Modes and Effective Address Calculation ..................................................... 2.7.1 Addressing Modes ............................................................................................... 2.7.2 Effective Address Calculation.............................................................................. Processing States............................................................................................................... 2.8.1 Overview.............................................................................................................. 2.8.2 Program Execution State...................................................................................... 2.8.3 Exception-Handling State .................................................................................... 2.8.4 Exception-Handling Sequences ........................................................................... 2.8.5 Bus-Released State............................................................................................... 19 19 20 21 22 23 23 24 25 26 27 27 28 30 30 31 32 41 42 44 44 46 50 50 51 51 53 54
2.2 2.3 2.4
2.5
2.6
2.7
2.8
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2.9
2.8.6 Reset State ........................................................................................................... 2.8.7 Power-Down State ............................................................................................... Basic Operational Timing ................................................................................................. 2.9.1 Overview.............................................................................................................. 2.9.2 On-Chip Memory Access Timing........................................................................ 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 2.9.4 Access to External Address Space .......................................................................
54 54 55 55 55 56 57
Section 3 MCU Operating Modes .................................................................................. 59
3.1 Overview........................................................................................................................... 3.1.1 Operating Mode Selection ................................................................................... 3.1.2 Register Configuration......................................................................................... Mode Control Register (MDCR) ...................................................................................... System Control Register (SYSCR) ................................................................................... Operating Mode Descriptions ........................................................................................... 3.4.1 Mode 1 ................................................................................................................. 3.4.2 Mode 2 ................................................................................................................. 3.4.3 Mode 3 ................................................................................................................. 3.4.4 Mode 4 ................................................................................................................. Pin Functions in Each Operating Mode ............................................................................ Memory Map in Each Operating Mode ............................................................................ 3.6.1 Note on Reserved Areas....................................................................................... 59 59 60 60 61 63 63 63 64 64 64 65 65
3.2 3.3 3.4
3.5 3.6
Section 4 Exception Handling ......................................................................................... 69
4.1 Overview........................................................................................................................... 4.1.1 Exception Handling Types and Priority............................................................... 4.1.2 Exception Handling Operation............................................................................. 4.1.3 Exception Vector Table ....................................................................................... Reset.................................................................................................................................. 4.2.1 Overview.............................................................................................................. 4.2.2 Reset Sequence .................................................................................................... 4.2.3 Interrupts after Reset............................................................................................ Interrupts........................................................................................................................... Trap Instruction................................................................................................................. Stack Status after Exception Handling.............................................................................. Notes on Stack Usage ....................................................................................................... 69 69 69 70 72 72 72 74 75 76 76 77
4.2
4.3 4.4 4.5 4.6
Section 5 Interrupt Controller .......................................................................................... 79
5.1 Overview........................................................................................................................... 79 5.1.1 Features................................................................................................................ 79
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5.2
5.3
5.4
5.5
5.1.2 Block Diagram ..................................................................................................... 5.1.3 Pin Configuration................................................................................................. 5.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 5.2.1 System Control Register (SYSCR) ...................................................................... 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 5.2.3 IRQ Status Register (ISR).................................................................................... 5.2.4 IRQ Enable Register (IER) .................................................................................. 5.2.5 IRQ Sense Control Register (ISCR) .................................................................... Interrupt Sources ............................................................................................................... 5.3.1 External Interrupts ............................................................................................... 5.3.2 Internal Interrupts................................................................................................. 5.3.3 Interrupt Vector Table.......................................................................................... Interrupt Operation............................................................................................................ 5.4.1 Interrupt Handling Process................................................................................... 5.4.2 Interrupt Sequence ............................................................................................... 5.4.3 Interrupt Response Time...................................................................................... Usage Notes ...................................................................................................................... 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ...................... 5.5.2 Instructions that Inhibit Interrupts........................................................................ 5.5.3 Interrupts during EEPMOV Instruction Execution ..............................................
80 81 81 82 82 83 89 90 91 92 92 93 93 97 97 102 103 104 104 105 105
Section 6 Bus Controller.................................................................................................... 107
6.1 Overview........................................................................................................................... 6.1.1 Features................................................................................................................ 6.1.2 Block Diagram ..................................................................................................... 6.1.3 Pin Configuration................................................................................................. 6.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 6.2.1 Bus Width Control Register (ABWCR)............................................................... 6.2.2 Access State Control Register (ASTCR) ............................................................. 6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 6.2.4 Bus Release Control Register (BRCR) ................................................................ 6.2.5 Bus Control Register (BCR) ................................................................................ 6.2.6 Chip Select Control Register (CSCR).................................................................. 6.2.7 DRAM Control Register A (DRCRA) ................................................................. 6.2.8 DRAM Control Register B (DRCRB) ................................................................. 6.2.9 Refresh Timer Control/Status Register (RTMCSR) ............................................ 6.2.10 Refresh Timer Counter (RTCNT)........................................................................ 6.2.11 Refresh Time Constant Register (RTCOR) ......................................................... 107 107 108 110 111 112 112 113 113 117 119 121 122 124 127 128 129
6.2
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6.3
Operation .......................................................................................................................... 6.3.1 Area Division....................................................................................................... 6.3.2 Bus Specifications................................................................................................ 6.3.3 Memory Interfaces............................................................................................... 6.3.4 Chip Select Signals .............................................................................................. 6.4 Basic Bus Interface ........................................................................................................... 6.4.1 Overview.............................................................................................................. 6.4.2 Data Size and Data Alignment............................................................................. 6.4.3 Valid Strobes........................................................................................................ 6.4.4 Memory Areas ..................................................................................................... 6.4.5 Basic Bus Control Signal Timing ........................................................................ 6.4.6 Wait Control ........................................................................................................ 6.5 DRAM Interface ............................................................................................................... 6.5.1 Overview.............................................................................................................. 6.5.2 DRAM Space and RAS Output Pin Settings ....................................................... 6.5.3 Address Multiplexing........................................................................................... 6.5.4 Data Bus............................................................................................................... 6.5.5 Pins Used for DRAM Interface............................................................................ 6.5.6 Basic Timing........................................................................................................ 6.5.7 Precharge State Control ....................................................................................... 6.5.8 Wait Control ........................................................................................................ 6.5.9 Byte Access Control and CAS Output Pin........................................................... 6.5.10 Burst Operation.................................................................................................... 6.5.11 Refresh Control.................................................................................................... 6.5.12 Examples of Use .................................................................................................. 6.5.13 Usage Notes ......................................................................................................... 6.6 Interval Timer ................................................................................................................... 6.6.1 Operation ............................................................................................................. 6.7 Interrupt Sources............................................................................................................... 6.8 Burst ROM Interface......................................................................................................... 6.8.1 Overview.............................................................................................................. 6.8.2 Basic Timing........................................................................................................ 6.8.3 Wait Control ........................................................................................................ 6.9 Idle Cycle.......................................................................................................................... 6.9.1 Operation ............................................................................................................. 6.9.2 Pin States in Idle Cycle ........................................................................................ 6.10 Bus Arbiter........................................................................................................................ 6.10.1 Operation ............................................................................................................. 6.11 Register and Pin Input Timing .......................................................................................... 6.11.1 Register Write Timing .........................................................................................
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130 130 132 133 133 134 134 134 136 136 138 145 147 147 147 148 148 149 149 151 152 153 154 160 164 168 170 170 175 176 176 176 177 178 178 181 182 182 185 185
6.11.2 BREQ Pin Input Timing ...................................................................................... 186
Section 7 DMA Controller................................................................................................ 187
7.1 Overview........................................................................................................................... 7.1.1 Features................................................................................................................ 7.1.2 Block Diagram ..................................................................................................... 7.1.3 Functional Overview............................................................................................ 7.1.4 Pin Configuration................................................................................................. 7.1.5 Register Configuration......................................................................................... Register Descriptions (1) (Short Address Mode) .............................................................. 7.2.1 Memory Address Registers (MAR) ..................................................................... 7.2.2 I/O Address Registers (IOAR) ............................................................................. 7.2.3 Execute Transfer Count Registers (ETCR) .......................................................... 7.2.4 Data Transfer Control Registers (DTCR) ............................................................ Register Descriptions (2) (Full Address Mode) ................................................................ 7.3.1 Memory Address Registers (MAR) ..................................................................... 7.3.2 I/O Address Registers (IOAR) ............................................................................. 7.3.3 Execute Transfer Count Registers (ETCR) .......................................................... 7.3.4 Data Transfer Control Registers (DTCR) ............................................................ Operation........................................................................................................................... 7.4.1 Overview.............................................................................................................. 7.4.2 I/O Mode.............................................................................................................. 7.4.3 Idle Mode............................................................................................................. 7.4.4 Repeat Mode ........................................................................................................ 7.4.5 Normal Mode....................................................................................................... 7.4.6 Block Transfer Mode ........................................................................................... 7.4.7 DMAC Activation................................................................................................ 7.4.8 DMAC Bus Cycle ................................................................................................ 7.4.9 Multiple-Channel Operation ................................................................................ 7.4.10 External Bus Requests, DRAM Interface, and DMAC........................................ 7.4.11 NMI Interrupts and DMAC.................................................................................. 7.4.12 Aborting a DMAC Transfer................................................................................. 7.4.13 Exiting Full Address Mode .................................................................................. 7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode.......................... Interrupts ........................................................................................................................... Usage Notes ...................................................................................................................... 7.6.1 Note on Word Data Transfer................................................................................ 7.6.2 DMAC Self-Access ............................................................................................. 7.6.3 Longword Access to Memory Address Registers ................................................ 7.6.4 Note on Full Address Mode Setup ....................................................................... 187 187 188 188 190 190 191 192 192 193 195 198 198 198 199 201 207 207 209 211 214 218 221 226 227 233 234 235 236 237 238 238 239 239 239 240 240
7.2
7.3
7.4
7.5 7.6
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7.6.5 7.6.6 7.6.7 7.6.8 7.6.9
Note on Activating DMAC by Internal Interrupts ............................................... NMI Interrupts and Block Transfer Mode ........................................................... Memory and I/O Address Register Values .......................................................... Bus Cycle when Transfer Is Aborted ................................................................... Transfer Requests by A/D Converter...................................................................
241 242 242 243 243
Section 8 I/O Ports .............................................................................................................. 245
8.1 8.2 Overview........................................................................................................................... Port 4................................................................................................................................. 8.2.1 Overview.............................................................................................................. 8.2.2 Register Configuration......................................................................................... Port 6................................................................................................................................. 8.3.1 Overview.............................................................................................................. 8.3.2 Register Configuration......................................................................................... Port 7................................................................................................................................. 8.4.1 Overview.............................................................................................................. 8.4.2 Register Configuration......................................................................................... Port 8................................................................................................................................. 8.5.1 Overview.............................................................................................................. 8.5.2 Register Configuration......................................................................................... Port 9................................................................................................................................. 8.6.1 Overview.............................................................................................................. 8.6.2 Register Configuration......................................................................................... Port A................................................................................................................................ 8.7.1 Overview.............................................................................................................. 8.7.2 Register Configuration......................................................................................... Port B ................................................................................................................................ 8.8.1 Overview.............................................................................................................. 8.8.2 Register Configuration......................................................................................... 245 248 248 249 251 251 252 255 255 255 256 256 257 261 261 262 265 265 267 277 277 278
8.3
8.4
8.5
8.6
8.7
8.8
Section 9 16-Bit Timer....................................................................................................... 285
9.1 Overview........................................................................................................................... 9.1.1 Features................................................................................................................ 9.1.2 Block Diagrams ................................................................................................... 9.1.3 Pin Configuration................................................................................................. 9.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 9.2.1 Timer Start Register (TSTR) ............................................................................... 9.2.2 Timer Synchro Register (TSNC) ......................................................................... 9.2.3 Timer Mode Register (TMDR) ............................................................................ 285 285 287 290 291 292 292 293 295
9.2
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9.3
9.4
9.5
9.6
9.2.4 Timer Interrupt Status Register A (TISRA)......................................................... 9.2.5 Timer Interrupt Status Register B (TISRB) ......................................................... 9.2.6 Timer Interrupt Status Register C (TISRC) ......................................................... 9.2.7 Timer Counters (16TCNT) .................................................................................. 9.2.8 General Registers (GRA, GRB)........................................................................... 9.2.9 Timer Control Registers (16TCR) ....................................................................... 9.2.10 Timer I/O Control Register (TIOR) ..................................................................... 9.2.11 Timer Output Level Setting Register C (TOLR) ................................................. CPU Interface.................................................................................................................... 9.3.1 16-Bit Accessible Registers ................................................................................. 9.3.2 8-Bit Accessible Registers ................................................................................... Operation........................................................................................................................... 9.4.1 Overview.............................................................................................................. 9.4.2 Basic Functions.................................................................................................... 9.4.3 Synchronization ................................................................................................... 9.4.4 PWM Mode.......................................................................................................... 9.4.5 Phase Counting Mode .......................................................................................... 9.4.6 Setting Initial Value of 16-Bit Timer Output ....................................................... Interrupts ........................................................................................................................... 9.5.1 Setting of Status Flags.......................................................................................... 9.5.2 Timing of Clearing of Status Flags ...................................................................... 9.5.3 Interrupt Sources and DMA Controller Activation.............................................. Usage Notes ......................................................................................................................
297 300 303 305 306 307 310 312 314 314 316 317 317 317 325 327 331 333 334 334 336 336 338
Section 10 8-Bit Timers..................................................................................................... 351
10.1 Overview........................................................................................................................... 10.1.1 Features................................................................................................................ 10.1.2 Block Diagram ..................................................................................................... 10.1.3 Pin Configuration................................................................................................. 10.1.4 Register Configuration......................................................................................... 10.2 Register Descriptions ........................................................................................................ 10.2.1 Timer Counters (8TCNT) .................................................................................... 10.2.2 Time Constant Registers A (TCORA) ................................................................. 10.2.3 Time Constant Registers B (TCORB).................................................................. 10.2.4 Timer Control Register (8TCR) ........................................................................... 10.2.5 Timer Control/Status Registers (8TCSR) ............................................................ 10.3 CPU Interface.................................................................................................................... 10.3.1 8-Bit Registers ..................................................................................................... 10.4 Operation........................................................................................................................... 10.4.1 8TCNT Count Timing.......................................................................................... 351 351 352 353 354 355 355 356 357 358 361 366 366 368 368
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10.4.2 Compare Match Timing....................................................................................... 10.4.3 Input Capture Signal Timing ............................................................................... 10.4.4 Timing of Status Flag Setting .............................................................................. 10.4.5 Operation with Cascaded Connection.................................................................. 10.4.6 Input Capture Setting ........................................................................................... 10.5 Interrupt ............................................................................................................................ 10.5.1 Interrupt Source ................................................................................................... 10.5.2 A/D Converter Activation.................................................................................... 10.6 8-Bit Timer Application Example..................................................................................... 10.7 Usage Notes ...................................................................................................................... 10.7.1 Contention between 8TCNT Write and Clear...................................................... 10.7.2 Contention between 8TCNT Write and Increment .............................................. 10.7.3 Contention between TCOR Write and Compare Match ...................................... 10.7.4 Contention between TCOR Read and Input Capture ........................................... 10.7.5 Contention between Counter Clearing by Input Capture and Counter Increment ............................................................................................... 10.7.6 Contention between TCOR Write and Input Capture .......................................... 10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection) ........................................................................................ 10.7.8 Contention between Compare Matches A and B ................................................. 10.7.9 8TCNT Operation at Internal Clock Source Switchover .....................................
369 371 372 373 375 376 376 377 377 378 378 379 380 381 382 383 384 385 385
Section 11 Programmable Timing Pattern Controller (TPC) ................................. 389
11.1 Overview........................................................................................................................... 11.1.1 Features................................................................................................................ 11.1.2 Block Diagram..................................................................................................... 11.1.3 Pin Configuration................................................................................................. 11.1.4 Register Configuration......................................................................................... 11.2 Register Descriptions ........................................................................................................ 11.2.1 Port A Data Direction Register (PADDR) ........................................................... 11.2.2 Port A Data Register (PADR).............................................................................. 11.2.3 Port B Data Direction Register (PBDDR) ........................................................... 11.2.4 Port B Data Register (PBDR) .............................................................................. 11.2.5 Next Data Register A (NDRA) ............................................................................ 11.2.6 Next Data Register B (NDRB)............................................................................. 11.2.7 Next Data Enable Register A (NDERA).............................................................. 11.2.8 Next Data Enable Register B (NDERB) .............................................................. 11.2.9 TPC Output Control Register (TPCR) ................................................................. 11.2.10 TPC Output Mode Register (TPMR) ................................................................... 11.3 Operation ..........................................................................................................................
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389 389 390 391 392 393 393 393 394 394 395 396 398 399 400 402 404
11.3.1 Overview.............................................................................................................. 11.3.2 Output Timing...................................................................................................... 11.3.3 Normal TPC Output............................................................................................. 11.3.4 Non-Overlapping TPC Output ............................................................................. 11.3.5 TPC Output Triggering by Input Capture ............................................................ 11.4 Usage Notes ...................................................................................................................... 11.4.1 Operation of TPC Output Pins ............................................................................. 11.4.2 Note on Non-Overlapping Output........................................................................
404 405 406 408 410 410 410 411
Section 12 Watchdog Timer............................................................................................. 413
12.1 Overview........................................................................................................................... 12.1.1 Features................................................................................................................ 12.1.2 Block Diagram ..................................................................................................... 12.1.3 Pin Configuration................................................................................................. 12.1.4 Register Configuration......................................................................................... 12.2 Register Descriptions ........................................................................................................ 12.2.1 Timer Counter (TCNT)........................................................................................ 12.2.2 Timer Control/Status Register (TCSR) ................................................................ 12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 12.2.4 Notes on Register Access..................................................................................... 12.3 Operation........................................................................................................................... 12.3.1 Watchdog Timer Operation ................................................................................. 12.3.2 Interval Timer Operation ..................................................................................... 12.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 12.4 Interrupts ........................................................................................................................... 12.5 Usage Notes ...................................................................................................................... 413 413 414 414 415 415 415 416 418 419 420 420 422 422 423 423 424
Section 13 Serial Communication Interface ................................................................ 425
13.1 Overview........................................................................................................................... 13.1.1 Features................................................................................................................ 13.1.2 Block Diagram ..................................................................................................... 13.1.3 Pin Configuration................................................................................................. 13.1.4 Register Configuration......................................................................................... 13.2 Register Descriptions ........................................................................................................ 13.2.1 Receive Shift Register (RSR) .............................................................................. 13.2.2 Receive Data Register (RDR) .............................................................................. 13.2.3 Transmit Shift Register (TSR) ............................................................................. 13.2.4 Transmit Data Register (TDR)............................................................................. 13.2.5 Serial Mode Register (SMR)................................................................................ 425 425 427 428 429 430 430 430 431 431 432
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13.2.6 Serial Control Register (SCR).............................................................................. 13.2.7 Serial Status Register (SSR) ................................................................................ 13.2.8 Bit Rate Register (BRR) ...................................................................................... 13.3 Operation .......................................................................................................................... 13.3.1 Overview.............................................................................................................. 13.3.2 Operation in Asynchronous Mode ....................................................................... 13.3.3 Multiprocessor Communication........................................................................... 13.3.4 Synchronous Operation........................................................................................ 13.4 SCI Interrupts.................................................................................................................... 13.5 Usage Notes ...................................................................................................................... 13.5.1 Notes on Use of SCI ............................................................................................
436 441 446 454 454 457 466 473 481 482 482
Section 14 Smart Card Interface ..................................................................................... 487
14.1 Overview........................................................................................................................... 14.1.1 Features................................................................................................................ 14.1.2 Block Diagram..................................................................................................... 14.1.3 Pin Configuration................................................................................................. 14.1.4 Register Configuration......................................................................................... 14.2 Register Descriptions ........................................................................................................ 14.2.1 Smart Card Mode Register (SCMR) .................................................................... 14.2.2 Serial Status Register (SSR) ................................................................................ 14.2.3 Serial Mode Register (SMR) ............................................................................... 14.2.4 Serial Control Register (SCR).............................................................................. 14.3 Operation .......................................................................................................................... 14.3.1 Overview.............................................................................................................. 14.3.2 Pin Connections ................................................................................................... 14.3.3 Data Format ......................................................................................................... 14.3.4 Register Settings .................................................................................................. 14.3.5 Clock.................................................................................................................... 14.3.6 Transmitting and Receiving Data ........................................................................ 14.4 Usage Notes ...................................................................................................................... 487 487 488 488 489 490 490 492 494 494 495 495 495 496 498 499 501 509
Section 15 A/D Converter................................................................................................. 513
15.1 Overview........................................................................................................................... 15.1.1 Features................................................................................................................ 15.1.2 Block Diagram..................................................................................................... 15.1.3 Pin Configuration................................................................................................. 15.1.4 Register Configuration......................................................................................... 15.2 Register Descriptions ........................................................................................................ 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................
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513 513 514 515 516 516 516
15.3 15.4
15.5 15.6
15.2.2 A/D Control/Status Register (ADCSR) ............................................................... 15.2.3 A/D Control Register (ADCR) ............................................................................ CPU Interface.................................................................................................................... Operation........................................................................................................................... 15.4.1 Single Mode (SCAN = 0)..................................................................................... 15.4.2 Scan Mode (SCAN = 1) ....................................................................................... 15.4.3 Input Sampling and A/D Conversion Time.......................................................... 15.4.4 External Trigger Input Timing ............................................................................. Interrupts ........................................................................................................................... Usage Notes ......................................................................................................................
518 520 522 523 523 525 527 528 528 529
Section 16 D/A Converter................................................................................................. 535
16.1 Overview........................................................................................................................... 16.1.1 Features................................................................................................................ 16.1.2 Block Diagram ..................................................................................................... 16.1.3 Pin Configuration................................................................................................. 16.1.4 Register Configuration......................................................................................... 16.2 Register Descriptions ........................................................................................................ 16.2.1 D/A Data Registers 0 and 1 (DADR0/1).............................................................. 16.2.2 D/A Control Register (DACR) ............................................................................ 16.2.3 D/A Standby Control Register (DASTCR) .......................................................... 16.3 Operation........................................................................................................................... 16.4 D/A Output Control .......................................................................................................... 535 535 536 536 537 537 537 538 539 540 541
Section 17 RAM .................................................................................................................. 543
17.1 Overview........................................................................................................................... 17.1.1 Block Diagram ..................................................................................................... 17.1.2 Register Configuration......................................................................................... 17.2 System Control Register (SYSCR) ................................................................................... 17.3 Operation........................................................................................................................... 543 543 544 544 545
Section 18 Clock Pulse Generator .................................................................................. 547
18.1 Overview........................................................................................................................... 18.1.1 Block Diagram ..................................................................................................... 18.2 Oscillator Circuit............................................................................................................... 18.2.1 Connecting a Crystal Resonator........................................................................... 18.2.2 External Clock Input ............................................................................................ 18.3 Duty Adjustment Circuit ................................................................................................... 18.4 Prescalers .......................................................................................................................... 18.5 Frequency Divider............................................................................................................. 547 547 548 548 550 552 552 552
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18.5.1 Register Configuration......................................................................................... 553 18.5.2 Division Control Register (DIVCR) .................................................................... 553 18.5.3 Usage Notes ......................................................................................................... 554
Section 19 Power-Down State ......................................................................................... 555
19.1 Overview........................................................................................................................... 555 19.2 Register Configuration...................................................................................................... 557 19.2.1 System Control Register (SYSCR) ...................................................................... 557 19.2.2 Module Standby Control Register H (MSTCRH)................................................ 559 19.2.3 Module Standby Control Register L (MSTCRL)................................................. 560 19.3 Sleep Mode ....................................................................................................................... 562 19.3.1 Transition to Sleep Mode..................................................................................... 562 19.3.2 Exit from Sleep Mode.......................................................................................... 562 19.4 Software Standby Mode.................................................................................................... 563 19.4.1 Transition to Software Standby Mode ................................................................. 563 19.4.2 Exit from Software Standby Mode ...................................................................... 563 19.4.3 Selection of Waiting Time for Exit from Software Standby Mode...................... 564 19.4.4 Sample Application of Software Standby Mode.................................................. 565 19.4.5 Note...................................................................................................................... 565 19.5 Hardware Standby Mode .................................................................................................. 566 19.5.1 Transition to Hardware Standby Mode................................................................ 566 19.5.2 Exit from Hardware Standby Mode ..................................................................... 566 19.5.3 Timing for Hardware Standby Mode ................................................................... 566 19.6 Module Standby Function................................................................................................. 567 19.6.1 Module Standby Timing ...................................................................................... 567 19.6.2 Read/Write in Module Standby............................................................................ 567 19.6.3 Usage Notes ......................................................................................................... 567 19.7 System Clock Output Disabling Function......................................................................... 568
Section 20 Electrical Characteristics ............................................................................. 20.1 Absolute Maximum Ratings ............................................................................................. 20.2 Electrical Characteristics................................................................................................... 20.2.1 DC Characteristics ............................................................................................... 20.2.2 AC Characteristics ............................................................................................... 20.2.3 A/D Conversion Characteristics........................................................................... 20.2.4 D/A Conversion Characteristics........................................................................... 20.3 Operational Timing........................................................................................................... 20.3.1 Clock Timing ....................................................................................................... 20.3.2 Control Signal Timing ......................................................................................... 20.3.3 Bus Timing ..........................................................................................................
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569 569 570 570 580 588 590 591 591 592 593
20.3.4 20.3.5 20.3.6 20.3.7 20.3.8
DRAM Interface Bus Timing .............................................................................. TPC and I/O Port Timing..................................................................................... Timer Input/Output Timing ................................................................................. SCI Input/Output Timing ..................................................................................... DMAC Timing.....................................................................................................
599 602 603 604 605
Appendix A Instruction Set .............................................................................................. 607
A.1 A.2 A.3 Instruction List .................................................................................................................. 607 Operation Code Maps ....................................................................................................... 622 Number of States Required for Execution ........................................................................ 625
Appendix B Internal I/O Registers ................................................................................. 634
B.1 B.2 Addresses .......................................................................................................................... 634 Functions........................................................................................................................... 643
Appendix C I/O Port Block Diagrams........................................................................... 719
C.1 C.2 C.3 C.4 C.5 C.6 C.7 Port 4 Block Diagram ....................................................................................................... Port 6 Block Diagrams...................................................................................................... Port 7 Block Diagrams...................................................................................................... Port 8 Block Diagrams...................................................................................................... Port 9 Block Diagrams...................................................................................................... Port A Block Diagrams ..................................................................................................... Port B Block Diagrams ..................................................................................................... 719 720 723 725 729 735 738
Appendix D Pin States ....................................................................................................... 744
D.1 D.2 Port States in Each Mode .................................................................................................. 744 Pin States at Reset ............................................................................................................. 750
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode ............................................................................................... 752 Appendix F List of Product Codes ................................................................................. 753 Appendix G Package Dimensions .................................................................................. 754 Appendix H Comparison of H8/300H Series Product Specifications.................. 757
H.1 H.2 Differences between H8/3067 and H8/3062 Group, H8/3048 Group, H8/3006 and H8/3007, and H8/3002 ...................................................................................................... 757 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B) ....... 760
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1. Overview
Section 1 Overview
1.1 Overview
The H8/3006 and H8/3007 are a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Renesas architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU, enabling easy porting of software from the H8/300 Series. The on-chip system supporting functions include RAM, a 16-bit timer, an 8-bit timer, a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller (DMAC), and other facilities. Four MCU operating modes offer a choice of bus width and address space size. Table 1.1 summarizes the features of the H8/3006 and H8/3007.
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1. Overview
Table 1.1
Feature CPU
Features
Description Upward-compatible with the H8/300 CPU at the object-code level General-register machine * Sixteen 16-bit general registers (also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight 32-bit registers) High-speed operation * * Maximum clock rate: 20 MHz Add/subtract: 100 ns
* Multiply/divide: 700 ns 16-Mbyte address space Instruction features * * * * * Memory 8/16/32-bit data transfer, arithmetic, and logic instructions Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits) Signed and unsigned divide instructions (16 bits / 8 bits, 32 bits / 16 bits) Bit accumulator function Bit manipulation instructions with register-indirect specification of bit positions
H8/3007 * RAM: 4 kbytes H8/3006 * RAM: 2 kbytes Seven external interrupt pins: NMI, IRQ0 to IRQ5 36 internal interrupts Three selectable interrupt priority levels
Interrupt controller
* * *
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1. Overview Feature Bus controller Description * * * * * * * * * DMA controller (DMAC) * * * Address space can be partitioned into eight areas, with independent bus specifications in each area Chip select output available for areas 0 to 7 8-bit access or 16-bit access selectable for each area Two-state or three-state access selectable for each area Selection of two wait modes Number of program wait states selectable for each area Direct connection of burst ROM Direct connection of up to 8-Mbyte DRAM (or DRAM interface can be used as interval timer) Bus arbitration function Maximum four channels available Selection of I/O mode, idle mode, or repeat mode
Short address mode
Can be activated by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, conversion-end interrupts from the A/D converter, transmit-data-empty and receive-data-full interrupts from the SCI, or external requests Full address mode * * * Maximum two channels available Selection of normal mode or block transfer mode Can be activated by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, conversion-end interrupts from the A/D converter, external requests, or auto-request Three 16-bit timer channels, capable of processing up to six pulse outputs or six pulse inputs 16-bit timer counter (channels 0 to 2) Two multiplexed output compare/input capture pins (channels 0 to 2) Operation can be synchronized (channels 0 to 2) PWM mode available (channels 0 to 2) Phase counting mode available (channel 2) DMAC can be activated by compare match/input capture A interrupts (channels 0 to 2)
16-bit timer, 3 channels
* * * * * * *
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1. Overview Feature 8-bit timer, 4 channels Description * * * Programmable timing pattern controller (TPC) * * * * Watchdog timer (WDT), 1 channel Serial communication interface (SCI), 3 channels A/D converter * * * * * * * * * * * * * D/A converter * * * I/O ports * * 8-bit up-counter (external event count capability) Two time constant registers Two channels can be connected Maximum 16-bit pulse output, using 16-bit timer as time base Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups) Non-overlap mode available Output data can be transferred by DMAC Internal reset signal can be generated by overflow Reset signal can be output externally Usable as an interval timer Selection of asynchronous or synchronous mode Full duplex: can transmit and receive simultaneously On-chip baud-rate generator Smart card interface functions added Resolution: 10 bits Eight channels, with selection of single or scan mode Variable analog conversion voltage range Sample-and-hold function A/D conversion can be started by an external trigger or 8-bit timer comparematch DMAC can be activated by an A/D conversion end interrupt Resolution: 8 bits Two channels D/A outputs can be sustained in software standby mode 35 input/output pins 12 input-only pins
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1. Overview Feature Operating modes Description Four MCU operating modes Mode Mode 1 Mode 2 Mode 3 Mode 4 Power-down state * * * * * Other features Product lineup * Address Space Address Pins Initial Bus Width Max. Bus Width 1 Mbyte 1 Mbyte 16 Mbytes 16 Mbytes A19 to A0 A19 to A0 A23 to A0 A23 to A0 8 bits 16 bits 8 bits 16 bits 16 bits 16 bits 16 bits 16 bits
Sleep mode Software standby mode Hardware standby mode Module standby function Programmable system clock frequency division On-chip clock pulse generator Model 5 V 10% (5 V) HD6413007F HD6413007TE HD6413007FP 2.7 to 5.5 V (Low voltage) HD6413007VF HD6413007VTE HD6413007VFP Package 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100A) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100A) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100A) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100A)
Part No. H8/3007
H8/3006
5 V 10% (5 V)
HD6413006F HD6413006TE HD6413006FP
2.7 to 5.5 V (Low voltage)
HD6413006VF HD6413006VTE HD6413006VFP
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1. Overview
1.2
Internal Block Diagram
Figure 1.1 shows an internal block diagram.
P47 /D7 P46 /D6 P45 /D5 P44 /D4 P43 /D3 P42 /D2 P41 /D1 P40 /D0 VCC VCC VCC VSS VSS VSS VSS VSS VSS D15 D14 D13 D12 D11 D10
D9
Data bus Address bus MD2 MD1 MD0 EXTAL XTAL STBY RES RESO NMI AS RD HWR LWR /P67
Port 6 Clock pulse generator
D8
Port 4
Data bus (upper) Data bus (lower)
A19 A18 A17 A16 A15 A14 A13
Address bus Port 9
H8/300H CPU
A12 A11 A10 A9 A8 A7 A6 A5 A4
Interrupt controller DMA controller (DMAC)
BACK/P62 BREQ/P61 WAIT/P60
Bus controller
RAM
A3 A2 A1 A0
CS0/P84 CS2/IRQ2/P82 CS3/IRQ1/P81 RFSH/IRQ0/P80
Port 8
ADTRG/CS1/IRQ3/P83
Watchdog timer (WDT) 16-bit timer unit Serial communication interface (SCI) x 3 channels A/D converter D/A converter
8-bit timer unit
P95 /SCK 1 /IRQ 5 P94 /SCK 0 /IRQ 4 P93 /RxD1 P92 /RxD0 P91 /TxD 1 P90 /TxD 0
Programmable timing pattern controller (TPC)
Port B
RxD2/TP15/PB7 TxD2/TP14/PB6 SCK2/LCAS/TP13/PB5 UCAS/TP12/PB4 CS4/DREQ1/TMIO3/TP11/PB3 CS5/TMO2/TP10/PB2 CS6/DREQ0/TMIO1/TP9/PB1 CS7/TMO0/TP8/PB0 A20/TIOCB2/TP7/PA7 A21/TIOCA2/TP6/PA6 A22/TIOCB1/TP5/PA5
Port A
AVCC A23/TIOCA1/TP4/PA4 TCLKD/TIOCB0/TP3/PA3 TCLKC/TIOCA0/TP2/PA2 TEND1/TCLKB/TP1/PA1 TEND0/TCLKA/TP0/PA0 AVSS VREF DA1/AN7/P77 DA0/AN6/P76 AN5/P75
Port 7
AN4/P74 AN3/P73 AN2/P72 AN1/P71 AN0/P70
Figure 1.1 Block Diagram
Rev.5.00 Sep. 12, 2007 Page 6 of 764 REJ09B0396-0500
1. Overview
1.3
1.3.1
Pin Description
Pin Arrangement
The pin arrangement of the H8/3006, H8/3007 FP-100B and TFP-100B packages is shown in figure 1.2, and that of the FP-100A package in figure 1.3.
P61 /BREQ P62 /BACK P60 /WAIT
EXTAL
STBY
P67/
XTAL
HWR
LWR
RES
MD2
MD1
MD0
VCC
NMI
VSS
VSS
A19
A18
A17
A16 53
A15 52
RD
75
74
73
72
71
70
69
AS
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS P80/IRQ0/RFSH P81/IRQ1/CS3 P82/IRQ2/CS2 P83/IRQ3/CS1/ADTRG P84/CS0 VSS PA0/TP0/TCLKA/TEND0 PA1/TP1/TCLKB/TEND1 PA2/TP2/TIOCA0/TCLKC PA3/TP3/TIOCB0/TCLKD PA4/TP4/TIOCA1/A23 PA5/TP5/TIOCB1/A22 PA6/TP6/TIOCA2/A21 PA7/TP7/TIOCB2/A20
51
A14
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
1 2
50 49 48 47 46 45 44 43 42 41 40 Top view (FP-100B, TFP-100B) 39 38 37 36 35 34 33 32 31 30 29 28 INDEX
10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 11 3 4 5 6 7 8 9
A13 A12 A11 A10 A9 A8 VSS A7 A6 A5 A4 A3 A2 A1 A0 VCC D15 D14 D13 D12 D11 D10 D9 D8 D7/P47
27 26
TxD0 /P90
TxD1 /P91
RxD0 /P92
RxD1 /P93
IRQ4 /SCK0 /P94
IRQ5 /SCK1 /P95
D0 /P40
D1 /P41
D2 /P42
CS7/TMO0/TP8/PB0
CS6/DREQ0/TMIO1/TP9/PB1
CS5/TMO2/TP10/PB2
CS4/DREQ1/TMIO3/TP11/PB3
UCAS/TP12/PB4
SCK2/LCAS/TP13/PB5
TxD2/TP14/PB6
RxD2/TP15/PB7
D3 /P43
RESO VSS
VCC
VSS
D4 /P44
D5 /P45
Figure 1.2 Pin Arrangement (FP-100B or TFP-100B, Top View)
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D6 /P46
1. Overview
P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS P80/IRQ0/RFSH P81/IRQ1/CS3 P82/IRQ2/CS2 P83/IRQ3/CS1/ADTRG P84/CS0 VSS PA0/TP0/TCLKA/TEND0 PA1/TP1/TCLKB/TEND1 PA2/TP2/TIOCA0/TCLKC PA3/TP3/TIOCB0/TCLKD PA4/TP4/TIOCA1/A23 PA5/TP5/TIOCB1/A22 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
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Top view (FP-100A)
Figure 1.3 Pin Arrangement (FP-100A, Top View)
A21/TIOCA2 /TP6 /PA6 A20/TIOCB2 /TP7 /PA7 V CC CS7 /TMO0 /TP8 /PB0 CS6 /DREQ 0 /TMIO1 /TP9 /PB1 CS 5 /TMO 2 /TP10 /PB2 CS 4 /DREQ 1 /TMIO 3 /TP11/PB3 UCAS/TP12 /PB4 SCK 2 /LCAS/TP13 /PB5 TxD 2 /TP14 /PB6 RxD 2 /TP15 /PB 7 RESO VSS TxD0 /P90 TxD1 /P91 RxD 0 /P9 2 RxD 1 /P9 3 IRQ 4 /SCK 0 /P94 IRQ 5 /SCK 1 /P95 D0 /P4 0 D1 /P41 D2 /P42 D3 /P43 V SS D4/P44 D5/P45 D6/P46 D7/P47 D8 D9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 A11 A10 A9 A8 VSS A7 A6 A5 A4 A3 A2 A1 A0 VCC D15 D14 D13 D12 D11 D10
P70/AN0 VREF AVCC MD2 MD1 MD0 LWR HWR RD AS VCC XTAL EXTAL VSS NMI RES STBY P67/ P62/BACK P61/BREQ P60/WAIT VSS A19 A18 A17 A16 A15 A14 A13 A12
1. Overview
1.3.2
Pin Functions
Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions
Pin No. Type Power Symbol VCC FP-100B TFP-100B FP-100A I/O 1, 35, 68 3, 37, 70 Input Name and Function Power: For connection to the power supply. Connect all VCC pins to the system power supply. Ground: For connection to ground (0 V). Connect all VSS pins to the 0-V system power supply. For connection to a crystal resonator. For examples of crystal resonator and external clock input, see section 18, Clock Pulse Generator. For connection to a crystal resonator or input of an external clock signal. For examples of crystal resonator and external clock input, see section 18, Clock Pulse Generator.
VSS
11, 22, 44, 57, 65, 92 67
13, 24, 46, 59, 67, 94 69
Input
Clock
XTAL
Input
EXTAL
66
68
Input
Operating MD2 to mode MD0 control
61 75 to 73
63
Output System clock: Supplies the system clock to external devices. Mode 2 to mode 0: For setting the operating mode, as follows. Inputs at these pins must not be changed during operation. MD2 0 0 0 0 1 1 1 1 MD1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 Operating Mode Mode 1 Mode 2 Mode 3 Mode 4
77 to 75 Input
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1. Overview Pin No. Type System control Symbol RES RESO FP-100B TFP-100B FP-100A I/O 63 10 65 12 Input Name and Function Reset input: When driven low, this pin resets the chip.
Output Reset output: Outputs the reset signal generated by the watchdog timer to external devices Input Input Standby: When driven low, this pin forces a transition to hardware standby mode. Bus request: Used by an external bus master to request the bus right
STBY BREQ BACK
62 59 60
64 61 62
Output Bus request acknowledge: Indicates that the bus has been granted to an external bus master Input Nonmaskable interrupt: Requests a nonmaskable interrupt Interrupt request 5 to 0: Maskable interrupt request pins
Interrupts NMI IRQ5 to IRQ0 Address bus A23 to A0
64 17, 16, 90 to 87
66
19, 18, Input 92 to 89
100 to 97, 99, 100, Output Address bus: Outputs address signals 56 to 45, 1, 2, 43 to 36 58 to 47, 45 to 38 34 to 23, 21 to 18 2 to 5, 88 to 91 69 70 71 36 to 25, Input/ Data bus: Bidirectional data bus 23 to 20 output 4 to 7, Output Chip select: Select signals for areas 7 to 0 90 to 93 71 72 73 Output Address strobe: Goes low to indicate valid address output on the address bus Output Read: Goes low to indicate reading from the external address space Output High write: Goes low to indicate writing to the external address space; indicates valid data on the upper data bus (D15 to D8). Output Low write: Goes low to indicate writing to the external address space; indicates valid data on the lower data bus (D7 to D0). Input Wait: Requests insertion of wait states in bus cycles during access to the external address space
Data bus Bus control
D15 to D0 CS7 to CS0 AS RD HWR
LWR
72
74
WAIT
58
60
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1. Overview Pin No. Type DRAM interface Symbol RFSH CS2 to CS5 RD HWR UCAS LWR LCAS DMA controller (DMAC) DREQ1, DREQ0 TEND1, TEND0 FP-100B TFP-100B FP-100A I/O 87 89 Name and Function
Output Refresh: Indicates a refresh cycle Output Row address strobe RAS: Row address strobe signal for DRAM Output Write enable WE: Write enable signal for DRAM Output Upper column address strobe UCAS: Column address strobe signal for DRAM Output Lower column address strobe LCAS: Column address strobe signal for DRAM Input DMA request 1 and 0: DMAC activation requests
89, 88, 5, 91, 90, 4 7, 6 70 71 6 72 7 5, 3 94, 93 72 73 8 74 9 7, 5 96, 95 98 to95
Output Transfer end 1 and 0: These signals indicate that the DMAC has ended a data transfer. Input Clock input D to A: External clock inputs
16-bit timer
TCLKD to 96 to 93 TCLKA
TIOCA2 to 99, 97, 95 1, 99, 97 Input/ Input capture/output compare A2 to A0: TIOCA0 output GRA2 to GRA0 output compare or input capture, or PWM output TIOCB2 to 100, 98, TIOCB0 96 8-bit timer TMO0, TMO2 TMIO1, TMIO3 2, 4 3, 5 2, 100, 98 4, 6 5, 7 Input/ Input capture/output compare B2 to B0: output GRB2 to GRB0 output compare or input capture, or PWM output Output Compare match output: Compare match output pins Input/ Input capture input/compare match output: output Input capture input or compare match output pins Counter external clock input: These pins input an external clock to the counters.
TCLKD to 96 to 93 TCLKA
98 to 95 Input
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1. Overview Pin No. Type Symbol FP-100B TFP-100B FP-100A I/O 9 to 2, 11 to 4, 100 to 93 2, 1, 100 to 95 Name and Function
Program- TP15 to mable TP0 timing pattern controller (TPC) Serial communication interface (SCI) TxD2 to TxD0 RxD2 to RxD0 SCK2 to SCK0 A/D AN7 to converter AN0 ADTRG
Output TPC output 15 to 0: Pulse output
8, 13, 12 9, 15, 14 7, 17, 16 85 to 78 90
10, 15, 14 11, 17, 16
Output Transmit data (channels 0, 1, 2): SCI data output Input Receive data (channels 0, 1, 2): SCI data input
9, 19, 18 Input/ Serial clock (channels 0, 1, 2): SCI clock output input/output 87 to 80 Input 92 Input Analog 7 to 0: Analog input pins A/D conversion external trigger input: External trigger input for starting A/D conversion
D/A DA1, DA0 converter A/D and AVCC D/A converters AVSS VREF
85, 84 76
87, 86 78
Output Analog output: Analog output from the D/A converter Input Power supply pin for the A/D and D/A converters. Connect to the system power supply when not using the A/D and D/A converters. Ground pin for the A/D and D/A converters. Connect to system ground (0 V). Reference voltage input pin for the A/D and D/A converters. Connect to the system power supply when not using the A/D and D/A converters.
86 77
88 79
Input Input
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1. Overview Pin No. Type I/O ports Symbol FP-100B TFP-100B FP-100A I/O Name and Function
P47 to P40 26 to 23, 21 to 18 P67, 61 to 58 P62 to P60 P77 to P70 85 to 78 P84 to P80 91 to 87
28 to 25, Input/ Port 4: Eight-bit input/output pins. The 23 to 20 output direction of each-bit pin can be selected in the port 4 data direction register (P4DDR). 63 to 60 Input/ Port 6: Four-bit input/output pins. The output direction of each-bit pin can be selected in the port 6 data direction register (P6DDR). 87 to 80 Input Port 7: Eight-bit input pins
93 to 89 Input/ Port 8: Five-bit input/output pins. The direction output of each-bit pin can be selected in the port 8 data direction register (P8DDR). 19 to 14 Input/ Port 9: Six-bit input/output pins. The direction output of each-bit pin can be selected in the port 9 data direction register (P9DDR). Input/ Port A: Eight-bit input/output pins. The output direction of each-bit pin can be selected in the port A data direction register (PADDR). Input/ Port B: Eight-bit input/output pins. The output direction of each-bit pin can be selected in the port B data direction register (PBDDR).
P95 to P90 17 to 12
PA7 to PA0 PB7 to PB0
100 to 93 2, 1, 100 to 95 9 to 2 11 to 4
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1. Overview
1.3.3
Pin Assignments in Each Mode
Table 1.3 lists the pin assignments in each mode. Table 1.3 Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A)
Pin Name Mode 1 VCC PB0/TP8/TMO0/ CS7 PB1/TP9/TMIO1/ DREQ0/CS6 PB2/TP10/TMO2/ CS5 PB3/TP11/TMIO3/ DREQ1/CS4 PB4/TP12/UCAS PB5/TP13/LCAS/ SCK2 PB6/TP14/TxD2 PB7/TP15/RxD2 RESO VSS P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94 /IRQ4 /SCK0 P95/IRQ5 /SCK1 P40/D0* P41/D1* P42/D2* P43/D3* VSS P44/D4*
1 1 1 1 1
Pin No. FP-100B TFP-100B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 FP-100A 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Mode 2 VCC
Mode 3 VCC PB0/TP8/TMO0/ CS7 PB1/TP9/TMIO1/ DREQ0/CS6 PB2/TP10/TMO2/ CS5 PB3/TP11/TMIO3/ DREQ1/CS4 PB4/TP12/UCAS PB5/TP13/LCAS/ SCK2 PB6/TP14/TxD2 PB7/TP15/RxD2 RESO VSS P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94 /IRQ4 /SCK0 P95/IRQ5 /SCK1 P40/D0* P41/D1* P42/D2* P43/D3* VSS P44/D4*
1 1 1 1
Mode 4 VCC PB0/TP8/TMO0/ CS7 PB1/TP9/TMIO1/ DREQ0/CS6 PB2/TP10/TMO2/ CS5 PB3/TP11/TMIO3/ DREQ1/CS4 PB4/TP12/UCAS PB5/TP13/LCAS/ SCK2 PB6/TP14/TxD2 PB7/TP15/RxD2 RESO VSS P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94 /IRQ4 /SCK0 P95/IRQ5 /SCK1 P40/D0* P41/D1* P42/D2* P43/D3* VSS P44/D4*
2 2 2 2
PB0/TP8/TMO0/ CS7 PB1/TP9/TMIO1/ DREQ0/CS6 PB2/TP10/TMO2/ CS5 PB3/TP11/TMIO3/ DREQ1/CS4 PB4/TP12/UCAS PB5/TP13/LCAS/ SCK2 PB6/TP14/TxD2 PB7/TP15/RxD2 RESO VSS P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94 /IRQ4 /SCK0 P95/IRQ5 /SCK1 P40/D0* P41/D1* P42/D2* P43/D3* VSS P44/D4*
2 2 2 2 2
1
2
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1. Overview Pin No. FP-100B TFP-100B 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 FP-100A 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Mode 1 P45/D5* P46/D6* P47/D7* D8 D9 D10 D11 D12 D13 D14 D15 VCC A0 A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
1 1 1
Pin Name Mode 2 P45/D5* P46/D6* P47/D7* D8 D9 D10 D11 D12 D13 D14 D15 VCC A0 A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
2 2 2
Mode 3 P45/D5* P46/D6* P47/D7* D8 D9 D10 D11 D12 D13 D14 D15 VCC A0 A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
1 1 1
Mode 4 P45/D5* P46/D6* P47/D7* D8 D9 D10 D11 D12 D13 D14 D15 VCC A0 A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
2 2 2
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1. Overview Pin No. FP-100B TFP-100B 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 FP-100A 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Mode 1 A18 A19 VSS P60/WAIT P61/BREQ P62/BACK P67/ STBY RES NMI VSS EXTAL XTAL VCC AS RD HWR LWR MD0 MD1 MD2 AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 Mode 2 A18 A19 VSS P60/WAIT P61/BREQ P62/BACK P67/ STBY RES NMI VSS EXTAL XTAL VCC AS RD HWR LWR MD0 MD1 MD2 AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 Pin Name Mode 3 A18 A19 VSS P60/WAIT P61/BREQ P62/BACK P67/ STBY RES NMI VSS EXTAL XTAL VCC AS RD HWR LWR MD0 MD1 MD2 AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 Mode 4 A18 A19 VSS P60/WAIT P61/BREQ P62/BACK P67/ STBY RES NMI VSS EXTAL XTAL VCC AS RD HWR LWR MD0 MD1 MD2 AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1
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1. Overview Pin No. FP-100B TFP-100B 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 FP-100A 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 Mode 1 AVSS P80/IRQ0/RFSH P81/IRQ1/CS3 P82/IRQ2/CS2 P83/IRQ3/CS1/ ADTRG P84/CS0 VSS Mode 2 AVSS P80/IRQ0/RFSH P81/IRQ1/CS3 P82/IRQ2/CS2 P83/IRQ3/CS1/ ADTRG P84/CS0 VSS Pin Name Mode 3 AVSS P80/IRQ0/RFSH P81/IRQ1/CS3 P82/IRQ2/CS2 P83/IRQ3/CS1/ ADTRG P84/CS0 VSS Mode 4 AVSS P80/IRQ0/RFSH P81/IRQ1/CS3 P82/IRQ2/CS2 P83/IRQ3/CS1/ ADTRG P84/CS0 VSS
PA0/TP0/TCLKA/ PA0/TP0/TCLKA/ PA0/TP0/TCLKA/ PA0/TP0/TCLKA/ TEND0 TEND0 TEND0 TEND0 PA1/TP1/TCLKB/ PA1/TP1/TCLKB/ PA1/TP1/TCLKB/ PA1/TP1/TCLKB/ TEND1 TEND1 TEND1 TEND1 PA2/TP2/TIOCA0/ PA2/TP2/TIOCA0/ PA2/TP2/TIOCA0/ PA2/TP2/TIOCA0/ TCLKC TCLKC TCLKC TCLKC PA3/TP3/TIOCB0/ PA3/TP3/TIOCB0/ PA3/TP3/TIOCB0/ PA3/TP3/TIOCB0/ TCLKD TCLKD TCLKD TCLKD PA4/TP4/TIOCA1 PA5/TP5/TIOCB1 PA6/TP6/TIOCA2 PA7/TP7/TIOCB2 PA4/TP4/TIOCA1 PA5/TP5/TIOCB1 PA6/TP6/TIOCA2 PA7/TP7/TIOCB2 PA4/TP4/TIOCA1/ PA4/TP4/TIOCA1/ A23 A23 PA5/TP5/TIOCB1/ PA5/TP5/TIOCB1/ A22 A22 PA6/TP6/TIOCA2/ PA6/TP6/TIOCA2/ A21 A21 A20 A20
Notes: 1. In modes 1 and 3, the P40 to P47 functions of pins P40/D0 to P47/D7 are selected after a reset, but they can be changed by software. 2. In modes 2 and 4, the D0 to D7 functions of pins P40/D0 to P47/D7 are selected after a reset, but they can be changed by software.
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1. Overview
Rev.5.00 Sep. 12, 2007 Page 18 of 764 REJ09B0396-0500
2. CPU
Section 2 CPU
2.1 Overview
The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 2.1.1 Features
The H8/300H CPU has the following features. * Upward compatibility with H8/300 CPU Can execute H8/300 Series object programs * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * Sixty-two basic instructions 8/16/32-bit data transfer, arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, or @aa:24] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8, PC) or @(d:16, PC)] Memory indirect [@@aa:8] * 16-Mbyte linear address space
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2. CPU
* High-speed operation All frequently-used instructions execute in two to four states Maximum clock frequency: 8 x 8-bit register-register multiply: 16 / 8-bit register-register divide: 16 x 16-bit register-register multiply: 32 / 16-bit register-register divide: * Two CPU operating modes Normal mode (not available in the H8/3006 and H8/3007) Advanced mode * Low-power mode Transition to power-down state by SLEEP instruction 2.1.2 Differences from H8/300 CPU 20 MHz 700 ns 700 ns 1.1 s 1.1 s 8/16/32-bit register-register add/subtract: 100 ns
In comparison to the H8/300 CPU, the H8/300H has the following enhancements. * More general registers Eight 16-bit registers have been added. * Expanded address space Advanced mode supports a maximum 16-Mbyte address space. Normal mode supports the same 64-kbyte address space as the H8/300 CPU. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Data transfer, arithmetic, and logic instructions can operate on 32-bit data. Signed multiply/divide instructions and other instructions have been added.
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2. CPU
2.2
CPU Operating Modes
The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes.
Normal mode* Maximum 64 kbytes, program and data areas combined
CPU operating modes Maximum 16 Mbytes, program and data areas combined
Advanced mode
Note: * Normal mode is not available in the H8/3006 and H8/3007.
Figure 2.1 CPU Operating Modes
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2. CPU
2.3
Address Space
Figure 2.2 shows a simple memory map for the H8/3006 and H8/3007. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode. The 1-Mbyte operating modes use 20-bit addressing. The upper 4 bits of effective addresses are ignored.
H'0000 H'FFFF H'FFFFF H'00000 H'000000
H'FFFFFF a. 1-Mbyte mode Normal mode* b. 16-Mbyte mode Advanced mode
Note: * Normal mode is not available in the H8/3006 and H8/3007.
Figure 2.2 Memory Map
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2. CPU
2.4
2.4.1
Register Configuration
Overview
The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers.
General Registers (ERn) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 Control Registers (CR) 23 PC 76543210 CCR I UI H U N Z V C Legend: SP: Stack pointer PC: Program counter CCR: Condition code register Interrupt mask bit I: User bit or interrupt mask bit UI: Half-carry flag H: User bit U: Negative flag N: Zero flag Z: Overflow flag V: Carry flag C: 0 E0 E1 E2 E3 E4 E5 E6 E7 (SP) 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0
Figure 2.3 CPU Registers
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2. CPU
2.4.2
General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2.4 illustrates the usage of the general registers. The usage of each register can be selected independently.
* Address registers * 32-bit registers
* 16-bit registers E registers (extended registers) E0 to E7
* 8-bit registers
ER registers ER0 to ER7 R registers R0 to R7
RH registers R0H to R7H
RL registers R0L to R7L
Figure 2.4 Usage of General Registers
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General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack.
Free area SP (ER7) Stack area
Figure 2.5 Stack 2.4.3 Control Registers
The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR). Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word) or a multiple of 2 bytes, so the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0. Condition Code Register (CCR): This 8-bit register contains internal CPU status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7--Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. Bit 6--User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details see section 5, Interrupt Controller. Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.
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Bit 4--User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3--Negative Flag (N): Stores the value of the most significant bit of data, regarded as the sign bit. Bit 2--Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry is generated by execution of an operation, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional branch (Bcc) instructions. For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and UI bits, see section 5, Interrupt Controller. 2.4.4 Initial CPU Register Values
In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the initial value of the stack pointer (ER7) is also undefined. The stack pointer (ER7) must therefore be initialized by an MOV.L instruction executed immediately after a reset.
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2.5
Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats
Figures 2.6 and 2.7 show the data formats in general registers.
General Register
Data Type
Data Format 7 0 Don't care 7 0
1-bit data
RnH
76543210
1-bit data
RnL 7
Don't care 43 0
76543210
4-bit BCD data
RnH
Upper digit Lower digit
Don't care 7 43 0
4-bit BCD data
RnL 7
Don't care 0
Upper digit Lower digit
Byte data
RnH MSB LSB 7
Don't care 0 LSB
Byte data
RnL
Don't care MSB
Legend: RnH: General register RH RnL: General register RL
Figure 2.6 General Register Data Formats (1)
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General Register
Data Type
Data Format 15 0 LSB
Word data
Rn MSB 15 0 LSB 16 15 0 LSB
Word data
En MSB 31
Longword data ERn MSB Legend :: ERn: General register En: General register E Rn: General register R MSB: Most significant bit LSB: Least significant bit
Figure 2.7 General Register Data Formats (2) 2.5.2 Memory Data Formats
Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
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Data Type Address Data Format
7 1-bit data Byte data Word data Address L Address L Address 2M Address 2M + 1 Address 2N Longword data Address 2N + 1 Address 2N + 2 Address 2N + 3
MSB
0 6 5 4 3 2 1 0
LSB
7
MSB
MSB LSB
LSB
Figure 2.8 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size.
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2.6
2.6.1
Instruction Set
Instruction Set Overview
The H8/300H CPU has 64 types of instructions, which are classified in table 2.1. Table 2.1
Function Data transfer Arithmetic operations Logic operations Shift operations Bit manipulation Branch System control Block data transfer
Instruction Classification
Instruction MOV, PUSH* , POP* , MOVTPE* , MOVFPE*
1 1 2 2
Types 5
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, 18 MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 4 8
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, 14 BIXOR, BLD, BILD, BST, BIST Bcc* , JMP, BSR, JSR, RTS TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV
3
5 9 1 Total 64 types
Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn. PUSH.W Rn is identical to MOV.W Rn, @-SP. POP.L ERn is identical to MOV.L @SP+, Rn. PUSH.L ERn is identical to MOV.L Rn, @-SP. 2. Not available in the H8/3006 and H8/3007. 3. Bcc is a generic branching instruction.
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2.6.2
Instructions and Addressing Modes
Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes
Addressing Modes @ (d:16, ERn) BWL @ (d:24, ERn) BWL @ (d:8, PC) @ (d:16, PC)
Function Data transfer
Instruction MOV POP, PUSH MOVFPE, MOVTPE
#xx BWL BWL WL B
Rn BWL BWL BWL B L BWL B BW
@ERn BWL
@ERn+/ @-ERn BWL
@ aa:8 B
@ aa:16 BWL
@ aa:24 BWL
@@ aa:8
WL
Arithmetic operations
ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, MULXS, DIVXU, DIVXS NEG EXTU, EXTS

BWL WL BWL BWL BWL B B B
B

W W
W W
B
W W

Logic operations
AND, OR, XOR NOT B B
Shift instructions Bit manipulation Branch Bcc, BSR JMP, JSR RTS System control TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP Block data transfer
W W
W W
W W

BW
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2.6.3
Tables of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation
Rd Rs Rn ERn (EAd) (EAs) CCR N Z V C PC SP #IMM disp + - x / :3/:8/:16/:24 Note: * General register (destination)* General register (source)* General register* General register (32-bit register or address register) Destination operand Source operand Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move NOT (logical complement) 3-, 8-, 16-, or 24-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).
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Table 2.3
Data Transfer Instructions
Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
Instruction Size* MOV B/W/L
MOVFPE MOVTPE POP
B B W/L
(EAs) Rd Cannot be used in this LSI. Rs (EAs) Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. Similarly, POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH
W/L
Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. Similarly, PUSH.L ERn is identical to MOV.L ERn, @-SP.
Note:
* B: W: L:
Size refers to the operand size. Byte Word Longword
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Table 2.4
Arithmetic Operation Instructions
Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register. Use the SUBX or ADD instruction.)
Instruction Size* ADD,SUB B/W/L
ADDX, SUBX INC, DEC ADDS, SUBS DAA, DAS MULXU
B
Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on data in two general registers, or on immediate data and data in a general register.
B/W/L
Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.)
L B
Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to CCR to produce 4-bit BCD data.
B/W
Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits.
MULXS
B/W
Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits.
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2. CPU Instruction Size* DIVXU B/W Function Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder DIVXS B/W Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder, or 32 bits / 16 bits 16-bit quotient and 16-bit remainder CMP B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR according to the result. NEG B/W/L 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTS W/L Rd (sign extension) Rd Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by extending the sign bit. EXTU W/L Rd (zero extension) Rd Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by padding with zeros. Note: * B: W: L: Size refers to the operand size. Byte Word Longword
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Table 2.5
Logic Operation Instructions
Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data.
Instruction Size* AND B/W/L
OR
B/W/L
Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data.
XOR
B/W/L
Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data.
NOT
B/W/L
Rd Rd Takes the one's complement (logical complement) of general register contents.
Note:
* B: W: L:
Size refers to the operand size. Byte Word Longword
Table 2.6
Shift Instructions
Function Rd (shift) Rd Performs an arithmetic shift on general register contents. B/W/L B/W/L B/W/L Rd (shift) Rd Performs a logical shift on general register contents. Rd (rotate) Rd Rotates general register contents. Rd (rotate) Rd Rotates general register contents, including the carry bit. Size refers to the operand size. Byte Word Longword
Instruction Size* SHAL, SHAR SHLL, SHLR ROTL, ROTR ROTXL, ROTXR Note: * B: W: L: B/W/L
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Table 2.7
Bit Manipulation Instructions
Function 1 ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
Instruction Size* BSET B
BCLR
B
0 ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
BNOT
B
( of ) ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
BTST
B
( of ) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
BAND
B
C ( of ) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BIAND
B
C [ ( of )] C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
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2. CPU Instruction Size* BOR B Function C ( of ) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BIOR B C [ ( of )] C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BXOR B C ( of ) C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BIXOR B C [ ( of )] C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B ( of ) C Transfers a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BILD B ( of ) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST B C ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. BIST B C ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Note: * Size refers to the operand size. B: Byte
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Table 2.8
Branching Instructions
Function Branches to a specified address if address specified condition is met. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS Bcc (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Condition Always Never CZ=0 CZ=1
Instruction Size Bcc
Carry clear (high or same) C = 0 Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1
JMP BSR JSR RTS

Branches unconditionally to a specified address Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine
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Table 2.9
System Control Instructions
Function Starts trap-instruction exception handling Returns from an exception-handling routine Causes a transition to the power-down state (EAs) CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access.
Instruction Size* TRAPA RTE SLEEP LDC B/W
STC
B/W
CCR (EAd) Transfers the CCR contents to a destination location. The condition code register size is one byte, but in transfer to memory, data is written by word access.
ANDC ORC XORC NOP Note:
B B B
CCR #IMM CCR Logically ANDs the condition code register with immediate data. CCR #IMM CCR Logically ORs the condition code register with immediate data. CCR #IMM CCR Logically exclusive-ORs the condition code register with immediate data. PC + 2 PC Only increments the program counter.
* Size refers to the operand size. B: Byte W: Word
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Table 2.10 Block Transfer Instruction
Instruction EEPMOV.B Size Function if R4L 0 then repeat @ER5+ @ER6+, R4L - 1 R4L until R4L = 0 else next; if R4 0 then repeat @ER5+ @ER6+, R4 - 1 R4 until R4 = 0 else next; Block transfer instruction. This instruction transfers the number of data bytes specified by R4L or R4, starting from the address indicated by ER5, to the location starting at the address indicated by ER6. At the end of the transfer, the next instruction is executed.
EEPMOV.W
2.6.4
Basic Instruction Formats
The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first 4 bits of the instruction. Some instructions have two operation fields. Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the first 8 bits are 0 (H'00). Condition Field: Specifies the branching condition of Bcc instructions. Figure 2.9 shows examples of instruction formats.
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Operation field only op Operation field and register fields op rn rm ADD.B Rn, Rm, etc. NOP, RTS, etc.
Operation field, register fields, and effective address extension op EA (disp) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:8 rn rm MOV.B @(d:16, Rn), Rm
Figure 2.9 Instruction Formats 2.6.5 Notes on Use of Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the byte, then write the byte back. Care is required when these instructions are used to access registers with write-only bits, or to access ports.
Step 1 2 3 Read Modify Write Description Read one data byte at the specified address Modify one bit in the data byte Write the modified data byte back to the specified address
Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR) under the following conditions. P47, P46: P45 - P40: Input pins Output pins
The intended purpose of this BCLR instruction is to switch P40 from output to input.
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Before Execution of BCLR Instruction
P47 Input/output DDR Input 0 P46 Input 0 P45 Output 1 P44 Output 1 P43 Output 1 P42 Output 1 P41 Output 1 P40 Output 1
Execution of BCLR Instruction BCLR #0, @P4DDR ; Execute BCLR instruction on DDR
After Execution of BCLR Instruction
P47 Input/output DDR Output 1 P46 Output 1 P45 Output 1 P44 Output 1 P43 Output 1 P42 Output 1 P41 Output 1 P40 Input 0
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F. Next the CPU clears bit 0 of the read data, changing the value to H'FE. Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction. As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR are set to 1, making P47 and P46 output pins. The BCLR instruction can be used to clear flags in the on-chip registers to 0. In the case of the IRQ status register (ISR), for example, a flag must be read as a condition for clearing it, but when using the BCLR instruction, if it is known that a flag has been set to 1 in an interrupt-handling routine, for instance, it is not necessary to read the flag ahead of time.
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2.7
2.7.1
Addressing Modes and Effective Address Calculation
Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes
No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16, ERn)/@(d:24, ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24 #xx:8/#xx:16/#xx:32 @(d:8, PC)/@(d:16, PC) @@aa:8
1 Register DirectRn: The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2 Register Indirect@ERn: The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand. 3 Register Indirect with Displacement@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit displacement contained in the instruction code is added to the contents of an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the address of a memory operand. A 16-bit displacement is sign-extended when added.
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4 Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn: * Register indirect with post-increment@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even. * Register indirect with pre-decrement@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result become the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the resulting register value should be even. 5 Absolute Address@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space. Table 2.12 indicates the accessible address ranges. Table 2.12 Absolute Address Access Ranges
Absolute Address 8 bits (@aa:8) 16 bits (@aa:16) 1-Mbyte Modes H'FFF00 to H'FFFFF (1048320 to 1048575) H'00000 to H'07FFF, H'F8000 to H'FFFFF (0 to 32767, 1015808 to 1048575) H'00000 to H'FFFFF (0 to 1048575) 16-Mbyte Modes H'FFFF00 to H'FFFFFF (16776960 to 16777215) H'000000 to H'007FFF, H'FF8000 to H'FFFFFF (0 to 32767, 16744448 to 16777215) H'000000 to H'FFFFFF (0 to 16777215)
24 bits (@aa:24)
6 Immediate#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data specifying a vector address.
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7 Program-Counter Relative@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is signextended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 8 Memory Indirect@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed by longword access. The first byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2.10. The upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is 0 to 255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector area. For further details see section 5, Interrupt Controller.
Specified by @aa:8
Reserved
Branch address
Figure 2.10 Memory-Indirect Branch Address Specification When a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. The accessed data or instruction code therefore begins at the preceding address. See section 2.5.2, Memory Data Formats. 2.7.2 Effective Address Calculation
Table 2.13 explains how an effective address is calculated in each addressing mode. In the 1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to generate a 20-bit effective address.
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No. Operand is general register contents 31 23 General register contents 0 0
Addressing Mode and Instruction Format Effective Address Calculation Effective Address
1
Register direct (Rn)
op
rm rn
2
Register indirect (@ERn)
op 31 General register contents 0 23
r
3
Register indirect with displacement @(d:16, ERn)/@(d:24, ERn)
0
Table 2.13 Effective Address Calculation
op Sign extension disp
r
4 31
Register indirect with post-increment or pre-decrement 0 General register contents 23 0
Register indirect with post-increment @ERn+
op 31
r
1, 2, or 4 0 General register contents 23 1, 2, or 4 1 for a byte operand, 2 for a word operand, 4 for a longword operand 0
Register indirect with pre-decrement @-ERn
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op
r
2. CPU
2. CPU
No. 23 H'FFFF 87
Addressing Mode and Instruction Format Effective Address Calculation Effective Address 0
5 abs 23
Sign extension
Absolute address @aa:8
op 16 15
0
@aa:16 abs 23
op
0
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abs Operand is immediate data IMM 23 PC contents 0 23
Sign extension
@aa:24
op
6
Immediate #xx:8, #xx:16, or #xx:32
op
7
Program-counter relative @(d:8, PC) or @(d:16, PC)
0 disp
op
disp
No.
Addressing Mode and Instruction Format Effective Address Calculation Effective Address
8
Memory indirect @@aa:8
Normal mode abs 23 H'0000 15 0 Memory contents abs 23 16 15 H'00 0 87 0
op
Advanced mode abs 23 H'0000 31 Memory contents 87 abs 0 23 0 0
op
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Legend: r, rm, rn: op: disp: IMM: abs:
Register field Operation field Displacement Immediate data Absolute address
2. CPU
2. CPU
2.8
2.8.1
Processing States
Overview
The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2.11 classifies the processing states. Figure 2.13 indicates the state transitions.
Processing states Program execution state The CPU executes program instructions in sequence Exception-handling state A transient state in which the CPU executes a hardware sequence (saving PC and CCR, fetching a vector, etc.) in response to a reset, interrupt, or other exception
Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU Reset state The CPU and all on-chip supporting modules are initialized and halted
Power-down state The CPU is halted to conserve power
Sleep mode
Software standby mode
Hardware standby mode
Figure 2.11 Processing States
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2.8.2
Program Execution State
In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address. In interrupt and trap exception handling the CPU references the stack pointer (ER7) and saves the program counter and condition code register. Types of Exception Handling and Their Priority: Exception handling is performed for resets, interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their priority. Trap instruction exceptions are accepted at all times in the program execution state. Table 2.14 Exception Handling Types and Priority
Priority High Type of Exception Detection Timing Reset Interrupt Synchronized with clock End of instruction execution or end of exception handling* Start of Exception Handling Exception handling starts immediately when RES changes from low to high When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence
Trap instruction Low
When TRAPA instruction Exception handling starts when a trap is executed (TRAPA) instruction is executed
Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling.
Figure 2.12 classifies the exception sources. For further details about exception sources, vector numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt Controller.
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2. CPU
Reset External interrupts Exception sources Interrupt Internal interrupts (from on-chip supporting modules) Trap instruction
Figure 2.12 Classification of Exception Sources
Bus request End of bus release Program execution state End of bus release Bus request Exception handling source Bus-released state End of exception handling Exception-handling state
SLEEP instruction with SSBY = 0 Sleep mode
Interrupt source NMI, IRQ 0 , IRQ 1, or IRQ 2 interrupt
SLEEP instruction with SSBY = 1
Software standby mode
RES = High STBY = High, RES = Low
Reset state
*1
Hardware standby mode Power-down state
*2
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. 2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2.13 State Transitions
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2. CPU
2.8.4
Exception-Handling Sequences
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception handling starts the CPU fetches a start address from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during the reset exception-handling sequence and immediately after it ends. Interrupt Exception Handling and Trap Instruction Exception Handling: When these exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the program counter and condition code register on the stack. Next, if the UE bit in the system control register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then the CPU fetches a start address from the exception vector table and execution branches to that address. Figure 2.14 shows the stack after the exception-handling sequence.
SP-4 SP-3 SP-2 SP-1 SP (ER7) Stack area
SP (ER7) SP+1 SP+2 SP+3 SP+4
CCR
PC
Even address
Before exception handling starts Legend: CCR: Condition code register SP: Stack pointer
Pushed on stack
After exception handling ends
Notes: 1. PC is the address of the first instruction executed after the return from the exception-handling routine. 2. Registers must be saved and restored by word access or longword access, starting at an even address.
Figure 2.14 Stack Structure after Exception Handling
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2. CPU
2.8.5
Bus-Released State
In this state the bus is released to a bus master other than the CPU, in response to a bus request. The bus masters other than the CPU are the DMA controller, the DRAM interface, and an external bus master. While the bus is released, the CPU halts except for internal operations. Interrupt requests are not accepted. For details see section 6.10, Bus Arbiter. 2.8.6 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. The I bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details see section 12, Watchdog Timer. 2.8.7 Power-Down State
In the power-down state the CPU stops operating to conserve power. There are three modes: sleep mode, software standby mode, and hardware standby mode. Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop immediately after execution of the SLEEP instruction, but the contents of CPU registers are retained. Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input goes low. As in software standby mode, the CPU and all clocks halt and the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. For further information see section 19, Power-Down State.
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2. CPU
2.9
2.9.1
Basic Operational Timing
Overview
The H8/300H CPU operates according to the system clock (). The interval from one rise of the system clock to the next rise is referred to as a "state." A memory cycle or bus cycle consists of two or three states. The CPU uses different methods to access on-chip memory, the on-chip supporting modules, and the external address space. Access to the external address space can be controlled by the bus controller. 2.9.2 On-Chip Memory Access Timing
On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and word access. Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin states.
Bus cycle T1 state Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Write data Read data Address T2 state
Figure 2.15 On-Chip Memory Access Cycle
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2. CPU
T1 Address bus AS , RD, HWR , LWR Address T2
High High impedance
D15 to D0
Figure 2.16 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide, depending on the internal I/O register being accessed. Figure 2.17 shows the on-chip supporting module access timing. Figure 2.18 indicates the pin states.
Bus cycle T1 state Address bus Internal read signal Internal data bus Address T2 state T3 state
Read access
Read data
Internal write signal Write access Internal data bus Write data
Figure 2.17 Access Cycle for On-Chip Supporting Modules
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2. CPU
T1 Address bus AS , RD, HWR , LWR Address T2 T3
High High impedance
D15 to D0
Figure 2.18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space
The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in two or three states. For details see section 6, Bus Controller.
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2. CPU
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3. MCU Operating Modes
Section 3 MCU Operating Modes
3.1
3.1.1
Overview
Operating Mode Selection
The H8/3006 and H8/3007 have four operating modes (modes 1 to 4) that are selected by the mode pins (MD2 to MD0) as indicated in table 3.1. The input at these pins determines the size of the address space and the initial bus mode. Table 3.1 Operating Mode Selection
Description Operating Mode Mode 1 Mode 2 Mode 3 Mode 4 Mode Pins MD2 0 0 0 0 1 1 1 1 MD1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 Address Space Setting prohibited 1 Mbyte 1 Mbyte 16 Mbytes 16 Mbytes Initial Bus 1 Mode* Setting prohibited 8 bits 16 bits 8 bits 16 bits On-Chip RAM Setting prohibited Enabled* Enabled* Enabled* Enabled*
2 2 2 2
Notes: 1. In modes 1 to 4, an 8-bit or 16-bit data bus can be selected on a per-area basis by settings made in the area bus width control register (ABWCR). For details see section 6, Bus Controller. 2. If the RAME bit in SYSCR is cleared to 0, these addresses become external addresses.
For the address space size there are two choices: 1 Mbyte, or 16 Mbyte.The external data bus is either 8 or 16 bits wide depending on ABWCR settings. If 8-bit access is selected for all areas, 8bit bus mode is used. For details see section 6, Bus Controller. Modes 1 and 2 support a maximum address space of 1 Mbyte. Modes 3 and 4 support a maximum address space of 16 Mbytes. The H8/3006 and H8/3007 can be used only in modes 1 to 4. The inputs at the mode pins must select one of these four modes. The inputs at the mode pins must not be changed during operation.
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3. MCU Operating Modes
When changing the mode, the chip must be placed in the reset state before the mode pin inputs are changed. 3.1.2 Register Configuration
The H8/3006 and H8/3007 have a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR). Table 3.2 summarizes these registers. Table 3.2
Address* H'EE011 H'EE012 Note: *
Registers
Name Mode control register System control register Abbreviation MDCR SYSCR R/W R R/W Initial Value Undetermined H'09
Lower 20 bits of the address in advanced mode.
3.2
Mode Control Register (MDCR)
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3006 and H8/3007.
Bit Initial value Read/Write 7 1 6 1 5 0 Reserved bits 4 0 3 0 2 MDS2 * R 1 MDS1 * R 0 MDS0 * R
Mode select 2 to 0 Bits indicating the current operating mode
Note: * Determined by pins MD 2 to MD 0 .
Bits 7 and 6Reserved: These bits can not be modified and are always read as 1. Bits 5 to 3Reserved: These bits can not be modified and are always read as 0. Bits 2 to 0Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins MD2 to MD0 (the current operating mode). MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits. The mode pin (MD2 to MD0) levels are latched into these bits when MDCR is read.
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3. MCU Operating Modes
3.3
System Control Register (SYSCR)
SYSCR is an 8-bit register that controls the operation of the H8/3006 and H8/3007.
Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 SSOE 0 R/W 0 RAME 1 R/W RAM enable Enables or disables on-chip RAM Software standby output port enable Selects the output state of the address bus and bus control signals in software standby mode NMI edge select Selects the valid edge of the NMI input User bit enable Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit Standby timer select 2 to 0 These bits select the waiting time at recovery from software standby mode Software standby Enables transition to software standby mode
Bit 7Software Standby (SSBY): Enables transition to software standby mode. (For further information about software standby mode see section 19, Power-Down State.) When software standby mode is exited by an external interrupt and a transition is made to normal operation, this bit remains set to 1. To clear this bit, write 0.
Bit 7 SSBY 0 1 Description SLEEP instruction causes transition to sleep mode SLEEP instruction causes transition to software standby mode (Initial value)
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3. MCU Operating Modes
Bits 6 to 4Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. When using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the system clock rate. For further information about waiting time selection, see section 19.4.3, Selection of Waiting Time for Exit from Software Standby Mode.
Bit 6 STS2 0 Bit 5 STS1 0 Bit 4 STS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Waiting time = 8,192 states Waiting time = 16,384 states Waiting time = 32,768 states Waiting time = 65,536 states Waiting time = 131,072 states Waiting time = 262,144 states Waiting time = 1,024 states Illegal setting (Initial value)
Bit 3User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a user bit or an interrupt mask bit.
Bit 3 UE 0 1 Description UI bit in CCR is used as an interrupt mask bit UI bit in CCR is used as a user bit (Initial value)
Bit 2NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit 2 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI An interrupt is requested at the rising edge of NMI (Initial value)
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3. MCU Operating Modes
Bit 1Software Standby Output Port Enable (SSOE): Specifies whether the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR, UCAS, LCAS, and RFSH) are kept as outputs or fixed high, or placed in the high-impedance state in software standby mode.
Bit 1 SSOE 0 1 Description In software standby mode, the address bus and bus control signals are all highimpedance (Initial value) In software standby mode, the address bus retains its output state and bus control signals are fixed high
Bit 0RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value)
3.4
3.4.1
Operating Mode Descriptions
Mode 1
A maximum 1-Mbyte address space can be accessed. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits. 3.4.2 Mode 2
A maximum 1-Mbyte address space can be accessed. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.
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3. MCU Operating Modes
3.4.3
Mode 3
Part of port A function as address pins A23 to A20, permitting access to a maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of the bus release control register (BRCR). (In this mode A20 is always used for address output.) 3.4.4 Mode 4
Part of port A function as address pins A23 to A20, permitting access to a maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of BRCR. (In this mode A20 is always used for address output.)
3.5
Pin Functions in Each Operating Mode
The pin functions of port 4 and port A vary depending on the operating mode. Table 3.3 indicates their functions in each operating mode. Table 3.3
Port Port 4 Port A
Pin Functions in Each Mode
Mode 1 P47 to P40* PA7 to PA4
1
Mode 2 D7 to D0*
1
Mode 3 P47 to P40*
1 2
Mode 4 D7 to D0*
1 2
PA7 to PA4
PA6 to PA4, A20*
PA6 to PA4, A20*
Notes: 1. Initial state. The bus mode can be switched by settings in ABWCR. These pins function as P47 to P40 in 8-bit bus mode, and as D7 to D0 in 16-bit bus mode. 2. Initial state. A20 is always an address output pin. PA6 to PA4 are switched over to A23 to A21 output by writing 0 in bits 7 to 5 of BRCR.
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3. MCU Operating Modes
3.6
Memory Map in Each Operating Mode
Figures 3.1 and 3.2 show a memory maps of the H8/3006 and H8/3007. The address space is divided into eight areas. The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4. The address locations of the on-chip RAM and internal I/O registers differ between the 1-Mbyte modes (modes 1, 2), and the 16-Mbyte modes (modes 3, 4). The address range specifiable by the CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also differs. 3.6.1 Note on Reserved Areas
The memory map of the H8/3006 and H8/3007 includes reserved areas to which read/write access is prohibited. Note that normal operation is not guaranteed if the following reserved areas are accessed. The internal I/O register space of the H8/3006 and H8/3007 includes a reserved area to which access is prohibited. For details, see Appendix B, Internal I/O Registers.
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3. MCU Operating Modes
Modes 1 and 2 (1 Mbyte)
Memory-indirect branch addresses
Modes 3 and 4 (16 Mbytes)
Memory-indirect branch addresses
H'00000 Vector area H'000FF
H'000000
16-bit absolute addresses
Vector area H'0000FF
H'07FFF
H'007FFF
H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'EE000 H'EE0FF H'F8000 H'FEF1F H'FEF20 H'FFF00 H'FFF1F H'FFF20 H'FFFE9 H'FFFEA H'FFFFF Internal I/O registers (2) External address space Internal I/O registers (1)
External address space
Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'7FFFFF H'800000 H'9FFFFF H'A00000 H'5FFFFF H'600000 External address space H'3FFFFF H'400000 H'1FFFFF H'200000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
8-bit absolute addresses 16-bit absolute addresses
H'BFFFFF H'C00000 Area 6 H'DFFFFF H'E00000 H'FEE000 H'FEE0FF H'FF8000 H'FFEF1F H'FFEF20 H'FFFF00 H'FFFF1F H'FFFF20 H'FFFFE9 H'FFFFEA H'FFFFFF
8-bit absolute addresses
External address space
On-chip RAM*
Area 7 Internal I/O registers (1)
On-chip RAM*
Internal I/O registers (2) External address space
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3.1 H8/3007 Memory Map in Each Operating Mode
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16-bit absolute addresses
16-bit absolute addresses
3. MCU Operating Modes
Modes 1 and 2 (1 Mbyte) Modes 3 and 4 (16 Mbytes)
Memory-indirect branch addresses
Memory-indirect branch addresses
Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7
H'00000 Vector area H'000FF
H'000000
16-bit absolute addresses
Vector area H'0000FF
H'07FFF
H'007FFF
H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'EE000 H'EE0FF H'F8000 Internal I/O registers (1)
External address space
Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'7FFFFF H'800000 H'9FFFFF H'A00000 H'BFFFFF H'C00000 H'DFFFFF H'E00000 H'FEE000 H'FEE0FF H'FF8000
External address space
H'1FFFFF H'200000 H'3FFFFF H'400000 H'5FFFFF H'600000
External address space
On-chip RAM* Internal I/O registers (2) External address space
H'FFF1F H'FFF20 H'FFFE9 H'FFFEA H'FFFFF
8-bit absolute addresses
H'FF71F H'FF720 H'FFF00
16-bit absolute addresses
Internal I/O registers (1)
H'FFFF1F H'FFFF20 H'FFFFE9 H'FFFFEA
On-chip RAM* Internal I/O registers (2) External address space
H'FFFFFF Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3.2 H8/3006 Memory Map in Each Operating Mode
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16-bit absolute addresses
8-bit absolute addresses
H'FFF71F H'FFF720 H'FFFF00
16-bit absolute addresses
3. MCU Operating Modes
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4. Exception Handling
Section 4 Exception Handling
4.1
4.1.1
Overview
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are accepted at all times in the program execution state. Table 4.1
Priority High
Exception Types and Priority
Exception Type Reset Interrupt Trap instruction (TRAPA) Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin Interrupt requests are handled when execution of the current instruction or handling of the current exception is completed Started by execution of a trap instruction (TRAPA)
Low
4.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows. 1. The program counter (PC) and condition code register (CCR) are pushed onto the stack. 2. The CCR interrupt mask bit is set to 1. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. Note: For a reset exception, steps 2 and 3 above are carried out.
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4. Exception Handling
4.1.3
Exception Vector Table
The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses.
* Reset External interrupts: NMI, IRQ 0 to IRQ5 Exception sources * Interrupts Internal interrupts: 36 interrupts from on-chip supporting modules
* Trap instruction
Figure 4.1 Exception Sources
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4. Exception Handling
Table 4.2
Exception Vector Table
Vector Address*
1
Exception Source Reset Reserved for system use
Vector Number 0 1 2 3 4 5 6
Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 to H'00FC to H'00FF
Normal Mode*
3
H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0005 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 to H'007E to H'007F
External interrupt (NMI) Trap instruction (4 sources)
7 8 9 10 11
External interrupt IRQ0 External interrupt IRQ1 External interrupt IRQ2 External interrupt IRQ3 External interrupt IRQ4 External interrupt IRQ5 Reserved for system use
2
12 13 14 15 16 17 18 19
Internal interrupts*
20 to 63
Notes: 1. Lower 16 bits of the address. 2. For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table. 3. Normal mode is not available in the H8/3006 and H8/3007.
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4. Exception Handling
4.2
4.2.1
Reset
Overview
A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules. Reset exception handling begins when the RES pin changes from low to high. The chip can also be reset by overflow of the watchdog timer. For details see section 12, Watchdog Timer. 4.2.2 Reset Sequence
The chip enters the reset state when the RES pin goes low. To ensure that the chip is properly reset, hold the RES pin low for at last 20 ms at power-up. To reset the chip during operation, hold the RES pin low for at least 10 system clock () cycles. See appendix D.2, Pin States at Reset, for the states of the pins in the reset state. When the RES pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows. * The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit is set to 1 in CCR. * The contents of the reset vector address (H'0000 to H'0003) are read, and program execution starts from the address indicated in the vector address. Figure 4.2 shows the reset sequence in modes 1 and 3. Figure 4.3 shows the reset sequence in modes 2 and 4.
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Vector fetch
Internal processing
Prefetch of first program instruction
RES
Address bus (1) (3) (5)
(7)
(9)
RD
HWR , LWR High (2) (4)
Figure 4.2 Reset Sequence (Modes 1 and 3)
(6) (8)
D15 to D8
(10)
(1), (3), (5), (7) (2), (4), (6), (8) (9) (10)
Address of reset vector: (1) = H'000000, (3) = H'000001, (5) = H'000002, (7) = H'000003 Start address (contents of reset exception handling vector address) Start address First instruction of program
4. Exception Handling
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Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
4. Exception Handling
Internal processing
Vector fetch
Prefetch of first program instruction
RES Address bus
(1)
(3)
(5)
RD HWR , LWR D15 to D0
High (2) (4) (6)
(1), (3) (2), (4) (5) (6)
Address of reset vector: (1) = H'000000, (3) = H'000002 Start address (contents of reset exception handling vector address) Start address First instruction of program
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Figure 4.3 Reset Sequence (Modes 2 and 4) 4.2.3 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. The first instruction of the program is always executed immediately after the reset state ends. This instruction should initialize the stack pointer (example: MOV.L #xx:32, SP).
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4. Exception Handling
4.3
Interrupts
Interrupt exception handling can be requested by seven external sources (NMI, IRQ0 to IRQ5), and 36 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), DRAM interface, 16-bit timer, 8-bit timer, DMA controller (DMAC), serial communication interface (SCI), and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt priority registers A and B (IPRA and IPRB) in the interrupt controller. For details on interrupts see section 5, Interrupt Controller.
External interrupts Interrupts NMI (1) IRQ 0 to IRQ 5 (6) WDT*1 (1) DRAM interface*2 (1) 16-bit timer (9) 8-bit timer (8) DMAC (4) SCI (12) A/D converter (1)
Internal interrupts
Notes: Numbers in parentheses are the number of interrupt sources. 1. When the watchdog timer is used as an interval timer, it generates an interrupt request at every counter overflow. 2. When the DRAM interface is used as an interval timer, it generates an interrupt request at compare match.
Figure 4.4 Interrupt Sources and Number of Interrupts
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4. Exception Handling
4.4
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1 in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, which is specified in the instruction code.
4.5
Stack Status after Exception Handling
Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling.
SP-4 SP-3 SP-2 SP-1 SP (ER7)
Stack area
SP (ER7) SP+1 SP+2 SP+3 SP+4
CCR PCE PCH PCL Even address
Before exception handling Pushed on stack Legend: PCE: Bits 23 to 16 of program counter (PC) PCH: Bits 15 to 8 of program counter (PC) PCL: Bits 7 to 0 of program counter (PC) CCR: Condition code register SP: Stack pointer
After exception handling
Notes: 1. PC indicates the address of the first instruction that will be executed after return. 2. Registers must be saved in word or longword size at even addresses.
Figure 4.5 Stack after Completion of Exception Handling
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4. Exception Handling
4.6
Notes on Stack Usage
When accessing word data or longword data, the H8/3006 and H8/3007 regard the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn PUSH.L ERn (MOV.W Rn, @-SP) (MOV.L ERn, @-SP)
Use the following instructions to restore registers: POP.W Rn POP.L ERn (MOV.W @SP+, Rn) (MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what happens when the SP value is odd.
CCR SP PC
SP
R1L
H'FFFEFA H'FFFEFB
PC
H'FFFEFC H'FFFEFD
SP
H'FFFEFF
TRAPA instruction executed
MOV. B R1L, @-ER7
SP set to H'FFFEFF Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer
Data saved above SP
CCR contents lost
Note: The diagram illustrates modes 3 and 4.
Figure 4.6 Operation when SP Value Is Odd
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4. Exception Handling
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5. Interrupt Controller
Section 5 Interrupt Controller
5.1
5.1.1
Overview
Features
The interrupt controller has the following features: * Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB). * Three-level enable/disable state setting possible by means of the I and UI bits in the CPU's condition code register (CCR) and the UE bit in the system control register (SYSCR) * Seven external interrupt pins NMI has the highest priority and is always accepted; either the rising or falling edge can be selected. For each of IRQ0 to IRQ5, sensing of the falling edge or level sensing can be selected independently.
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5. Interrupt Controller
5.1.2
Block Diagram
Figure 5.1 shows a block diagram of the interrupt controller.
CPU ISCR NMI input IRQ input OVF TME . . . . . . . TEI TEIE IRQ input section ISR Priority decision logic IER IPRA, IPRB
Interrupt request Vector number
. . .
I Interrupt controller UE SYSCR Legend: ISCR: IER: ISR: IPRA: IPRB: SYSCR: IRQ sense control register IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B System control register UI
CCR
Figure 5.1 Interrupt Controller Block Diagram
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5. Interrupt Controller
5.1.3
Pin Configuration
Table 5.1 lists the interrupt pins. Table 5.1
Name Nonmaskable interrupt External interrupt request 5 to 0
Interrupt Pins
Abbreviation I/O NMI IRQ5 to IRQ0 Function
Input Nonmaskable interrupt, rising edge or falling edge selectable Input Maskable interrupts, falling edge or level sensing selectable
5.1.4
Register Configuration
Table 5.2 lists the registers of the interrupt controller. Table 5.2
Address* H'EE012 H'EE014 H'EE015 H'EE016 H'EE018 H'EE019
1
Interrupt Controller Registers
Name System control register IRQ sense control register IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B Abbreviation SYSCR ISCR IER ISR IPRA IPRB R/W R/W R/W R/W R/(W)* R/W R/W
2
Initial Value H'09 H'00 H'00 H'00 H'00 H'00
Notes: 1. Lower 20 bits of the address in advanced mode. 2. Only 0 can be written, to clear flags.
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5. Interrupt Controller
5.2
5.2.1
Register Descriptions
System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register (SYSCR). SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 SSOE 0 R/W 0 RAME 1 R/W
RAM enable Software standby output port enable Standby timer select 2 to 0 Software standby NMI edge select Selects the NMI input edge User bit enable Selects whether to use the UI bit in CCR as a user bit or interrupt mask bit
Bit 3User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit.
Bit 3 UE 0 1 Description UI bit in CCR is used as interrupt mask bit UI bit in CCR is used as user bit (Initial value)
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5. Interrupt Controller
Bit 2NMI Edge Select (NMIEG): Selects the NMI input edge.
Bit 2 NMIEG 0 1 Description Interrupt is requested at falling edge of NMI input Interrupt is requested at rising edge of NMI input (Initial value)
5.2.2
Interrupt Priority Registers A and B (IPRA, IPRB)
IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority.
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5. Interrupt Controller
Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set.
Bit Initial value Read/Write 7 IPRA7 0 R/W 6 IPRA6 0 R/W 5 IPRA5 0 R/W 4 IPRA4 0 R/W 3 IPRA3 0 R/W 2 IPRA2 0 R/W 1 IPRA1 0 R/W 0 IPRA0 0 R/W
Priority level A0 Selects the priority level of 16-bit timer channel 2 interrupt requests Priority level A1 Selects the priority level of 16-bit timer channel 1 interrupt requests Priority level A2 Selects the priority level of 16-bit timer channel 0 interrupt requests Priority level A3 Selects the priority level of WDT, DRAM interface, and A/D converter interrupt requests Priority level A4 Selects the priority level of IRQ 4 and IRQ 5 interrupt requests Priority level A5 Selects the priority level of IRQ 2 and IRQ 3 interrupt requests Priority level A6 Selects the priority level of IRQ 1 interrupt requests Priority level A7 Selects the priority level of IRQ 0 interrupt requests
IPRA is initialized to H'00 by a reset and in hardware standby mode.
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5. Interrupt Controller
Bit 7Priority Level A7 (IPRA7): Selects the priority level of IRQ0 interrupt requests.
Bit 7 IPRA7 0 1 Description IRQ0 interrupt requests have priority level 0 (low priority) IRQ0 interrupt requests have priority level 1 (high priority) (Initial value)
Bit 6Priority Level A6 (IPRA6): Selects the priority level of IRQ1 interrupt requests.
Bit 6 IPRA6 0 1 Description IRQ1 interrupt requests have priority level 0 (low priority) IRQ1 interrupt requests have priority level 1 (high priority) (Initial value)
Bit 5Priority Level A5 (IPRA5): Selects the priority level of IRQ2 and IRQ3 interrupt requests.
Bit 5 IPRA5 0 1 Description IRQ2 and IRQ3 interrupt requests have priority level 0 (low priority) IRQ2 and IRQ3 interrupt requests have priority level 1 (high priority) (Initial value)
Bit 4Priority Level A4 (IPRA4): Selects the priority level of IRQ4 and IRQ5 interrupt requests.
Bit 4 IPRA4 0 1 Description IRQ4 and IRQ5 interrupt requests have priority level 0 (low priority) IRQ4 and IRQ5 interrupt requests have priority level 1 (high priority) (Initial value)
Bit 3Priority Level A3 (IPRA3): Selects the priority level of WDT, DRAM interface, and A/D converter interrupt requests.
Bit 3 IPRA3 0 1 Description WDT, DRAM interface, and A/D converter interrupt requests have priority level 0 (low priority) (Initial value) WDT, DRAM interface, and A/D converter interrupt requests have priority level 1 (high priority)
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5. Interrupt Controller
Bit 2Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt requests.
Bit 2 IPRA2 0 1 Description 16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (Initial value) 16-bit timer channel 0 interrupt requests have priority level 1 (high priority)
Bit 1Priority Level A1 (IPRA1): Selects the priority level of 16-bit timer channel 1 interrupt requests.
Bit 1 IPRA1 0 1 Description 16-bit timer channel 1 interrupt requests have priority level 0 (low priority) (Initial value) 16-bit timer channel 1 interrupt requests have priority level 1 (high priority)
Bit 0Priority Level A0 (IPRA0): Selects the priority level of 16-bit timer channel 2 interrupt requests.
Bit 0 IPRA0 0 1 Description 16-bit timer channel 2 interrupt requests have priority level 0 (low priority) (Initial value) 16-bit timer channel 2 interrupt requests have priority level 1 (high priority)
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5. Interrupt Controller
Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set.
Bit Initial value Read/Write 7 IPRB7 0 R/W 6 IPRB6 0 R/W 5 IPRB5 0 R/W 4 0 R/W 3 IPRB3 0 R/W 2 IPRB2 0 R/W 1 IPRB1 0 R/W 0 0 R/W
Reserved bit Priority level B1 Selects the priority level of SCI channel 2 interrupt requests Priority level B2 Selects the priority level of SCI channel 1 interrupt requests Priority level B3 Selects the priority level of SCI channel 0 interrupt requests Reserved bit
Priority level B5 Selects the priority level of DMAC interrupt requests (channels 0 and 1) Priority level B6 Selects the priority level of 8-bit timer channel 2, 3 interrupt requests Priority level B7 Selects the priority level of 8-bit timer channel 0, 1 interrupt requests
IPRB is initialized to H'00 by a reset and in hardware standby mode.
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5. Interrupt Controller
Bit 7Priority Level B7 (IPRB7): Selects the priority level of 8-bit timer channel 0, 1 interrupt requests.
Bit 7 IPRB7 0 1 Description 8-bit timer channel 0, 1 interrupt requests have priority level 0 (low priority)(Initial value) 8-bit timer channel 0, 1 interrupt requests have priority level 1 (high priority)
Bit 6Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt requests.
Bit 6 IPRB6 0 1 Description 8-bit timer channel 2, 3 interrupt requests have priority level 0 (low priority)(Initial value) 8-bit timer channel 2, 3 interrupt requests have priority level 1 (high priority)
Bit 5Priority Level B5 (IPRB5): Selects the priority level of DMAC interrupt requests (channels 0 and 1).
Bit 5 IPRB5 0 1 Description DMAC interrupt requests (channels 0 and 1) have priority level 0 (low priority) (Initial value)
DMAC interrupt requests (channels 0 and 1) have priority level 1 (high priority)
Bit 4Reserved: This bit can be written and read, but it does not affect interrupt priority. Bit 3Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests.
Bit 3 IPRB3 0 1 Description SCI channel 0 interrupt requests have priority level 0 (low priority) SCI channel 0 interrupt requests have priority level 1 (high priority) (Initial value)
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5. Interrupt Controller
Bit 2Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests.
Bit 2 IPRB2 0 1 Description SCI channel 1 interrupt requests have priority level 0 (low priority) SCI channel 1 interrupt requests have priority level 1 (high priority) (Initial value)
Bit 1Priority Level B1 (IPRB1): Selects the priority level of SCI channel 2 interrupt requests.
Bit 1 IPRB1 0 1 Description SCI channel 2 interrupt requests have priority level 0 (low priority) SCI channel 2 interrupt requests have priority level 1 (high priority) (Initial value)
Bit 0Reserved: This bit can be written and read, but it does not affect interrupt priority. 5.2.3 IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ5 interrupt requests.
Bit Initial value Read/Write 7 0 6 0 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)*
Reserved bits
IRQ 5 to IRQ0 flags These bits indicate IRQ 5 to IRQ 0 interrupt request status
Note: * Only 0 can be written, to clear flags.
ISR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6Reserved: These bits can not be modified and are always read as 0.
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5. Interrupt Controller
Bits 5 to 0IRQ5 to IRQ0 Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ5 to IRQ0 interrupt requests.
Bits 5 to 0 IRQ5F to IRQ0F Description 0 [Clearing conditions] * * * 1 * * Note: n = 5 to 0 (Initial value)
0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1. IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out. IRQnSC = 1 and IRQn interrupt exception handling is carried out. IRQnSC = 0 and IRQn input is low. IRQnSC = 1 and IRQn input changes from high to low.
[Setting conditions]
5.2.4
IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that enables or disables IRQ0 to IRQ5 interrupt requests.
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W
Reserved bits
IRQ 5 to IRQ0 enable These bits enable or disable IRQ 5 to IRQ 0 interrupts
IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6Reserved: These bits can be written and read, but they do not enable or disable interrupts. Bits 5 to 0IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E): These bits enable or disable IRQ5 to IRQ0 interrupts.
Bits 5 to 0 IRQ5E to IRQ0E Description 0 1 IRQ5 to IRQ0 interrupts are disabled IRQ5 to IRQ0 interrupts are enabled (Initial value)
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5. Interrupt Controller
5.2.5
IRQ Sense Control Register (ISCR)
ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ5 to IRQ0.
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
Reserved bits
IRQ 5 to IRQ0 sense control These bits select level sensing or falling-edge sensing for IRQ 5 to IRQ 0 interrupts
ISCR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6Reserved: These bits can be written and read, but they do not select level or falling-edge sensing. Bits 5 to 0IRQ5 to IRQ0 Sense Control (IRQ5SC to IRQ0SC): These bits select whether interrupts IRQ5 to IRQ0 are requested by level sensing of pins IRQ5 to IRQ0, or by falling-edge sensing.
Bits 5 to 0 IRQ5SC to IRQ0SC Description 0 1 Interrupts are requested when IRQ5 to IRQ0 inputs are low Interrupts are requested by falling-edge input at IRQ5 to IRQ0 (Initial value)
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5. Interrupt Controller
5.3
Interrupt Sources
The interrupt sources include external interrupts (NMI, IRQ0 to IRQ5) and 36 internal interrupts. 5.3.1 External Interrupts
There are seven external interrupts: NMI, and IRQ0 to IRQ5. Of these, NMI, IRQ0, IRQ1, and IRQ2 can be used to exit software standby mode. NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the I and UI bits in CCR. The NMIEG bit in SYSCR selects whether an interrupt is requested by the rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector number 7. IRQ0 to IRQ5 Interrupts: These interrupts are requested by input signals at pins IRQ0 to IRQ5. The IRQ0 to IRQ5 interrupts have the following features. * ISCR settings can select whether an interrupt is requested by the low level of the input at pins IRQ0 to IRQ5, or by the falling edge. * IER settings can enable or disable the IRQ0 to IRQ5 interrupts. Interrupt priority levels can be assigned by four bits in IPRA (IPRA7 to IPRA4). * The status of IRQ0 to IRQ5 interrupt requests is indicated in ISR. The ISR flags can be cleared to 0 by software. Figure 5.2 shows a block diagram of interrupts IRQ0 to IRQ5.
IRQnSC IRQnF Edge/level sense circuit IRQn input S R Clear signal Note: n = 5 to 0 Q IRQn interrupt request IRQnE
Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5
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5. Interrupt Controller
Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF).
IRQn input pin IRQnF
Note: n = 5 to 0
Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ0 to IRQ5 have vector numbers 12 to 17. These interrupts are detected regardless of whether the corresponding pin is set for input or output. When using a pin for external interrupt input, clear its DDR bit to 0 and do not use the pin for chip select output, refresh output, SCI input/output, or A/D external trigger input. 5.3.2 Internal Interrupts
Thirty-Six internal interrupts are requested from the on-chip supporting modules. * Each on-chip supporting module has status flags for indicating interrupt status, and enable bits for enabling or disabling interrupts. * Interrupt priority levels can be assigned in IPRA and IPRB. * 16-bit timer, SCI, and A/D converter interrupt requests can activate the DMAC, in which case no interrupt request is sent to the interrupt controller, and the I and UI bits are disregarded. 5.3.3 Interrupt Vector Table
Table 5.3 lists the interrupt sources, their vector addresses, and their default priority order. In the default priority order, smaller vector numbers have higher priority. The priority of interrupts other than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order shown in table 5.3.
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5. Interrupt Controller
Table 5.3
Interrupt Sources, Vector Addresses, and Priority
Vector Address*
Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved WOVI (interval timer) CMI (compare match) Reserved ADI (A/D end) IMIA0 (compare match/ input capture A0) IMIB0 (compare match/ input capture B0) OVI0 (overflow 0) Reserved IMIA1 (compare match/ inputcapture A1) IMIB1 (compare match/ input capture B1) OVI1 (overflow 1) Reserved
Origin External pins
Vector Number 7 12 13 14 15 16 17
Advanced Mode H'001C to H'001F H'0030 to H'0033 H'0034 to H0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005E to H'005F H'0060 to H'0063
IPR IPRA7 IPRA6 IPRA5 IPRA4
Priority High
Watchdog timer DRAM interface A/D 16-bit timer channel 0
18 19 20 21 22 23 24
IPRA3
IPRA2
25
H'0064 to H'0067
26 16-bit timer channel 1 27 28
H'0068 to H'006B H'006C to H'006F H'0070 to H'0073 IPRA1
29
H'0074 to H'0077
30 31
H'0078 to H'007B H'007C to H'007F Low
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5. Interrupt Controller
Vector Address* Interrupt Source IMIA2 (compare match/ input capture A2) IMIB2 (compare match/ input capture B2) OVI2 (overflow 2) Reserved CMIA0 (compare match A0) CMIB0 (compare match B0) CMIA1/CMIB1 (compare match A1/B1) TOVI0/TOVI1 (overflow 0/1) CMIA2 (compare match A2) CMIB2 (compare match B2) CMIA3/CMIB3 (compare match A3/B3) TOVI2/TOVI3 (overflow 2/3) DEND0A DEND0B DEND1A DEND1B Reserved Origin 16-bit timer channel 2 Vector Number 32 Advanced Mode H'0080 to H'0083 IPR IPRA0 Priority High
33
H'0084 to H'0087
34 8-bit timer channel 0/1 35 36
H'0088 to H'008B H'008C to H'008F H'0090 to H'0093 IPRB7
37
H'0094 to H'0097
38
H'0098 to H'009B
39 8-bit timer channel 2/3 40
H'009C to H'009F H'00A0 to H'00A3 IPRB6
41
H'00A4 to H'00A7
42
H'00A8 to H'00AB
43 DMAC 44 45 46 47 48 49 50 51
H'00AC to H'00AF H'00B0 to H'00B3 H'00B4 to H'00B7 H'00B8 to H'00BB H'00BC to H'00BF H'00C0 to H'00C3 H'00C4 to H'00C7 H'00C8 to H'00CB H'00CC to H'00CF IPRB5
Low
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5. Interrupt Controller
Vector Address* Interrupt Source ERI0 (receive error 0) RXI0 (receive data full 0) TXI0 (transmit data empty 0) TEI0 (transmit end 0) ERI1 (receive error 1) RXI1 (receive data full 1) TXI1 (transmit data empty 1) TEI1 (transmit end 1) ERI2 (receive error 2) RXI2 (receive data full 2) TXI2 (transmit data empty 2) TEI2 (transmit end 2) Note: * Origin SCI channel 0 Vector Number 52 53 54 55 SCI channel 1 56 57 58 59 SCI channel 2 60 61 62 63 Advanced Mode H'00D0 to H'00D3 H'00D4 to H'00D7 H'00D8 to H'00DB H'00DC to H'00DF H'00E0 to H'00E3 H'00E4 to H'00E7 H'00E8 to H'00EB H'00EC to H'00EF H'00F0 to H'00F3 H'00F4 to H'00F7 H'00F8 to H'00FB H'00FC to H'00FF Low IPRB1 IPRB2 IPR IPRB3 Priority High
Lower 16 bits of the address.
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5. Interrupt Controller
5.4
5.4.1
Interrupt Operation
Interrupt Handling Process
The H8/3006 and H8/3007 handle interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits. Table 5.4 indicates how interrupts are handled for all setting combinations of the UE, I, and UI bits. NMI interrupts are always accepted except in the reset and hardware standby states. IRQ interrupts and interrupts from the on-chip supporting modules have their own enable bits. Interrupt requests are ignored when the enable bits are cleared to 0. Table 5.4
SYSCR UE 1 I 0 1 0 0 1
UE, I, and UI Bit Settings and Interrupt Handling
CCR UI 0 1 Description All interrupts are accepted. Interrupts with priority level 1 have higher priority. No interrupts are accepted except NMI. All interrupts are accepted. Interrupts with priority level 1 have higher priority. NMI and interrupts with priority level 1 are accepted. No interrupts are accepted except NMI.
UE = 1: Interrupts IRQ0 to IRQ5 and interrupts from the on-chip supporting modules can all be masked by the I bit in the CPU's CCR. Interrupts are masked when the I bit is set to 1, and unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority. Figure 5.4 is a flowchart showing how interrupts are accepted when UE = 1.
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5. Interrupt Controller
Program execution state
No Interrupt requested? Yes Yes NMI No No Priority level 1? Yes No No Pending
IRQ 0 Yes
IRQ 0 No Yes
IRQ 1 Yes
IRQ 1 Yes
No
TEI2 Yes
TEI2 Yes
No I=0 Yes Save PC and CCR I 1 Read vector address Branch to interrupt service routine
Figure 5.4 Process Up to Interrupt Acceptance when UE = 1
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5. Interrupt Controller
* If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. * When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests pending. If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5.3. * The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are held pending. * When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. * In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. * Next the I bit is set to 1 in CCR, masking all interrupts except NMI. * The vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. UE = 0: The I and UI bits in the CPU's CCR and the IPR bits enable three-level masking of IRQ0 to IRQ5 interrupts and interrupts from the on-chip supporting modules. * Interrupt requests with priority level 0 are masked when the I bit is set to 1, and are unmasked when the I bit is cleared to 0. * Interrupt requests with priority level 1 are masked when the I and UI bits are both set to 1, and are unmasked when either the I bit or the UI bit is cleared to 0. * For example, if the interrupt enable bits of all interrupt requests are set to 1, IPRA is set to H'20, and IPRB is set to H'00 (giving IRQ2 and IRQ3 interrupt requests priority over other interrupts), interrupts are masked as follows: a. If I = 0, all interrupts are unmasked (priority order: NMI > IRQ2 > IRQ3 >IRQ0 ...). b. If I = 1 and UI = 0, only NMI, IRQ2, and IRQ3 are unmasked. c. If I = 1 and UI = 1, all interrupts are masked except NMI.
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5. Interrupt Controller
Figure 5.5 shows the transitions among the above states.
I0 a. All interrupts are unmasked I 1, UI 0 b. Only NMI, IRQ 2 , and IRQ 3 are unmasked
I0
Exception handling, or I 1, UI 1
UI 0
Exception handling, or UI 1
c. All interrupts are masked except NMI
Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0. * If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. * When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests pending. If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5.3. * The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request is accepted regardless of its IPR setting, and regardless of the UI bit. If the I bit is set to 1 and the UI bit is cleared to 0, only NMI and interrupts with priority level 1 are accepted; interrupt requests with priority level 0 are held pending. If the I bit and UI bit are both set to 1, interrupt requests are held pending. * When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. * In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. * The I and UI bits are set to 1 in CCR, masking all interrupts except NMI. * The vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address.
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5. Interrupt Controller
Program execution state
No Interrupt requested? Yes Yes NMI No No Priority level 1? Yes No No Pending
IRQ 0 Yes
IRQ 0 No Yes
IRQ 1 Yes
IRQ 1 Yes
No
TEI2 Yes
TEI2 Yes
No I=0 Yes No UI = 0 Yes I=0 Yes
No
Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt service routine
Figure 5.6 Process Up to Interrupt Acceptance when UE = 0
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5.4.2
Interrupt accepted
5. Interrupt Controller
Interrupt level decision and wait for end of instruction Instruction Internal prefetch processing Stack Vector fetch
Prefetch of interrupt Internal service routine processing instruction
Interrupt Sequence
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(1) (3) (5) (7) (9) (11) (13) High (2) (4) (6) (8) (10) (12) (14) (6), (8) PC and CCR saved to stack (9), (11) Vector address (10), (12) Starting address of interrupt service routine (contents of vector address) (13) Starting address of interrupt service routine; (13) = (10), (12) (14) First instruction of interrupt service routine
Interrupt request signal
Address bus
RD
HWR , LWR
Figure 5.7 shows the interrupt sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus.
Figure 5.7 Interrupt Sequence
D15 to D0
(1)
Instruction prefetch address (not executed; return address, same as PC contents) (2), (4) Instruction code (not executed) (3) Instruction prefetch address (not executed) (5) SP - 2 (7) SP - 4
Note: Mode 2, with program code and stack in external memory area accessed in two states via 16-bit bus.
5. Interrupt Controller
5.4.3
Interrupt Response Time
Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time
External Memory On-Chip Memory 2*
1
8-Bit Bus 2 States 2*
1
16-Bit Bus 2 States 2*
4 1
No. 1 2
Item Interrupt priority decision Maximum number of states until end of current instruction Saving PC and CCR to stack Vector fetch Instruction prefetch* Internal processing*
2 3
3 States 2*
1
3 States 2*
1
1 to 23
1 to 27
1 to 31*
1 to 23
1 to 25*
4
3 4 5 6 Total
4 4 4 4 19 to 41
8 8 8 4 31 to 57
12* 12* 12* 4
4
4 4 4 4 19 to 41
6* 6* 6* 4
4
4 4
4 4
43 to 73
25 to 49
Notes: 1. 1 state for internal interrupts. 2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt service routine. 3. Internal processing after the interrupt is accepted and internal processing after vector fetch. 4. The number of states increases if wait states are inserted in external memory access.
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5.5
5.5.1
Usage Notes
Contention between Interrupt and Interrupt-Disabling Instruction
When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored. This also applies to the clearing of an interrupt flag to 0. Figure 5.8 shows an example in which an IMIEA bit is cleared to 0 in the 16-bit timer's TISRA register.
TISRA write cycle by CPU Internal address bus Internal write signal IMIEA IMIA exception handling
TISRA address
IMIA IMFA interrupt signal
Figure 5.8 Contention between Interrupt and Interrupt-Disabling Instruction This type of contention will not occur if the interrupt is masked when the interrupt enable bit or flag is cleared to 0.
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5.5.2
Instructions that Inhibit Interrupts
The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction. 5.5.3 Interrupts during EEPMOV Instruction Execution
The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests. When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the transfer is completed, not even NMI. When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction. Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution:
L1: EEPMOV.W MOV.W R4,R4 BNE L1
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6. Bus Controller
Section 6 Bus Controller
6.1 Overview
The H8/3006 and H8/3007 have an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function that controls the operation of the internal bus masters-the CPU, DMA controller (DMAC), and DRAM interface and can release the bus to an external device. 6.1.1 Features
The features of the bus controller are listed below. * Manages external address space in area units Manages the external space as eight areas (0 to 7) of 128 kbytes in 1M-byte modes, or 2 Mbytes in 16-Mbyte modes Bus specifications can be set independently for each area DRAM/burst ROM interfaces can be set * Basic bus interface Chip select (CS0 to CS7) can be output for areas 0 to 7 8-bit access or 16-bit access can be selected for each area Two-state access or three-state access can be selected for each area Program wait states can be inserted for each area Pin wait insertion capability is provided * DRAM interface DRAM interface can be set for areas 2 to 5 Row address/column address multiplexed output (8/9/10 bits) 2-CAS byte access mode Burst operation (fast page mode) TP cycle insertion to secure RAS precharging time Choice of CAS-before-RAS refreshing or self-refreshing
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* Burst ROM interface Burst ROM interface can be set for area 0 Selection of two- or three-state burst access * Idle cycle insertion An idle cycle can be inserted in case of an external read cycle between different areas An idle cycle can be inserted when an external read cycle is immediately followed by an external write cycle * Bus arbitration function A built-in bus arbiter grants the bus right to the CPU, DMAC, DRAM interface, or an external bus master * Other features The refresh counter (refresh timer) can be used as an interval timer 6.1.2 Block Diagram
Figure 6.1 shows a block diagram of the bus controller.
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6. Bus Controller
CS0 to CS7 ABWCR ASTCR BCR Internal address bus Area decoder CSCR
Chip select control signals
Internal signals Bus mode control signal Bus size control signal Access state control signal
Bus control circuit
Internal data bus
BACK BREQ
Wait request signal
WAIT
Wait state controller WCRH WCRL
Internal signals CPU bus request signal DMAC bus request signal DRAM interface bus request signal CPU bus acknowledge signal DMAC bus acknowledge signal DRAM interface bus acknowledge signal
BRCR Bus arbiter
DRAM interface DRAM control DRCRA DRCRB RTMCSR RTCNT Legend: ABWCR ASTCR WCRH WCRL BRCR CSCR DRCRA DRCRB RTMCSR RTCNT RTCOR BCR : Bus width control register : Access state control register : Wait control register H : Wait control register L : Bus release control register : Chip select control register : DRAM control register A : DRAM control register B : Refresh timer control/status register : Refresh timer counter : Refresh time constant register : Bus control register RTCOR
Figure 6.1 Block Diagram of Bus Controller
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6. Bus Controller
6.1.3
Pin Configuration
Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1
Name Chip select 0 to 7 Address strobe Read High write
Bus Controller Pins
Abbreviation CS0 to CS7 AS RD HWR I/O Output Output Output Output Function Strobe signals selecting areas 0 to 7 Strobe signal indicating valid address output on the address bus Strobe signal indicating reading from the external address space Strobe signal indicating writing to the external address space, with valid data on the upper data bus (D15 to D8) Strobe signal indicating writing to the external address space, with valid data on the lower data bus (D7 to D0) Wait request signal for access to external three-state access areas Request signal for releasing the bus to an external device Acknowledge signal indicating release of the bus to an external device
Low write
LWR
Output
Wait Bus request Bus acknowledge
WAIT BREQ BACK
Input Input Output
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6.1.4
Register Configuration
Table 6.2 summarizes the bus controller's registers. Table 6.2
Address* H'EE020 H'EE021 H'EE022 H'EE023 H'EE013 H'EE01F H'EE024 H'EE026 H'EE027 H'EE028 H'EE029 H'EE02A Notes: 1. 2. 3. 4.
1
Bus Controller Registers
Name Bus width control register Access state control register Wait control register H Wait control register L Bus release control register Chip select control register Bus control register DRAM control register A DRAM control register B Refresh timer control/status register Refresh timer counter Refresh time constant register Abbreviation ABWCR ASTCR WCRH WCRL BRCR CSCR BCR DRCRA DRCRB RTMCSR RTCNT RTCOR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W
4
Initial Value H'FF* H'FF H'FF H'FF H'FE* H'0F H'C6 H'10 H'08 H'07 H'00 H'FF
3 2
Lower 20 bits of the address in advanced mode. In modes 2 and 4, the initial value is H'00. In modes 3 and 4, the initial value is H'EE. For Bit 7, only 0 can be written to clear the flag.
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6. Bus Controller
6.2
6.2.1
Register Descriptions
Bus Width Control Register (ABWCR)
ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area.
Bit Initial value Initial value 7 ABW7 Modes 1 and 3 Modes 2 and 4 1 0 Read/Write R/W Read/Write R/W 6 ABW6 1 R/W 0 R/W 5 ABW5 1 R/W 0 R/W 4 ABW4 1 R/W 0 R/W 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W
When ABWCR contains H'FF (selecting 8-bit access for all areas), the chip operates in 8-bit bus mode: the upper data bus (D15 to D8) is valid, and port 4 is an input/output port. When at least one bit is cleared to 0 in ABWCR, the chip operates in 16-bit bus mode with a 16-bit data bus (D15 to D0). In modes 1 and 3, ABWCR is initialized to H'FF by a reset and in hardware standby mode. In modes 2 and 4, ABWCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access or 16-bit access for the corresponding areas.
Bits 7 to 0 ABW7 to ABW0 0 1 Description Areas 7 to 0 are 16-bit access areas Areas 7 to 0 are 8-bit access areas
ABWCR specifies the data bus width of external memory areas. The data bus width of on-chip memory and registers is fixed, and does not depend on ABWCR settings.
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6. Bus Controller
6.2.2
Access State Control Register (ASTCR)
ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states.
Bit 7 AST7 Initial value Read/Write 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W
Bits selecting number of states for access to each area
ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is accessed in two or three states.
Bits 7 to 0 AST7 to AST0 0 1 Description Areas 7 to 0 are accessed in two states Areas 7 to 0 are accessed in three states (Initial value)
ASTCR specifies the number of states in which external areas are accessed. On-chip memory and registers are accessed in a fixed number of states that does not depend on ASTCR settings. When the corresponding area is designated as DRAM space by bits DRAS2 to DRAS0 in DRAM control register A (DRCRA), the number of access states does not depend on the AST bit setting. When an AST bit is cleared to 0, programmable wait insertion is not performed. 6.2.3 Wait Control Registers H and L (WCRH, WCRL)
WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. On-chip memory and registers are accessed in a fixed number of states that does not depend on WCRH/WCRL settings. WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not initialized in software standby mode.
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WCRH
Bit 7 W71 Initial value Read/Write 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W
Bits 7 and 6Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1.
Bit 7 W71 0 Bit 6 W70 0 1 1 0 1 Description Program wait not inserted when external space area 7 is accessed 1 program wait state inserted when external space area 7 is accessed 2 program wait states inserted when external space area 7 is accessed 3 program wait states inserted when external space area 7 is accessed (Initial value)
Bits 5 and 4Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1.
Bit 5 W61 0 Bit 4 W60 0 1 1 0 1 Description Program wait not inserted when external space area 6 is accessed 1 program wait state inserted when external space area 6 is accessed 2 program wait states inserted when external space area 6 is accessed 3 program wait states inserted when external space area 6 is accessed (Initial value)
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Bits 3 and 2Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1.
Bit 3 W51 0 Bit 2 W50 0 1 1 0 1 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value)
Bits 1 and 0Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1.
Bit 1 W41 0 Bit 0 W40 0 1 1 0 1 Description Program wait not inserted when external space area 4 is accessed 1 program wait state inserted when external space area 4 is accessed 2 program wait states inserted when external space area 4 is accessed 3 program wait states inserted when external space area 4 is accessed (Initial value)
WCRL
Bit 7 W31 Initial value Read/Write 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 W11 1 R/W 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W
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6. Bus Controller
Bits 7 and 6Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
Bit 7 W31 0 Bit 6 W30 0 1 1 0 1 Description Program wait not inserted when external space area 3 is accessed 1 program wait state inserted when external space area 3 is accessed 2 program wait states inserted when external space area 3 is accessed 3 program wait states inserted when external space area 3 is accessed (Initial value)
Bits 5 and 4Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1.
Bit 5 W21 0 Bit 4 W20 0 1 1 0 1 Description Program wait not inserted when external space area 2 is accessed 1 program wait state inserted when external space area 2 is accessed 2 program wait states inserted when external space area 2 is accessed 3 program wait states inserted when external space area 2 is accessed (Initial value)
Bits 3 and 2Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1.
Bit 3 W11 0 Bit 2 W10 0 1 1 0 1 Description Program wait not inserted when external space area 1 is accessed 1 program wait state inserted when external space area 1 is accessed 2 program wait states inserted when external space area 1 is accessed 3 program wait states inserted when external space area 1 is accessed (Initial value)
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Bits 1 and 0Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1.
Bit 1 W01 0 Bit 0 W00 0 1 1 0 1 Description Program wait not inserted when external space area 0 is accessed 1 program wait state inserted when external space area 0 is accessed 2 program wait states inserted when external space area 0 is accessed 3 program wait states inserted when external space area 0 is accessed (Initial value)
6.2.4
Bus Release Control Register (BRCR)
BRCR is an 8-bit readable/writable register that enables address output on bus lines A23 to A20 and enables or disables release of the bus to an external device.
Bit 7 A23E Modes Initial value 1 1 and 2 Read/Write Modes Initial value 1 3 and 4 Read/Write R/W 6 A22E 1 1 R/W 5 A21E 1 1 R/W 4 A20E 1 0 3 1 1 2 1 1 Reserved bits Address 23 to 20 enable These bits enable PA7 to PA4 to be used for A23 to A20 address output Bus release enable Enables or disables release of the bus to an external device 1 1 1 0 BRLE 0 R/W 0 R/W
BRCR is initialized to H'FE in modes 1 and 2, and to H'EE in modes 3 and 4, by a reset and in hardware standby mode. It is not initialized in software standby mode.
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6. Bus Controller
Bit 7Address 23 Enable (A23E): Enables PA4 to be used as the A23 address output pin. Writing 0 in this bit enables A23 output from PA4. In modes 1 and 2, this bit cannot be modified and PA4 has its ordinary port functions.
Bit 7 A23E 0 1 Description PA4 is the A23 address output pin PA4 is an input/output pin (Initial value)
Bit 6Address 22 Enable (A22E): Enables PA5 to be used as the A22 address output pin. Writing 0 in this bit enables A22 output from PA5. In modes 1 and 2, this bit cannot be modified and PA5 has its ordinary port functions.
Bit 6 A22E 0 1 Description PA5 is the A22 address output pin PA5 is an input/output pin (Initial value)
Bit 5Address 21 Enable (A21E): Enables PA6 to be used as the A21 address output pin. Writing 0 in this bit enables A21 output from PA6. In modes 1 and 2, this bit cannot be modified and PA6 has its ordinary port functions.
Bit 5 A21E 0 1 Description PA6 is the A21 address output pin PA6 is an input/output pin (Initial value)
Bit 4Address 20 Enable (A20E): Initial value of this bit varies depending on the mode. This bit can not be modified.
Bit 4 A20E 0 1 Description PA7 is the A20 address output pin (Initial value in mode 3 or 4) PA7 is an input/output pin (Initial value in mode 1 or 2)
Bits 3 to 1Reserved: These bits cannot be modified and are always read as 1.
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6. Bus Controller
Bit 0Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.
Bit 0 BRLE 0 1 Description The bus cannot be released to an external device BREQ and BACK can be used as input/output pins The bus can be released to an external device (Initial value)
6.2.5
Bit
Bus Control Register (BCR)
7 ICIS1 6 ICIS0 1 R/W 5 4 3 2
1 RDEA 1 R/W
0 WAITE 0 R/W
BROME BRSTS1 BRSTS0 0 R/W 0 R/W 0 R/W
Initial value Read/Write
1 R/W
1
BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the area division unit, and enables or disables WAIT pin input. BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted between bus cycles in case of consecutive external read cycles for different areas.
Bit 7 ICIS1 0 1 Description No idle cycle inserted in case of consecutive external read cycles for different areas Idle cycle inserted in case of consecutive external read cycles for different areas (Initial value)
Bit 6Idle Cycle Insertion 0 (ICIS0): Selects whether one idle cycle state is to be inserted between bus cycles in case of consecutive external read and write cycles.
Bit 6 ICIS0 0 1 Description No idle cycle inserted in case of consecutive external read and write cycles Idle cycle inserted in case of consecutive external read and write cycles (Initial value)
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6. Bus Controller
Bit 5Burst ROM Enable (BROME): Selects whether area 0 is a burst ROM interface area.
Bit 5 BROME 0 1 Description Area 0 is a basic bus interface area Area 0 is a burst ROM interface area (Initial value)
Bit 4Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycle states for the burst ROM interface.
Bit 4 BRSTS1 0 1 Description Burst access cycle comprises 2 states Burst access cycle comprises 3 states (Initial value)
Bit 3Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access.
Bit 3 BRSTS0 0 1 Description Max. 4 words in burst access (burst access on match of address bits above A3) (Initial value) Max. 8 words in burst access (burst access on match of address bits above A4)
Bit 2Reserved: Read-only bit, always read as 1. Bit 1Area Division Unit Select (RDEA): Selects the memory map area division units. This bit is valid in modes 3 and 4, and is invalid in modes 1 and 2.
Bit 1 RDEA 0 Description Area divisions are as follows: Area 0: 2 Mbytes Area 1: 2 Mbytes Area 2: 8 Mbytes Area 3: 2 Mbytes 1 Areas 0 to 7 are the same size (2 Mbytes) Area 4: 1.93 Mbytes Area 5: 4 kbytes Area 6: 23.75 kbytes Area 7: 22 bytes (Initial value)
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Bit 0WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the WAIT pin.
Bit 0 WAITE 0 1 Description WAIT pin wait input is disabled, and the WAIT pin can be used as an input/output port (Initial value) WAIT pin wait input is enabled
6.2.6
Chip Select Control Register (CSCR)
CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals (CS7 to CS4). If output of a chip select signal is enabled by a setting in this register, the corresponding pin functions a chip select signal (CS7 to CS4) output regardless of any other settings.
Bit Initial value Read/Write 7 CS7E 0 R/W 6 CS6E 0 R/W 5 CS5E 0 R/W 4 CS4E 0 R/W 3 1 2 1 1 1 0 1
Chip select 7 to 4 enable These bits enable or disable chip select signal output
Reserved bits
CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 4Chip Select 7 to 4 Enable (CS7E to CS4E): These bits enable or disable output of the corresponding chip select signal.
Bit n CSnE 0 1 Note: n = 7 to 4 Description Output of chip select signal CSn is disabled Output of chip select signal CSn is enabled (Initial value)
Bits 3 to 0Reserved: These bits cannot be modified and are always read as 1.
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6.2.7
Bit
DRAM Control Register A (DRCRA)
7 DRAS2 6 DRAS1 0 R/W 5 DRAS0 0 R/W 4
3 BE 0 R/W
2 RDM 0 R/W
1 SRFMD 0 R/W
0 RFSHE 0 R/W
Initial value Read/Write
0 R/W
1
DRCRA is an 8-bit readable/writable register that selects the areas that have a DRAM interface function, and the access mode, and enables or disables self-refreshing and refresh pin output. DRCRA is initialized to H'10 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 5DRAM Area Select (DRAS2 to DRAS0): These bits select which of areas 2 to 5 are to function as DRAM interface areas (DRAM space), and at the same time select the RAS output pin corresponding to each DRAM space.
Description Bit 7 Bit 6 Bit 5 DRAS2 DRAS1 DRAS0 Area 5 0 0 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 Normal Normal Normal Normal Normal DRAM space (CS5) Area 4 Normal Normal Normal Normal DRAM space (CS4) DRAM space (CS4) Area 3 Normal Normal DRAM space (CS3) DRAM space (CS3) DRAM space (CS3) Area 2 Normal DRAM space (CS2) DRAM space (CS2) DRAM space (CS2) DRAM space (CS2)
DRAM space (CS2)*
DRAM space (CS4)*
DRAM space (CS2)*
DRAM space (CS2)*
A single CSn pin serves as a common RAS output pin for a number of areas. Unused CSn pins can be used as input/output ports.
When any of bits DRAS2 to DRAS0 is set to 1, it is not possible to write to DRCRB, RTMCSR, RTCNT, or RTCOR. However, 0 can be written to the CMF flag in RTMCSR to clear the flag.
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When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than 000 must not be performed. Bit 4Reserved: This bit cannot be modified and is always read as 1. Bit 3Burst Access Enable (BE): Enables or disables burst access to DRAM space. DRAM space burst access is performed in fast page mode.
Bit 3 BE 0 1 Description Burst disabled (always full access) DRAM space access performed in fast page mode (Initial value)
Bit 2RAS Down Mode (RDM): Selects whether to wait for the next DRAM access with the RAS signal held low (RAS down mode), or to drive the RAS signal high again (RAS up mode), when burst access is enabled for DRAM space (BE = 1), and access to DRAM is interrupted. Caution is required when the HWR and LWR are used as the UCAS and LCAS output pins. For details, see RAS Down Mode and RAS Up Mode in section 6.5.10, Burst Operation.
Bit 2 RDM 0 1 Description DRAM interface: RAS up mode selected DRAM interface: RAS down mode selected (Initial value)
Bit 1Self-Refresh Mode (SRFMD): Specifies DRAM self-refreshing in software standby mode. When any of areas 2 to 5 is designated as DRAM space, DRAM self-refreshing is possible when a transition is made to software standby mode after the SRFMD bit has been set to 1. The normal access state is restored when software standby mode is exited, regardless of the SRFMD setting.
Bit 1 SRFMD 0 1 Description DRAM self-refreshing disabled in software standby mode DRAM self-refreshing enabled in software standby mode (Initial value)
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Bit 0Refresh Pin Enable (RFSHE): Enables or disables RFSH pin refresh signal output. If areas 2 to 5 are not designated as DRAM space, this bit should not be set to 1.
Bit 0 RFSHE 0 1 Description RFSH pin refresh signal output disabled (RFSH pin can be used as input/output port) RFSH pin refresh signal output enabled (Initial value)
6.2.8
Bit
DRAM Control Register B (DRCRB)
7 MXC1 6 MXC0 0 R/W 5 CSEL 0 R/W 4 RCYCE 0 R/W 3
2 TPC 0 R/W
1 RCW 0 R/W
0 RLW 0 R/W
Initial value Read/Write
0 R/W
1
DRCRB is an 8-bit readable/writable register that selects the number of address multiplex column address bits for the DRAM interface, the column address strobe output pin, enabling or disabling of refresh cycle insertion, the number of precharge cycles, enabling or disabling of wait state insertion between RAS and CAS, and enabling or disabling of wait state insertion in refresh cycles. DRCRB is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. The settings in this register are invalid when bits DRAS2 to DRAS0 in DRCRA are all 0.
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Bits 7 and 6Multiplex Control 1 and 0 (MXC1, MXC0): These bits select the row address/column address multiplexing method used on the DRAM interface. In burst operation, the row address used for comparison is determined by the setting of these bits and the bus width of the relevant area set in ABWCR.
Bit 7 MXC1 0 Bit 6 MXC0 0 Description Column address: 8 bits Compared address: Modes 1, 2 Modes 3, 4 1 Column address: 9 bits Compared address: Modes 1, 2 Modes 3, 4 1 0 Column address: 10 bits Compared address: Modes 1, 2 Modes 3, 4 1 Illegal setting 8-bit access space 16-bit access space 8-bit access space 16-bit access space A19 to A10 A19 to A11 A23 to A10 A23 to A11 8-bit access space 16-bit access space 8-bit access space 16-bit access space A19 to A9 A19 to A10 A23 to A9 A23 to A10 8-bit access space 16-bit access space 8-bit access space 16-bit access space A19 to A8 A19 to A9 A23 to A8 A23 to A9
Bit 5CAS Output Pin Select (CSEL): Selects the UCAS and LCAS output pins when areas 2 to 5 are designated as DRAM space.
Bit 5 CSEL 0 1 Description PB4 and PB5 selected as UCAS and LCAS output pins HWR and LWR selected as UCAS and LCAS output pins (Initial value)
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Bit 4Refresh Cycle Enable (RCYCE): CAS-before-RAS enables or disables refresh cycle insertion. When none of areas 2 to 5 has been designated as DRAM space, refresh cycles are not inserted regardless of the setting of this bit.
Bit 4 RCYCE 0 1 Description Refresh cycles disabled DRAM refresh cycles enabled (Initial value)
Bit 3Reserved: This bit cannot be modified and is always read as 1. Bit 2TP Cycle Control (TPC): Selects whether a 1-state or two-state precharge cycle (Tp) is to be used for DRAM read/write cycles and CAS-before-RAS refresh cycles. The setting of this bit does not affect the self-refresh function.
Bit 2 TPC 0 1 Description 1-state precharge cycle inserted 2-state precharge cycle inserted (Initial value)
Bit 1RAS-CAS Wait (RCW): Controls wait state (Trw) insertion between Tr and Tc1 in DRAM read/write cycles. The setting of this bit does not affect refresh cycles.
Bit 1 RCW 0 1 Description Wait state (Trw) insertion disabled One wait state (Trw) inserted (Initial value)
Bit 0Refresh Cycle Wait Control (RLW): Controls wait state (TRW) insertion for CAS-beforeRAS refresh cycles. The setting of this bit does not affect DRAM read/write cycles.
Bit 0 RLW 0 1 Description Wait state (TRW) insertion disabled One wait state (TRW) inserted (Initial value)
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6.2.9
Bit
Refresh Timer Control/Status Register (RTMCSR)
7 CMF 6 CMIE 0 R/W 5 CKS2 0 R/W 4 CKS1 0 R/W 3 CKS0 0 R/W 2
1
0
Initial value Read/Write
0 R/(W)*
1
1
1
RTMCSR is an 8-bit readable/writable register that selects the refresh timer counter clock. When the refresh timer is used as an interval timer, RTMCSR also enables or disables interrupt requests. Bits 7 and 6 of RTMCSR are initialized to 0 by a reset and in the standby modes. Bits 5 to 3 are initialized to 0 by a reset and in hardware standby mode; they are not initialized in software standby mode. Note: Only 0 can be written to clear the flag. Bit 7Compare Match Flag (CMF): Status flag that indicates a match between the values of RTCNT and RTCOR.
Bit 7 CMF 0 Description [Clearing conditions] * * 1 When the chip is reset and in standby mode Read CMF when CMF = 1, then write 0 in CMF (Initial value)
[Setting condition] When RTCNT = RTCOR
Bit 6Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when any of areas 2 to 5 is designated as DRAM space.
Bit 6 CMIE 0 1 Description The CMI interrupt requested by CMF is disabled The CMI interrupt requested by CMF is enabled (Initial value)
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Bits 5 to 3Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be input to RTCNT from among 7 clocks obtained by dividing the system clock (). When the input clock is selected with bits CKS2 to CKS0, RTCNT begins counting up.
Bit 5 Bit 4 Bit 3 CKS2 CKS1 CKS0 Description 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Count operation halted /2 used as counter clock /8 used as counter clock /32 used as counter clock /128 used as counter clock /512 used as counter clock /2048 used as counter clock /4096 used as counter clock (Initial value)
Bits 2 to 0Reserved: These bits cannot be modified and are always read as 1. 6.2.10
Bit
Refresh Timer Counter (RTCNT)
7 6 5 4 3 2 1 0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
RTCNT is an 8-bit readable/writable up-counter. RTCNT is incremented by an internal clock selected by bits CKS2 to CKS0 in RTMCSR. When RTCNT matches RTCOR (compare match), the CMF flag in RTMCSR is set to 1 and RTCNT is cleared to H'00. If the RCYCE bit in DRCRB is set to 1 at this time, a refresh cycle is started. Also, if the CMIE bit in RTMCSR is set to 1, a compare match interrupt (CMI) is generated. RTCNT is initialized to H'00 by a reset and in standby mode.
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6.2.11
Bit
Refresh Time Constant Register (RTCOR)
7 6 5 4 3 2 1 0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
RTCOR is an 8-bit readable/writable register that sets the RTCNT compare-match interval. RTCOR and RTCNT are constantly compared. When their values match, the CMF flag is set to 1 in RTMCSR, and RTCNT is simultaneously cleared to H'00. RTCOR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: Only byte access should be used with this register.
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6.3
6.3.1
Operation
Area Division
The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1Mbyte modes, or 2-Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the memory map.
H'00000 Area 0 (128 kbytes) H'1FFFF H'20000 Area 1 (128 kbytes) H'3FFFF H'40000 Area 2 (128 kbytes) H'5FFFF H'60000 Area 3 (128 kbytes) H'7FFFF H'80000 Area 4 (128 kbytes) H'9FFFF H'A0000 Area 5 (128 kbytes) H'BFFFF H'C0000 H'DFFFF H'E0000 Area 6 (128 kbytes) Area 7 (128 Mbytes) H'BFFFFF H'C00000 H'DFFFFF H'E00000 Area 6 (2 Mbytes) Area 7 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'000000 Area 0 (2 Mbytes)
H'FFFFF
H'FFFFFF
(a) 1-Mbyte modes (modes 1 and 2)
(b) 16-Mbyte modes (modes 3 and 4)
Figure 6.2 Access Area Map for Each Operating Mode Chip select signals (CS0 to CS7) can be output for areas 0 to 7. The bus specifications for each area are selected in ABWCR, ASTCR, WCRH, and WCRL. In 16-Mbyte mode, the area division units can be selected with the RDEA bit in BCR.
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H'000000 Area 0 2 Mbytes H'1FFFFF H'200000 Area 1 2 Mbytes H'3FFFFF H'400000 Area 2 2 Mbytes H'5FFFFF H'600000 Area 3 2 Mbytes H'7FFFFF H'800000 Area 4 2 Mbytes H'9FFFFF H'A00000 Area 5 2 Mbytes H'BFFFFF H'C00000 Area 6 2 Mbytes H'DFFFFF H'E00000 Area 3 2 Mbytes Area 1 2 Mbytes Area 0 2 Mbytes
Area 2 8 Mbytes
Area 7 1.93 Mbytes
Area 4 1.93 Mbytes
H'FEE000 Internal I/O registers (1) H'FEE0FF H'FEE100 Reserved 39.75 kbytes H'FF7FFF H'FF8000 H'FF8FFF H'FF9000 Area 5 4 kbytes Internal I/O registers (1)
H'FFEF1F H'FFEF20 On-chip RAM 4 kbytes On-chip RAM 4 kbytes*
H'FFFEFF H'FFFF00 H'FFFF1F H'FFFF20 Internal I/O registers (2) H'FFFFE9 H'FFFFEA H'FFFFFF Area 7 22 bytes (a) Memory map when RDEA = 1 Note: * Area 6 when the RAME bit is cleared. Internal I/O registers (2) Area 7 22 bytes (b) Memory map when RDEA = 0
Absolute address 8 bits
Figure 6.3 Memory Map in 16-Mbyte Mode (H8/3007)
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Absolute address 16 bits
2 Mbytes
Area 7 67.5 kbytes
Area 6 23.75 kbytes
2 Mbytes
2 Mbytes
2 Mbytes
2 Mbytes
2 Mbytes
2 Mbytes
2 Mbytes
6. Bus Controller
6.3.2
Bus Specifications
The external space bus specifications consist of three elements: (1) bus width, (2) number of access states, and (3) number of program wait states. The bus width and number of access states for on-chip memory and registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. Number of Access States: Two or three access states can be selected with ASTCR. An area for which two-state access is selected functions as a two-state access space, and an area for which three-state access is selected functions as a three-state access space. DRAM space is accessed in four states regardless of the ASTCR settings. When two-state access space is designated, wait insertion is disabled. Number of Program Wait States: When three-state access space is designated in ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. When ASTCR is cleared to 0 for DRAM space, a program wait (Tc1-Tc2 wait) is not inserted. Also, no program wait is inserted in burst ROM space burst cycles. Table 6.3 shows the bus specifications for each basic bus interface area.
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Table 6.3
Bus Specifications for Each Area (Basic Bus Interface)
Bus Specifications (Basic Bus Interface) Bus Width 16 Access States 2 3 Program Wait States 0 0 1 2 3 8 2 3 0 0 1 2 3
ABWCR ASTCR WCRH/WCRL ABWn 0 ASTn 0 1 Wn1
Wn0
0 1
0 1 0 1
1
0 1
0 1
0 1 0 1
6.3.3
Memory Interfaces
The H8/3006 and H8/3007 memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space, an area for which the DRAM interface is designated functions as DRAM space, and area 0 for which the burst ROM interface is designated functions as burst ROM space. 6.3.4 Chip Select Signals
For each of areas 0 to 7, the H8/3006 and H8/3007 can output a chip select signal (CS0 to CS7) that goes low when the corresponding area is selected. Figure 6.4 shows the output timing of a CSn signal. Output of CS0 to CS3: Output of CS0 to CS3 is enabled or disabled in the data direction register (DDR) of the corresponding port. A reset leaves pin CS0 in the output state and pins CS1 to CS3 in the input state. To output chip select signals CS1 to CS3, the corresponding DDR bits must be set to 1. For details, see section 8, I/O Ports.
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Output of CS4 to CS7: Output of CS4 to CS7 is enabled or disabled in the chip select control register (CSCR). A reset leaves pins CS4 to CS7 in the input state. To output chip select signals CS4 to CS7, the corresponding CSCR bits must be set to 1. For details, see section 8, I/O Ports.
Address bus
External address in area n
CSn
Figure 6.4 CSn Signal Output Timing (n = 0 to 7) When the on-chip RAM and on-chip registers are accessed, CS0 to CS7 remain high. The CSn signals are decoded from the address signals. They can be used as chip select signals for SRAM and other devices.
6.4
6.4.1
Basic Bus Interface
Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access area or 16-bit access area) and the data size.
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8-Bit Access Areas: Figure 6.5 illustrates data alignment control for 8-bit access space. With 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses.
Upper data bus Lower data bus D15 D8 D7 D0 Byte size
Word size
1st bus cycle 2nd bus cycle
1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle
Figure 6.5 Access Sizes and Data Alignment Control (8-Bit Access Area) 16-Bit Access Areas: Figure 6.6 illustrates data alignment control for 16-bit access areas. With 16-bit access areas, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address.
Upper data bus Lower data bus D15 D8 D7 D0 Byte size Byte size * Even address * Odd address
Word size Longword size 1st bus cycle 2nd bus cycle
Figure 6.6 Access Sizes and Data Alignment Control (16-Bit Access Area)
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6.4.3
Valid Strobes
Table 6.4 shows the data buses used, and the valid strobes, for the access spaces. In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.4
Area 8-bit access area 16-bit access area
Data Buses Used and Valid Strobes
Access Size Read/Write Byte Read Write Byte Read Write Address

Valid Strobe RD HWR RD HWR LWR RD HWR, LWR
Upper Data Bus Lower Data Bus (D15 to D8) (D7 to D0) Valid Invalid Undetermined data Valid Invalid Valid Undetermined data Valid Valid Invalid Valid Undetermined data Valid Valid Valid
Even Odd Even Odd
Word
Read Write

Notes: 1. Undetermined data means that unpredictable data is output. 2. Invalid means that the bus is in the input state and the input is ignored.
6.4.4
Memory Areas
The initial state of each area is basic bus interface, three-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the following sections should be referred to for further details: 6.4, Basic Bus Interface, 6.5, DRAM Interface, 6.8, Burst ROM Interface. Area 0: When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0. The size of area 0 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4. Areas 1 and 6: When area 1 and 6 external space is accessed, the CS1 and CS6 pin signals respectively can be output. Only the basic bus interface can be used for areas 1 and 6.
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The size of areas 1 and 6 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4. Areas 2 to 5: When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output. Basic bus interface or DRAM interface can be selected for areas 2 to 5. With the DRAM interface, signals CS2 to CS5 are used as RAS signals. The size of areas 2 to 5 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4. Area 7: Area 7 includes the on-chip RAM and registers. The space excluding the on-chip RAM and registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space . When area 7 external space is accessed, the CS7 signal can be output. Only the basic bus interface can be used for the area 7 memory interface. The size of area 7 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4.
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6.4.5
Basic Bus Control Signal Timing
8-Bit, Three-State-Access Areas: Figure 6.7 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper data bus (D15 to D8) is used in accesses to these areas. The LWR pin is always high. Wait states can be inserted.
Bus cycle T1 Address bus CSn AS RD Read access D15 to D8 D7 to D0 HWR LWR Write access D15 to D8 D7 to D0 Valid Undetermined data High Valid Invalid External address in area n T2 T3
Note: n = 7 to 0
Figure 6.7 Bus Control Signal Timing for 8-Bit, Three-State-Access Area
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8-Bit, Two-State-Access Areas: Figure 6.8 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper data bus (D15 to D8) is used in accesses to these areas. The LWR pin is always high. Wait states cannot be inserted.
Bus cycle T1 Address bus CSn AS RD Read access D15 to D8 D7 to D0 HWR LWR Write access D15 to D8 D7 to D0 Valid Undetermined data High Valid Invalid External address in area n T2
Note: n = 7 to 0
Figure 6.8 Bus Control Signal Timing for 8-Bit, Two-State-Access Area
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16-Bit, Three-State-Access Areas: Figures 6.9 to 6.11 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper data bus (D15 to D8) is used in accesses to even addresses and the lower data bus (D7 to D0) in accesses to odd addresses. Wait states can be inserted.
Bus cycle T1 Address bus CSn AS RD Read access D15 to D8 D7 to D0 HWR LWR Write access D15 to D8 D7 to D0 Valid Undetermined data High Valid Invalid Even external address in area n T2 T3
Note: n = 7 to 0
Figure 6.9 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1) (Byte Access to Even Address)
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Bus cycle T1 Address bus CSn AS RD Read access D15 to D8 D7 to D0 HWR LWR Write access D15 to D8 D7 to D0 Undetermined data Valid High Invalid Valid Odd external address in area n T2 T3
Note: n = 7 to 0
Figure 6.10 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2) (Byte Access to Odd Address)
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Bus cycle T1 Address bus CSn AS RD Read access D15 to D8 D7 to D0 HWR LWR Write access D15 to D8 D7 to D0 Valid Valid Valid Valid External address in area n T2 T3
Note: n = 7 to 0
Figure 6.11 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3) (Word Access)
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16-Bit, Two-State-Access Areas: Figures 6.12 to 6.14 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper data bus (D15 to D8) is used in accesses to even addresses and the lower data bus (D7 to D0) in accesses to odd addresses. Wait states cannot be inserted.
Bus cycle T1 Address bus CSn AS RD Read access D15 to D8 D7 to D0 HWR LWR Write access D15 to D8 D7 to D0 Valid Undetermined data High Valid Invalid Even external address in area n T2
Note: n = 7 to 0
Figure 6.12 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1) (Byte Access to Even Address)
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Bus cycle T1 Address bus CSn AS RD Read access D15 to D8 D7 to D0 HWR LWR Write access D15 to D8 D7 to D0 Undetermined data Valid High Invalid Valid Odd external address in area n T2
Note: n = 7 to 0
Figure 6.13 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) (Byte Access to Odd Address)
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Bus cycle T1 Address bus CSn AS RD Read access D15 to D8 D7 to D0 HWR LWR Write access D15 to D8 D7 to D0 Valid Valid Valid Valid External address in area n T2
Note: n = 7 to 0
Figure 6.14 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3) (Word Access) 6.4.6 Wait Control
When accessing external space, the H8/3006 and H8/3007 can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: (1) program wait insertion and (2) pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in three-state access space, according to the settings of WCRH and WCRL.
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Pin Wait Insertion: Setting the WAITE bit in BCR to 1 enables wait insertion by means of the WAIT pin. When external space is accessed in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of in the last T2 or TW state, another TW state is inserted. If the WAIT pin is held low, TW states are inserted until it goes high. This is useful when inserting four or more TW states, or when changing the number of TW states for different external devices. The WAITE bit setting applies to all areas. Pin waits cannot be inserted in DRAM space. Figure 6.15 shows an example of the timing for insertion of one program wait state in 3-state space.
Inserted by program wait Inserted by WAIT pin T2 Tw Tw Tw T3
T1 WAIT Address bus AS RD Read access Data bus
Read data
HWR, LWR Write access Data bus Note: Write data
indicates the timing of WAIT pin sampling.
Figure 6.15 Example of Wait State Insertion Timing
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6.5
6.5.1
DRAM Interface
Overview
The H8/3006 and H8/3007 are provided with a DRAM interface with functions for DRAM control signal (RAS, UCAS, LCAS, WE) output, address multiplexing, and refreshing, that direct connection of DRAM. In the expanded modes, external address space areas 2 to 5 can be designated as DRAM space accessed via the DRAM interface. A data bus width of 8 or 16 bits can be selected for DRAM space by means of a setting in ABWCR. When a 16-bit data bus width is selected, CAS is used for byte access control. In the case of x 16-bit organization DRAM, therefore, the 2-CAS type can be connected. A fast page mode is supported in addition to the normal read and write access modes. 6.5.2 DRAM Space and RAS Output Pin Settings
Designation of areas 2 to 5 as DRAM space, and selection of the RAS output pin for each area designated as DRAM space, is performed by setting bits DRAS2 to DRAS0 in DRCRA. Table 6.5 shows the correspondence between the settings of bits DRAS2 to DRAS0 and the selected DRAM space and RAS output pin. When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than 000 must not be performed. Table 6.5 Settings of Bits DRAS2 to DRAS0 and Corresponding DRAM Space (RAS Output Pin)
Area 4 Normal space Normal space Normal space Normal space DRAM space (CS4) DRAM space (CS4) Area 3 Normal space Normal space DRAM space (CS3) DRAM space (CS3) DRAM space (CS3) Area 2 Normal space DRAM space (CS2) DRAM space (CS2) DRAM space (CS2) DRAM space (CS2)
DRAS2 DRAS1 DRAS0 Area 5 0 0 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 Normal space Normal space Normal space Normal space Normal space DRAM space (CS5)
DRAM space (CS2)*
DRAM space (CS4)*
DRAM space (CS2)*
DRAM space (CS2)*
A single CSn pin serves as a common RAS output pin for a number of areas. Unused CSn pins can be used as input/output ports. Rev.5.00 Sep. 12, 2007 Page 147 of 764 REJ09B0396-0500
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6.5.3
Address Multiplexing
When DRAM space is accessed, the row address and column address are multiplexed. The address multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the number of bits in the DRAM column address. Table 6.6 shows the correspondence between the settings of MXC1 and MXC0 and the address multiplexing method. Table 6.6 Settings of Bits MXC1 and MXC0 and Address Multiplexing Method
DRCRB Column Address A23 to A13 A23 to A13 A23 to A13 A23 to A13 A23 to A13 A12 A11 A10 A9 Address Pins A8 A7 A6 A5 A4 A3 A2 A1 A0 A8
MXC1 MXC0 Bits Row address 0 0 1 1 0 1 Column address 8 bits 9 bits 10 bits Illegal setting
A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A12 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A12 A11 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A8 A7 A6 A5 A4 A3 A2 A1 A0
A12 A11 A10 A9
Note:
*
Row address bit A20 is not multiplexed in 1-Mbyte mode.
6.5.4
Data Bus
If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, x 16-bit organization DRAM can be connected directly. In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data Size and Data Alignment.
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6.5.5
Pins Used for DRAM Interface
Table 6.7 shows the pins used for DRAM interfacing and their functions. Table 6.7
Pin PB4 PB5 HWR LWR CS2 CS3 CS4 CS5 RD P80
DRAM Interface Pins
With DRAM Designated Name UCAS LCAS UCAS LCAS RAS2 RAS3 RAS4 RAS5 WE RFSH Upper column address strobe Lower column address strobe Upper column address strobe Lower column address strobe Row address strobe 2 Row address strobe 3 Row address strobe 4 Row address strobe 5 Write enable Refresh Address Data I/O Output Output Output Output Output Output Output Output Output Output Output I/O Function Upper column address strobe for DRAM space access (when CSEL = 0 in DRCRB) Lower column address strobe for DRAM space access (when CSEL = 0 in DRCRB) Upper column address strobe for DRAM space access (when CSEL = 1 in DRCRB) Lower column address strobe for DRAM space access (when CSEL = 1 in DRCRB) Row address strobe for DRAM space access Row address strobe for DRAM space access Row address strobe for DRAM space access Row address strobe for DRAM space access Write enable for DRAM space write access* Goes low in refresh cycle Row address/column address multiplexed output Data input/output pins
A12 to A0 A12 to A0 D15 to D0 D15 to D0 Note: *
Fixed high in a read access.
6.5.6
Basic Timing
Figure 6.16 shows the basic access timing for DRAM space. The basic DRAM access timing is four states: one precharge cycle (Tp) state, one row address output cycle (Tr) state, and two column address output cycle (Tc1, Tc2) states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion between Tc1 and Tc2, and do not affect the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted between Tc1 and Tc2 in the DRAM access cycle.
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If a DRAM read/write cycle is followed by an access cycle for an external area other than DRAM space when HWR and LWR are selected as the UCAS and LCAS output pins, an idle cycle (Ti) is inserted unconditionally immediately after the DRAM access cycle. See section 6.9, Idle Cycle, for details.
Tp Tr Tc1 Tc2
A23 to A0
Row
Column
AS
High
CSn (RAS) PB4 /PB5 (UCAS / LCAS) Read access RD(WE) High
D15 to D0
PB4 /PB5 (UCAS / LCAS) Write access RD(WE)
D15 to D0
Note: n = 2 to 5
Figure 6.16 Basic Access Timing (CSEL = 0 in DRCRB)
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6.5.7
Precharge State Control
In the H8/3006 and H8/3007, provision is made for the DRAM RAS precharge time by always inserting one RAS precharge state (Tp) when DRAM space is accessed. This can be changed to two Tp states by setting the TPC bit to 1 in DRCRB. The optimum number of Tp cycles should be set according to the DRAM connected and the operating frequency of the H8/3006 and H8/3007 chip. Figure 6.17 shows the timing when two Tp states are inserted. When the TCP bit is set to 1, two Tp states are also used for CAS-before-RAS refresh cycles.
Tp1 Row Column Tp2 Tr Tc1 Tc2
A23 to A0 AS CSn (RAS) PB4 /PB5 (UCAS /LCAS) Read access RD(WE)
High
High
D15 to D0 PB4 /PB5 (UCAS /LCAS)
Write access
RD(WE)
D15 to D0
Note: n = 2 to 5
Figure 6.17 Timing with Two Precharge States (CSEL = 0 in DRCRB)
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6.5.8
Wait Control
In a DRAM access cycle, wait states can be inserted (1) between the Tr state and Tc1 state, and (2) between the Tc1 state and Tc2 state. Insertion of Trw Wait State between Tr and Tc1: One Trw state can be inserted between Tr and Tc1 by setting the RCW bit to 1 in DRCRB. Insertion of Tw Wait State(s) between Tc1 and Tc2: When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 3 Tw states can be inserted between the Tc1 state and Tc2 state by means of settings in WCRH and WCRL. Figure 6.18 shows an example of the timing for wait state insertion. The settings of the RCW bit in DRCRB and of ASTCR, WCRH, and WCRL do not affect refresh cycles. Wait states cannot be inserted in a DRAM space access cycle by means of the WAIT pin.
Tp A23 to A0 Row Column Tr Trw Tc1 Tw Tw Tc2
AS CSn(RAS)
High
Read access
PB4 /PB5 (UCAS /LCAS) RD(WE) D15 to D0 High Read data
PB4 /PB5 (UCAS /LCAS) Write access RD(WE)
D15 to D0 Note: n = 2 to 5
Write data
Figure 6.18 Example of Wait State Insertion Timing (CSEL = 0)
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6.5.9
Byte Access Control and CAS Output Pin
When an access is made to DRAM space designated as a 16-bit-access area in ABWCR, column address strobes (UCAS and LCAS) corresponding to the upper and lower halves of the external data bus are output. In the case of x 16-bit organization DRAM, the 2-CAS type can be connected. Either PB4 and PB5, or HWR and LWR, can be used as the UCAS and LCAS output pins, the selection being made with the CSEL bit in DRCRB. Table 6.8 shows the CSEL bit settings and corresponding output pin selections. When an access is made to DRAM space designated as an 8-bit-access area in ABWCR, only UCAS is output. When the entire DRAM space is designated as 8-bit-access space and CSEL = 0, PB5 can be used as an input/output port. Note that RAS down mode cannot be used when a device other than DRAM is connected to external space and HWR and LWR are used as write strobes. In this case, also, an idle cycle (Ti) is always inserted when an external access to other than DRAM space occurs after a DRAM space access. For details, see section 6.9, Idle Cycle. Table 6.8
CSEL 0 1
CSEL Settings and UCAS and LCAS Output Pins
UCAS PB4 HWR LCAS PB5 LWR
Figure 6.19 shows the control timing.
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Tp
Tr
Tc1
Tc2
A23 to A0
Row
Column
CSn (RAS)
PB4(UCAS) Byte control PB5(LCAS) RD(WE)
Note: n = 2 to 5
Figure 6.19 Control Timing (Upper-Byte Write Access When CSEL = 0) 6.5.10 Burst Operation
With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit to 1 in DRCRA. Burst Access (Fast Page Mode) Operation Timing: Figure 6.20 shows the operation timing for burst access. When there are consecutive access cycles for DRAM space, the column address and CAS signal output cycles (two states) continue as long as the row address is the same for consecutive access cycles. In burst access, too, the bus cycle can be extended by inserting wait states between Tc1 and Tc2. The wait state insertion method and timing are the same as for full access: see section 6.5.8, Wait Control, for details. The row address used for the comparison is determined by the bus width of the relevant area set in bits MXC1 and MXC0 in BRCRB, and in ABWCR. Table 6.9 shows the compared row addresses corresponding to the various settings of bits MXC1 and MXC0, and ABWCR.
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Tp A23 to A0 AS CSn(RAS) PB4 /PB5 (UCAS /LCAS) Read access RD(WE) D15 to D0 PB4 /PB5 (UCAS/LCAS) Write access RD(WE) D15 to D0 High Row Column 1 High Column 2 Tr Tc1 Tc2 Tc1 Tc2
Note: n = 2 to 5
Figure 6.20 Operation Timing in Fast Page Mode
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Table 6.9
Correspondence between Settings of MXC1 and MXC0 Bits and ABWCR, and Row Address Compared in Burst Access
DRCRB ABWCR ABWn 0 1 1 0 1 1 0 0 1 1
Operating Mode Modes 1 and 2 (1-Mbyte)
MXC1 0
MXC0 0
Bus Width 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits
Compared Row Address A19 to A9 A19 to A8 A19 to A10 A19 to A9 A19 to A11 A19 to A10 Illegal setting A23 to A9 A23 to A8 A23 to A10 A23 to A9 A23 to A11 A23 to A10 Illegal setting
Modes 3 and 4 (16-Mbyte)
0
0
0 1
16 bits 8 bits 16 bits 8 bits 16 bits 8 bits
1
0 1
1
0
0 1
1 Note: n = 2 to 5
RAS Down Mode and RAS Up Mode: With DRAM provided with fast page mode, as long as accesses are to the same row address, burst operation can be continued without interruption even if accesses are not consecutive by holding the RAS signal low. * RAS Down Mode To select RAS down mode, set the BE and RDM bits to 1 in DRCRA. If access to DRAM space is interrupted and another space is accessed, the RAS signal is held low during the access to the other space, and burst access is performed if the row address of the next DRAM space access is the same as the row address of the previous DRAM space access. Figure 6.21 shows an example of the timing in RAS down mode.
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External space access Tc2 T1 T2
DRAM access Tp Tr Tc1
DRAM access Tc1 Tc2
A23 to A0
AS
CSn (RAS) PB4/PB5 (UCAS/LCAS) D15 to D0
Note: n = 2 to 5
Figure 6.21 Example of Operation Timing in RAS Down Mode (CSEL = 0) When RAS down mode is selected, the conditions for an asserted RASn signal to return to the high level are as shown below. The timing in these cases is shown in figure 6.22. When DRAM space with a different row address is accessed Immediately before a CAS-before-RAS refresh cycle When the BE bit or RDM bit is cleared to 0 in DRCRA Immediately before release of the external bus
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DRAM access cycle
RASn
(a) Access to DRAM space with a different row address CBR refresh cycle
RASn (b) CAS-before-RAS refresh cycle DRCRA write cycle
RASn
(c) BE bit or RDM bit cleared to 0 in DRCRA External bus released
RASn (d) External bus released Note: n = 2 to 5
High-impedance
Figure 6.22 RASn Negation Timing when RAS Down Mode Is Selected
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When RAS down mode is selected, the CAS-before-RAS refresh function provided with this DRAM interface must always be used as the DRAM refreshing method. When a refresh operation is performed, the RAS signal goes high immediately beforehand. The refresh interval setting must be made so that the maximum DRAM RAS pulse width specification is observed. When the self-refresh function is used, the RDM bit must be cleared to 0, and RAS up mode selected, before executing a SLEEP instruction in order to enter software standby mode. Select RAS down mode again after exiting software standby mode. Note that RAS down mode cannot be used when HWR and LWR are selected for UCAS and LCAS, a device other than DRAM is connected to external space, and HWR and LWR are used as write strobes. * RAS Up Mode To select RAS up mode, clear the RDM bit to 0 in DRCRA. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal returns to the high level. Burst operation is only performed if DRAM space is continuous. Figure 6.23 shows an example of the timing in RAS up mode.
DRAM access Tp Tr Tc1 Tc2 DRAM access Tc1 Tc2 External space access T1 T2
A23 to A0
AS CSn(RAS) PB4/PB5 (UCAS/LCAS) D15 to D0
Note: n = 2 to 5
Figure 6.23 Example of Operation Timing in RAS Up Mode
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6.5.11
Refresh Control
The H8/3006 and H8/3007 are provided with a CAS-before-RAS (CBR) function and self-refresh function as DRAM refresh control functions. CAS-Before-RAS (CBR) Refreshing: To select CBR refreshing, set the RCYCE bit to 1 in DRCRB. With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in RTMCSR, and a refresh request is generated when the count matches the value set in RTCOR (compare match). At the same time, RTCNT is reset and starts counting up again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits CKS2 to CKS0. A refresh cycle is executed after this refresh request has been accepted and the DRAM interface has acquired the bus. Set a value in bits CKS2 to CKS0 in RTCOR that will meet the refresh interval specification for the DRAM used. When RAS down mode is used, set the refresh interval so that the maximum RAS pulse width specification is met. RTCNT starts counting up when bits CKS2 to CKS0 are set. RTCNT and RTCOR settings should therefore be completed before setting bits CKS2 to CKS0. Also note that a repeat refresh request generated during a bus request, or a refresh request during refresh cycle execution, will be ignored. RTCNT operation is shown in figure 6.24, compare match timing in figure 6.25, and CBR refresh timing in figures 6.26 and 6.27.
RTCNT RTCOR
H'00 Refresh request
Figure 6.24 RTCNT Operation
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RTCNT
N
H'00
RTCOR
N
Refresh request signal and CMF bit setting signal
Figure 6.25 Compare Match Timing
TRp TR1 TR2
Address bus Area 2 start address
CSn(RAS) PB4/PB5 (UCAS/LCAS) RD(WE)
High
RFSH
AS
High
Figure 6.26 CBR Refresh Timing (CSEL = 0, TPC = 0, RLW = 0) The basic CBS refresh cycle timing comprises three states: one RAS precharge cycle (TRP) state, and two RAS output cycle (TR1, TR2) states. Either one or two states can be selected for the RAS precharge cycle. When the TPC bit is set to 1 in DRCRB, RAS signal output is delayed by one cycle. This does not affect the timing of UCAS and LCAS output.
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Use the RLW bit in DRCRB to adjust the RAS signal width. A single refresh wait state (TRW) can be inserted between the TR1 state and TR2 state by setting the RLW bit to 1. The RLW bit setting is valid only for CBR refresh cycles, and does not affect DRAM read/write cycles. The number of states in the CBR refresh cycle is not affected by the settings in ASTCR, WCRH, or WCRL, or by the state of the WAIT pin. Figure 6.27 shows the timing when the TPC bit and RLW bit are both set to 1.
TRp1 TRP2 TR1 TRW TR2
Area 2 start address
Address bus
CSn(RAS)
PB4/PB5 (UCAS/LCAS) RD(WE) High
RFSH
AS
High
Figure 6.27 CBR Refresh Timing (CSEL = 0, TPC = 1, RLW = 1) DRAM must be refreshed immediately after powering on in order to stabilize its internal state. When using the H8/3006 and H8/3007 CAS-before-RAS refresh function, therefore, a DRAM stabilization period should be provided by means of interrupts by another timer module, or by counting the number of times bit 7 (CMF) of RTMCSR is set, for instance, immediately after bits DRAS2 to DRAS0 have been set in DRCRA.
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Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. The H8/3006 and H8/3007 have a function that places the DRAM in self-refresh mode when the chip enters software standby mode. To use the self-refresh function, set the SRFMD bit to 1 in DRCRA. When a SLEEP instruction is subsequently executed in order to enter software standby mode, the CAS and RAS signals are output and the DRAM enters self-refresh mode, as shown in figure 6.28. When the chip exits software standby mode, CAS and RAS outputs go high. The following conditions must be observed when the self-refresh function is used: * When burst access is selected, RAS up mode must be selected before executing a SLEEP instruction in order to enter software standby mode. Therefore, if RAS down mode has been selected, the RDM bit in DRCRA must be cleared to 0 and RAS up mode selected before executing the SLEEP instruction. Select RAS down mode again after exiting software standby mode. * The instruction immediately following a SLEEP instruction must not be located in an area designated as DRAM space. The self-refresh function will not work properly unless the above conditions are observed.
Software standby mode Address bus CSn(RAS) PB4(UCAS) PB5(LCAS) RD(WE) RFSH High-impedance Oscillation stabilization time
Figure 6.28 Self-Refresh Timing (CSEL = 0)
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Refresh Signal (RFSH): A refresh signal (RFSH) that transmits a refresh cycle off-chip can be output by setting the RFSHE bit to 1 in DRCRA. RFSH output timing is shown in figures 6.26, 6.27, and 6.28. 6.5.12 Examples of Use
Examples of DRAM connection and program setup procedures are shown below. When the DRAM interface is used, check the DRAM device characteristics and choose the most appropriate method of use for that device.
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Connection Examples * Figure 6.29 shows typical interconnections when using two 2-CAS type 16-Mbit DRAMs using a x 16-bit organization, and the corresponding address map. The DRAMs used in this example are of the 10-bit row address x 10-bit column address type. Up to four DRAMs can be connected by designating areas 2 to 5 as DRAM space.
2-CAS 16-Mbit DRAM 10-bit row address x 10-bit column address x 16-bit organization RAS UCAS LCAS WE A9-A0 D15-D0 OE
H8/3006 and H8/3007 CS2 (RAS2) CS3 (RAS3) PB4 (UCAS) PB5(LCAS) RD (WE) A10-A1 D15-D0
No.1
RAS UCAS LCAS WE No.2
A9-A0 D15-D0 OE (a) Interconnections (example) PB4 (UCAS)
15 87
PB5 (LCAS)
0
H'400000 Area 2 H'5FFFFE H'600000 Area 3 H'7FFFFE H'800000 Area 4 H'9FFFFE H'A00000 Area 5 H'BFFFFE (b) Address map Normal Normal DRAM (No. 2) DRAM (No. 1) CS2 (RAS2) CS3 (RAS3) CS4 CS5
Figure 6.29 Interconnections and Address Map for 2-CAS 16-Mbit DRAMs with x 16-Bit Organization
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* Figure 6.30 shows typical interconnections when using two 16-Mbit DRAMs using a x 8-bit organization, and the corresponding address map. The DRAMs used in this example are of the 11-bit row address x 10-bit column address type. The CS2 pin is used as a common RAS output pin for area 2 and area 3. When the DRAM address space spans a number of contiguous areas, as in this example, the appropriate setting of bits DRAS2 to DRAS0 enables a single CS pin to be used as the common RAS output pin for a number of areas, and makes it possible to directly connect large-capacity DRAM with address space that spans a maximum of four areas. Any unused CS pins (in this example, the CS3 pin) can be used as input/output ports.
2-CAS 16-Mbit DRAM 11-bit row address x 10-bit column address x 8-bit organization RAS CAS WE A10-A0 D7-D0 No.1
H8/3006 and H8/3007 CS2 (RAS2) PB4 (UCAS) PB5 (LCAS) RD (WE) A21, A10-A1
D15-D8 D7-D0
OE
RAS CAS WE No.2
A10-A0 D7-D0 OE (a) Interconnections (example) PB4 (UCAS)
15 87
PB5 (LCAS)
0
H'400000 Area 2 H'5FFFFE H'600000 Area 3 H'7FFFFE H'800000 Area 4 H'9FFFFE H'A00000 Area 5 H'BFFFFE 16-Mbyte mode (b) Address map Normal Normal CS4 CS5 DRAM (No.1) DRAM (No.2) CS2(RAS2)
Figure 6.30 Interconnections and Address Map for 16-Mbit DRAMs with x 8-Bit Organization
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* Figure 6.31 shows typical interconnections when using two 4-Mbit DRAMs, and the corresponding address map. The DRAMs used in this example are of the 9-bit row address x 9-bit column address type. In this example, upper address decoding allows multiple DRAMs to be connected to a single area. The RFSH pin is used in this case, since both DRAMs must be refreshed simultaneously. However, note that RAS down mode cannot be used in this interconnection example.
2-CAS 4-Mbit DRAM 9-bit row address x 9-bit column address x 16-bit organization RAS UCAS LCAS WE
H8/3006 and H8/3007 CS2 (RAS2) PB4 (UCAS) PB5 (LCAS) RD (WE) RFSH A19 A9-A1 D15-D0
No.1
A8-A0 D15-D0 OE
RAS UCAS LCAS WE
No.2
A8-A0 D15-D0 OE (a) Interconnections (example) PB4 (UCAS) 15 H'400000 DRAM (No.1) H'47FFFE H'480000 DRAM (No.2) Area 2 H'4FFFFE H'500000 Not used H'5FFFFE 16-Mbyte mode (b) Address map CS2 (RAS2) PB5 (LCAS) 0
87
Figure 6.31 Interconnections and Address Map for 2-CAS 4-Mbit DRAMs with x 16-Bit Organization
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Example of Program Setup Procedure: Figure 6.32 shows an example of the program setup procedure.
Set ABWCR
Set RTCOR
Set bits CKS2 to CKS0 in RTMCSR
Set DRCRB
Set DRCRA
Wait for DRAM stabilization time
DRAM can be accessed
Figure 6.32 Example of Setup Procedure when Using DRAM Interface 6.5.13 Usage Notes
Note the following points when using the DRAM refresh function. * Refresh cycles will not be executed when the external bus released state, software standby mode, or a bus cycle is extended by means of wait state insertion. Refreshing must therefore be performed by other means in these cases. * If a refresh request is generated internally while the external bus is released, the first request is retained and a single refresh cycle will be executed after the bus-released state is cleared. Figure 6.33 shows the bus cycle in this case. * When a bus cycle is extended by means of wait state insertion, the first request is retained in the same way as when the external bus has been released. In the event of contention with a bus request from an external bus master when a transition is made to software standby mode, the BACK and strobe states may be indeterminate after the transition to software standby mode (see figure 6.34). When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before executing the SLEEP instruction.
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6. Bus Controller
Similar contention in a transition to self-refresh mode may prevent dependable strobe waveform output. This can also be avoided by clearing the BRLW bit to 0 in BRCR. * Immediately after self-refreshing is cleared, external bus release is possible during a given period until the start of a CPU cycle. Attention must be paid to the RAS state to ensure that the specification for the RAS precharge time immediately after self-refreshing is met.
External bus released Refresh cycle CPU cycle Refresh cycle
RFSH Refresh request
BACK
Figure 6.33
Bus-Released State and Refresh Cycles
Software standby mode
BREQ
BACK
Address bus
Strobe
Figure 6.34 Bus-Released State and Software Standby Mode
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6. Bus Controller
Oscillation stabilization CPU internal cycle time on exit from software (period in which external standby mode bus can be released) CPU cycle
Address bus RAS CAS
@SP
Figure 6.35 Self-Refresh Clearing
6.6
6.6.1
Interval Timer
Operation
When DRAM is not connected to the H8/3006 and H8/3007 chip, the refresh timer can be used as an interval timer by clearing bits DRAS2 to DRAS0 in DRCRA to 0. After setting RTCOR, selection a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to 1. Timing of Setting of Compare Match Flag and Clearing by Compare Match: The CMF flag in RTMCSR is set to 1 by a compare match output when the RTCOR and RTCNT values match. The compare match signal is generated in the last state in which the values match (when RTCNT is updated from the matching value to a new value). Accordingly, when RTCNT and RTCOR match, the compare match signal is not generated until the next counter clock pulse. Figure 6.36 shows the timing.
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6. Bus Controller
RTCNT
N
H'00
RTCOR
N
Compare match signal
CMF
Figure 6.36 Timing of CMF Flag Setting Operation in Power-Down State: The interval timer operates in sleep mode. It does not operate in hardware standby mode. In software standby mode, RTCNT and RTMCSR bits 7 and 6 are initialized, but RTMCSR bits 5 to 3 and RTCOR retain their settings prior to the transition to software standby mode. Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the T3 state of an RTCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 6.37.
T1 T2 T3
Address bus
RTCNT address
Internal write signal
Counter clear signal
RTCNT
N
H'00
Figure 6.37 Contention between RTCNT Write and Clear
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6. Bus Controller
Contention between RTCNT Write and Increment: If an increment pulse occurs in the T3 state of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See figure 6.38.
T1 T2 T3
Address bus
RTCNT address
Internal write signal
RTCNT input clock
RTCNT
N
M
Counter write data
Figure 6.38 Contention between RTCNT Write and Increment Contention between RTCOR Write and Compare Match: If a compare match occurs in the T3 state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited. See figure 6.39.
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T1 T2 T3
Address bus
RTCOR address
Internal write signal
RTCNT
N
N+1
RTCOR
N
M RTCOR write data
Compare match signal Inhibited
Figure 6.39 Contention between RTCOR Write and Compare Match RTCNT Operation at Internal Clock Source Switchover: Switching internal clock sources may cause RTCNT to increment, depending on the switchover timing. Table 6.10 shows the relation between the time of the switchover (by writing to bits CKS2 to CKS0) and the operation of RTCNT. The RTCNT input clock is generated from the internal clock source by detecting the falling edge of the internal clock. If a switchover is made from a high clock source to a low clock source, as in case No. 3 in table 6.10, the switchover will be regarded as a falling edge, an RTCNT clock pulse will be generated, and RTCNT will be incremented.
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6. Bus Controller
Table 6.10 Internal Clock Switchover and RTCNT Operation
No. CKS2 to CKS0 Write Timing Low Low switchover*1 RTCNT Operation
1
Old clock source
New clock source
RTCNT clock
RTCNT
N
N+1
CKS bits rewritten 2 Low High switchover*2
Old clock source
New clock source
RTCNT clock
RTCNT
N
N+1
N+2
CKS bits rewritten
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6. Bus Controller
No. CKS2 to CKS0 Write Timing High Low switchover*3
RTCNT Operation
3
Old clock source
New clock source *4 RTCNT clock
RTCNT
N
N+1
N+2
CKS bits rewritten 4 High High switchover*4
Old clock source
New clock source
RTCNT clock
RTCNT
N
N+1
N+2
CKS bits rewritten
Notes: 1. Including switchovers from a low clock source to the halted state, and from the halted state to a low clock source. 2. Including switchover from the halted state to a high clock source. 3. Including switchover from a high clock source to the halted state. 4. The switchover is regarded as a falling edge, causing RTCNT to increment.
6.7
Interrupt Sources
Compare match interrupts (CMI) can be generated when the refresh timer is used as an interval timer. Compare match interrupt requests are masked/unmasked with the CMIE bit in RTMCSR.
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6. Bus Controller
6.8
6.8.1
Burst ROM Interface
Overview
With the H8/3006 and H8/3007, external space area 0 can be designated as burst ROM space, and burst ROM space interfacing can be performed. The burst ROM interface enables ROM with burst access capability to be accessed at high speed. Area 0 is designated as burst ROM space by means of the BROME bit in BCR. Continuous burst access of a maximum or four or eight words can be performed on external space area 0. Two or three states can be selected for burst access. 6.8.2 Basic Timing
The number of states in the initial cycle (full access) and a burst cycle of the burst ROM interface is determined by the setting of the AST0 bit in ASTCR. When the AST0 bit is set to 1, wait states can also be inserted in the initial cycle. Wait states cannot be inserted in a burst cycle. Burst access of up to four words is performed when the BRSTS0 bit is cleared to 0 in BCR, and burst access of up to eight words when the BRSTS0 bit is set to 1. The number of burst access states is two when the BRSTS1 bit is cleared to 0, and three when the BRSTS1 bit is set to 1. The basic access timing for burst ROM space is shown in figure 6.40.
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6. Bus Controller
Full access T1 T2 T3 T1 Burst access T2 T1 T2
Address bus
Only lower address changes
CS0 AS
RD
Data bus
Read data
Read data
Read data
Figure 6.40 Example of Burst ROM Access Timing 6.8.3 Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. Wait states cannot be inserted in a burst cycle.
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6. Bus Controller
6.9
6.9.1
Idle Cycle
Operation
When the H8/3006 and H8/3007 chip accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following cases: (1) when read accesses between different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when external address space other than DRAM space is accessed immediately after a DRAM space access. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, which has a long output floating time, and high-speed memory, I/O interfaces, and so on. The ICIS1 and ICIS0 bits in BCR both have an initial value of 1, so that an idle cycle is inserted in the initial state. If there are no data collisions, the ICIS bits can be cleared. Consecutive Reads between Different Areas: If consecutive reads between different areas occur while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle. Figure 6.41 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A Bus cycle B Address bus RD Data bus Data collision Long buffer-off time (a) Idle cycle not inserted T1 T2 T3 T1 T2 Address bus RD Data bus Bus cycle A Bus cycle B T1 T2 T3 Ti T1 T2
(b) Idle cycle inserted
Figure 6.41 Example of Idle Cycle Operation (1) (ICIS1 = 1) Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.42 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
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6. Bus Controller
In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A Bus cycle B Address bus RD HWR Data bus Long buffer-off time (a) Idle cycle not inserted Data collision (b) Idle cycle inserted T1 T2 T3 T1 T2 Address bus RD HWR Data bus Bus cycle A Bus cycle B T1 T2 T3 Ti T1 T2
Figure 6.42 Example of Idle Cycle Operation (2) (ICIS0 = 1) External Address Space Access Immediately after DRAM Space Access: If a DRAM space access is followed by a non-DRAM external access when HWR and LWR have been selected as the UCAS and LCAS output pins by means of the CSEL bit in DRCRB, a Ti cycle is inserted regardless of the settings of bits ICIS0 and ICIS1 in BCR. Figure 6.43 shows an example of the operation. This is done to prevent simultaneous changing of the HWR and LWR signals used as UCAS and LCAS in DRAM space and CSn for the space in the next cycle, and so avoid an erroneous write to the external device in the next cycle. A Ti cycle is not inserted when PB4 and PB5 have been selected as the UCAS and LCAS output pins. In the case of consecutive DRAM space access precharge cycles (Tp), the ICIS0 and ICIS1 bit settings are invalid. In the case of consecutive reads between different areas, for example, if the second access is a DRAM access, only a Tp cycle is inserted, and a Ti cycle is not. The timing in this case is shown in figure 6.44.
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6. Bus Controller
Bus cycle A (DRAM access cycle) Bus cycle B Tp Tr Tc1 Tc2 T1 T2 Bus cycle A (DRAM access cycle) Bus cycle B
Address bus HWR/LWR (UCAS/LCAS) CSn Simultaneous change of HWR/LWR and CSn
Address bus HWR/LWR (UCAS/LCAS) CSn
Tp
Tr
Tc1 Tc2
Ti
T1
T2
(a) Idle cycle not inserted
(b) Idle cycle inserted
Figure 6.43 Example of Idle Cycle Operation (3) (HWR/LWR Used as UCAS/LCAS)
External read DRAM space read
T1
Address bus RD UCAS/LCAS Address bus
T2
T3
Tp
Tr
Tc1
Tc2
Figure 6.44 Example of Idle Cycle Operation (4) (Consecutive Precharge Cycles) Usage Notes: When non-insertion of idle cycles is set, the rise (negation) of RD and the fall (assertion) of CSn may occur simultaneously. An example of the operation is shown in figure 6.45. If consecutive reads between different external areas occur while the ICIS1 bit is cleared to 0 in BCR, or if a write cycle to a different external area occurs after an external read while the ICIS0 bit is cleared to 0, the RD negation in the first read cycle and the CSn assertion in the following bus cycle will occur simultaneously. Therefore, depending on the output delay time of each signal, it is possible that the low-level output of RD in the preceding read cycle and the low-level output of CSn in the following bus cycle will overlap.
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A setting whereby idle cycle insertion is not performed can be made only when RD and CSn do not change simultaneously, or when it does not matter if they do.
Bus cycle A
Address bus RD CSn
Bus cycle B T1 T2
Address bus RD CSn
Bus cycle A T1 T2 T3
Bus cycle B Ti T1 T2
T1
T2
T3
Simultaneous change of RD and CSn Possibility of mutual overlap
(a) Idle cycle not inserted (b) Idle cycle inserted
Figure 6.45 Example of Idle Cycle Operation (5) 6.9.2 Pin States in Idle Cycle
Table 6.11 shows the pin states in an idle cycle. Table 6.11 Pin States in Idle Cycle
Pins A23 to A0 D15 to D0 CSn UCAS, LCAS AS RD HWR LWR Note: * Pin State Next cycle address value High impedance High* High High High High High Remains low in DRAM space RAS down mode.
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6. Bus Controller
6.10
Bus Arbiter
The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are four bus masters: the CPU, DMA controller (DMAC), DRAM interface, and an external bus master. When a bus master has the bus right it can carry out read, write, or refresh access. Each bus master uses a bus request signal to request the bus right. At fixed times the bus arbiter determines priority and uses a bus acknowledge signal to grant the bus to a bus master, which can the operate using the bus. The bus arbiter checks whether the bus request signal from a bus master is active or inactive, and returns an acknowledge signal to the bus master. When two or more bus masters request the bus, the highest-priority bus master receives an acknowledge signal. The bus master that receives an acknowledge signal can continue to use the bus until the acknowledge signal is deactivated. The bus master priority order is: (High) External bus master > DRAM interface > DMAC > CPU (Low)
The bus arbiter samples the bus request signals and determines priority at all times, but it does not always grant the bus immediately, even when it receives a bus request from a bus master with higher priority than the current bus master. Each bus master has certain times at which it can release the bus to a higher-priority bus master. 6.10.1 Operation
CPU: The CPU is the lowest-priority bus master. If the DMAC, DRAM interface, or an external bus master requests the bus while the CPU has the bus right, the bus arbiter transfers the bus right to the bus master that requested it. The bus right is transferred at the following times: * The bus right is transferred at the boundary of a bus cycle. If word data is accessed by two consecutive byte accesses, however, the bus right is not transferred between the two byte accesses. * If another bus master requests the bus while the CPU is performing internal operations, such as executing a multiply or divide instruction, the bus right is transferred immediately. The CPU continues its internal operations. * If another bus master requests the bus while the CPU is in sleep mode, the bus right is transferred immediately.
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6. Bus Controller
DMAC: When the DMAC receives an activation request, it requests the bus right from the bus arbiter. If the DMAC is bus master and the DRAM interface or an external bus master requests the bus, the bus arbiter transfers the bus right from the DMAC to the bus master that requested the bus. The bus right is transferred at the following times. The bus right is transferred when the DMAC finishes transferring one byte or one word. A DMAC transfer cycle consists of a read cycle and a write cycle. The bus right is not transferred between the read cycle and the write cycle. There is a priority order among the DMAC channels. For details see section 7.4.9, MultipleChannel Operation. DRAM Interface: The DRAM interface requests the bus right from the bus arbiter when a refresh cycle request is issued, and releases the bus at the end of the refresh cycle. For details see section 6.5, DRAM Interface. External Bus Master: When the BRLE bit is set to 1 in BRCR, the bus can be released to an external bus master. The external bus master has highest priority, and requests the bus right from the bus arbiter y driving the BREQ signal low. Once the external bus master acquires the bus, it keeps the bus until the BREQ signal goes high. While the bus is released to an external bus master, the H8/3006 and H8/3007 chip holds the address bus, data bus, bus control signals (AS, RD, HWR, and LWR), and chip select signals (CSn: n = 7 to 0) in the high-impedance state, and holds the BACK pin in the low output state. The bus arbiter samples the BREQ pin at the rise of the system clock (). If BREQ is low, the bus is released to the external bus master at the appropriate opportunity. The BREQ signal should be held low until the BACK signal goes low. When the BREQ pin is high in two consecutive samples, the BACK pin is driven high to end the bus-release cycle. Figure 6.46 shows the timing when the bus right is requested by an external bus master during a read cycle in a two-state access area. There is a minimum interval of three states from when the BREQ signal goes low until the bus is released.
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6. Bus Controller
CPU cycles T0 T1 T2 External bus released CPU cycles
Address bus Data bus AS RD
Address
High-impedance High-impedance
High-impedance
High-impedance High High-impedance
HWR, LWR BREQ BACK Minimum 3 cycles (1) (2) (3)
(4)
(5)
(6)
Figure 6.46 Example of External Bus Master Operation In the event of contention with a bus request from an external bus master when a transition is made to software standby mode, the BACK and strobe states may be indeterminate after the transition to software standby mode (see figure 6.34). When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before executing the SLEEP instruction.
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6. Bus Controller
6.11
6.11.1
Register and Pin Input Timing
Register Write Timing
ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR, WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.47 shows the timing when an instruction fetched from area 0 changes area 0 from three-state access to two-state access.
T1 Address bus 3-state access to area 0 T2 T3 T1 T2 T3 T1 T2
ASTCR address 2-state access to area 0
Figure 6.47 ASTCR Write Timing DDR and CSCR Write Timing: Data written to DDR or CSCR for the port corresponding to the CSn pin to switch between CSn output and generic input takes effect starting from the T3 state of the DDR write cycle. Figure 6.48 shows the timing when the CS1 pin is changed from generic input to CS1 output.
T1 Address bus CS1 High-impedance T2 T3
P8DDR address
Figure 6.48 DDR Write Timing
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6. Bus Controller
BRCR Write Timing: Data written to BRCR to switch between A23, A22, A21, or A20 output and generic input or output takes effect starting from the T3 state of the BRCR write cycle. Figure 6.49 shows the timing when a pin is changed from generic input to A23, A22, A21, or A20 output.
T1 Address bus PA7 to PA4 (A23 to A20) BRCR address T2 T3
High-impedance
Figure 6.49 BRCR Write Timing 6.11.2 BREQ Pin Input Timing
After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high level before BACK goes lows, the bus arbiter may operate incorrectly. To terminate the external-bus-released state, hold the BREQ signal high for at least three states. If BREQ is high for too short an interval, the bus arbiter may operate incorrectly.
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7. DMA Controller
Section 7 DMA Controller
7.1 Overview
The H8/3006 and H8/3007 have an on-chip DMA controller (DMAC) that can transfer data on up to four channels. When the DMA controller is not used, it can be independently halted to conserve power. For details see section 19.6, Module Standby Function. 7.1.1 Features
DMAC features are listed below. * Selection of short address mode or full address mode Short address mode 8-bit source address and 24-bit destination address, or vice versa Maximum four channels available Selection of I/O mode, idle mode, or repeat mode Full address mode 24-bit source and destination addresses Maximum two channels available Selection of normal mode or block transfer mode * Directly addressable 16-Mbyte address space * Selection of byte or word transfer * Activation by internal interrupts, external requests, or auto-request (depending on transfer mode) 16-bit integrated timer unit (ITU) compare match/input capture interrupts (x3) Serial communication interface (SCI channel 0) transmit-data-empty/receive-data-full interrupts External requests Auto-request A/D converter conversion-end interrupt
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7. DMA Controller
7.1.2
Block Diagram
Figure 7.1 shows a DMAC block diagram.
Internal address bus
Internal interrupts
IMIA0 IMIA1 IMIA2 ADI TXI0 RXI0 DREQ0 DREQ1 TEND0 TEND1 Control logic Channel 0
Address buffer Arithmetic-logic unit MAR0A Channel 0A IOAR0A
MAR0B Channel 0B IOAR0B ETCR0B MAR1A Channel 1A IOAR1A ETCR1A MAR1B Channel 1B IOAR1B ETCR1B
DTCR0A Interrupt DEND0A DEND0B signals DEND1A DEND1B DTCR0B DTCR1A DTCR1B Channel 1
Data buffer
Internal data bus Legend: DTCR: Data transfer control register MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register
Figure 7.1 Block Diagram of DMAC 7.1.3 Functional Overview
Table 7.1 gives an overview of the DMAC functions.
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Module data bus
ETCR0A
7. DMA Controller
Table 7.1
DMAC Functional Overview
Address Reg. Length
Transfer Mode Short address mode I/O mode * * * * * Transfers one byte or one word per request Increments or decrements the memory address by 1 or 2 Executes 1 to 65,536 transfers Transfers one byte or one word per request Holds the memory address fixed
Activation *
Source
Destination 8
*
Compare match/input 24 capture A interrupts from 16-bit timer channels 0 to 2 Transmit-data-empty interrupt from SCI channel 0
Idle mode
* * *
Conversion-end interrupt from A/D converter Receive-data-full interrupt from SCI channel 0 External request
8
24
* Executes 1 to 65,536 transfers Repeat mode * * * Transfers one byte or one word per request Increments or decrements the memory address by 1 or 2 Executes a specified number (1 to 255) of transfers, then returns to the initial state and continues Auto-request Retains the transfer request internally Executes a specified number(1 to 65,536) of transfers continuously Selection of burst mode or cyclesteal mode External request Transfers one byte or one word per request Executes 1 to 65,536 transfers
24
8
Full address mode
Normal mode *
* *
Auto-request External request
24
24
*
Block transfer * * * *
*
Transfers one block of a specified size per request * Executes 1 to 65,536 transfers Allows either the source or destination to * be a fixed block area Block size can be 1 to 255 bytes or words
Compare match/ input capture A interrupts from 16-bit timer channels 0 to 2 External request Conversion-end interrupt from A/D converter
24
24
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7. DMA Controller
7.1.4
Pin Configuration
Table 7.2 lists the DMAC pins. Table 7.2
Channel 0
DMAC Pins
Name DMA request 0 Transfer end 0 Abbreviation DREQ0 TEND0 DREQ1 TEND1 Input/ Output Input Output Input Output Function External request for DMAC channel 0 Transfer end on DMAC channel 0 External request for DMAC channel 1 Transfer end on DMAC channel 1
1
DMA request 1 Transfer end 1
Note: External requests cannot be made to channel A in short address mode.
7.1.5
Register Configuration
Table 7.3 lists the DMAC registers. Table 7.3 DMAC Registers
Abbreviation R/W MAR0AR MAR0AE MAR0AH MAR0AL IOAR0A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'00 Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'00
Channel Address* Name 0 H'FFF20 H'FFF21 H'FFF22 H'FFF23 H'FFF26 H'FFF24 H'FFF25 H'FFF27 H'FFF28 H'FFF29 H'FFF2A H'FFF2B H'FFF2E H'FFF2C H'FFF2D H'FFF2F Memory address register 0AR Memory address register 0AE Memory address register 0AH Memory address register 0AL I/O address register 0A
Execute transfer count register 0AH ETCR0AH Execute transfer count register 0AL ETCR0AL Data transfer control register 0A Memory address register 0BR Memory address register 0BE Memory address register 0BH Memory address register 0BL I/O address register 0B DTCR0A MAR0BR MAR0BE MAR0BH MAR0BL IOAR0B
Execute transfer count register 0BH ETCR0BH Execute transfer count register 0BL ETCR0BL Data transfer control register 0B DTCR0B
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7. DMA Controller Channel Address* Name 1 H'FFF30 H'FFF31 H'FFF32 H'FFF33 H'FFF36 H'FFF34 H'FFF35 H'FFF37 H'FFF38 H'FFF39 H'FFF3A H'FFF3B H'FFF3E H'FFF3C H'FFF3D H'FFF3F Note: * Memory address register 1AR Memory address register 1AE Memory address register 1AH Memory address register 1AL I/O address register 1A Abbreviation R/W MAR1AR MAR1AE MAR1AH MAR1AL IOAR1A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'00 Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'00
Execute transfer count register 1AH ETCR1AH Execute transfer count register 1AL ETCR1AL Data transfer control register 1A Memory address register 1BR Memory address register 1BE Memory address register 1BH Memory address register 1BL I/O address register 1B DTCR1A MAR1BR MAR1BE MAR1BH MAR1BL IOAR1B
Execute transfer count register 1BH ETCR1BH Execute transfer count register 1BL ETCR1BL Data transfer control register 1B DTCR1B
The lower 20 bits of the address are indicated.
7.2
Register Descriptions (1) (Short Address Mode)
In short address mode, transfers can be carried out independently on channels A and B. Short address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA) as indicated in table 7.4. Table 7.4 Selection of Short and Full Address Modes
Bit 1 DTS1A 1 Description DMAC channel 0 operates as one channel in full address mode DMAC channels 0A and 0B operate as two independent channels in short address mode DMAC channel 1 operates as one channel in full address mode DMAC channels 1A and 1B operate as two independent channels in short address mode
Bit 2 Channel DTS2A 0 1
Other than above 1 1 1
Other than above
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7. DMA Controller
7.2.1
Memory Address Registers (MAR)
A memory address register (MAR) is a 32-bit readable/writable register that specifies a source or destination address. The transfer direction is determined automatically from the activation source. An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits of MARR are reserved; they cannot be modified and are always read as 1.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value 1
1
1
1
1
1
1
1
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Read/Write MARR
MARE
MARH
MARL
Source or destination address
An MAR functions as a source or destination address register depending on how the DMAC is activated: as a destination address register if activation is by a receive-data-full interrupt from the serial communication interface (SCI) (channel 0) or by a conversion-end interrupt from the A/D converter, and as a source address register otherwise. The MAR value is incremented or decremented each time one byte or word is transferred, automatically updating the source or destination memory address. For details, see section 7.3.4, Data Transfer Control Registers (DTCR). The MARs are not initialized by a reset or in standby mode. 7.2.2 I/O Address Registers (IOAR)
An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits are all 1 (H'FFFF).
Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0
Undetermined R/W R/W R/W R/W R/W
Source or destination address
An IOAR functions as a source or destination address register depending on how the DMAC is activated: as a source address register if activation is by a receive-data-full interrupt from the SCI
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7. DMA Controller
(channel 0) or by a conversion-end interrupt from the A/D converter, and as a destination address register otherwise. The IOAR value is held fixed. It is not incremented or decremented when a transfer is executed. The IOARs are not initialized by a reset or in standby mode. 7.2.3 Execute Transfer Count Registers (ETCR)
An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the number of transfers to be executed. These registers function in one way in I/O mode and idle mode, and another way in repeat mode. I/O mode and idle mode
Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter
In I/O mode and idle mode, ETCR functions as a 16-bit counter. The count is decremented by 1 each time one transfer is executed. The transfer ends when the count reaches H'0000.
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Repeat mode
Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0
Undetermined R/W R/W R/W R/W R/W
ETCRH Transfer counter Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0
Undetermined R/W R/W R/W R/W R/W
ETCRL Initial count
In repeat mode, ETCRH functions as an 8-bit transfer counter and ETCRL holds the initial transfer count. ETCRH is decremented by 1 each time one transfer is executed. When ETCRH reaches H'00, the value in ETCRL is reloaded into ETCRH and the same operation is repeated. The ETCRs are not initialized by a reset or in standby mode.
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7.2.4
Data Transfer Control Registers (DTCR)
A data transfer control register (DTCR) is an 8-bit readable/writable register that controls the operation of one DMAC channel.
Bit Initial value Read/Write 7 DTE 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W 2 DTS2 0 R/W 1 DTS1 0 R/W 0 DTS0 0 R/W
Data transfer enable Enables or disables data transfer Data transfer size Selects byte or word size Data transfer increment/decrement Selects whether to increment or decrement the memory address register Repeat enable Selects repeat mode
Data transfer select These bits select the data transfer activation source Data transfer interrupt enable Enables or disables the CPU interrupt at the end of the transfer
The DTCRs are initialized to H'00 by a reset and in standby mode. Bit 7Data Transfer Enable (DTE): Enables or disables data transfer on a channel. When the DTE bit is set to 1, the channel waits for a transfer to be requested, and executes the transfer when activated as specified by bits DTS2 to DTS0. When DTE is 0, the channel is disabled and does not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then writing 1.
Bit 7 DTE 0 1 Description Data transfer is disabled. In I/O mode or idle mode, DTE is cleared to 0 when the specified number of transfers have been completed Data transfer is enabled (Initial value)
If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0.
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Bit 6Data Transfer Size (DTSZ): Selects the data size of each transfer.
Bit 6 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value)
Bit 5Data Transfer Increment/Decrement (DTID): Selects whether to increment or decrement the memory address register (MAR) after a data transfer in I/O mode or repeat mode.
Bit 5 DTID 0 Description MAR is incremented after each data transfer * * 1 * * If DTSZ = 0, MAR is incremented by 1 after each transfer If DTSZ = 1, MAR is incremented by 2 after each transfer If DTSZ = 0, MAR is decremented by 1 after each transfer If DTSZ = 1, MAR is decremented by 2 after each transfer
MAR is decremented after each data transfer
MAR is not incremented or decremented in idle mode. Bit 4Repeat Enable (RPE): Selects whether to transfer data in I/O mode, idle mode, or repeat mode.
Bit 4 RPE 0 Bit 3 DTIE 0 1 1 0 1 Repeat mode Idle mode Description I/O mode (Initial value)
Operations in these modes are described in sections 7.4.2, I/O Mode, 7.4.3, Idle Mode, and 7.4.4, Repeat Mode.
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Bit 3Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0.
Bit 3 DTIE 0 1 Description The DEND interrupt requested by DTE is disabled The DEND interrupt requested by DTE is enabled (Initial value)
Bits 2 to 0Data Transfer Select (DTS2 to DTS0): These bits select the data transfer activation source. Some of the selectable sources differ between channels A and B.* Note: * See section 7.3.4, Data Transfer Control Registers (DTCR).
Bit 2 DTS2 0 Bit 1 DTS1 0 Bit 0 DTS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Compare match/input capture A interrupt from 16-bit timer channel 0 (Initial value) Compare match/input capture A interrupt from 16-bit timer channel 1 Compare match/input capture A interrupt from 16-bit timer channel 2 Conversion-end interrupt from A/D converter Transmit-data-empty interrupt from SCI channel 0 Receive-data-full interrupt from SCI channel 0 Falling edge of DREQ input (channel B) Transfer in full address mode (channel A) Low level of DREQ input (channel B) Transfer in full address mode (channel A)
The same internal interrupt can be selected as an activation source for two or more channels at once. In that case the channels are activated in a priority order, highest-priority channel first. For the priority order, see section 7.4.9, Multiple-Channel Operation. When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a CPU interrupt.
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7.3
Register Descriptions (2) (Full Address Mode)
In full address mode the A and B channels operate together. Full address mode is selected as indicated in table 7.4. 7.3.1 Memory Address Registers (MAR)
A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the source address register of the transfer, and MARB as the destination address register. An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits of MARR are reserved; they cannot be modified and are always read as 1. (Write is invalid.)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value 1
1
1
1
1
1
1
1
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Read/Write MARR
MARE
MARH
MARL
Source or destination address
The MAR value is incremented or decremented each time one byte or word is transferred, automatically updating the source or destination memory address. For details, see section 7.3.4, Data Transfer Control Registers (DTCR). The MARs are not initialized by a reset or in standby mode. 7.3.2 I/O Address Registers (IOAR)
The I/O address registers (IOARs) are not used in full address mode.
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7.3.3
Execute Transfer Count Registers (ETCR)
An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the number of transfers to be executed. The functions of these registers differ between normal mode and block transfer mode. Normal mode * ETCRA
Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter
* ETCRB: Is not used in normal mode. In normal mode ETCRA functions as a 16-bit transfer counter. The count is decremented by 1 each time one transfer is executed. The transfer ends when the count reaches H'0000. ETCRB is not used. Block transfer mode * ETCRA
Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0
Undetermined R/W R/W R/W R/W R/W
ETCRAH Block size counter Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0
Undetermined R/W R/W R/W R/W R/W
ETCRAL Initial block size
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* ETCRB
Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Block transfer counter
In block transfer mode, ETCRAH functions as an 8-bit block size counter. ETCRAL holds the initial block size. ETCRAH is decremented by 1 each time one byte or word is transferred. When the count reaches H'00, ETCRAH is reloaded from ETCRAL. Blocks consisting of an arbitrary number of bytes or words can be transferred repeatedly by setting the same initial block size value in ETCRAH and ETCRAL. In block transfer mode ETCRB functions as a 16-bit block transfer counter. ETCRB is decremented by 1 each time one block is transferred. The transfer ends when the count reaches H'0000. The ETCRs are not initialized by a reset or in standby mode.
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7.3.4
Data Transfer Control Registers (DTCR)
The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address mode. DTCRA
Bit Initial value Read/Write 7 DTE 0 R/W 6 DTSZ 0 R/W 5 SAID 0 R/W 4 SAIDE 0 R/W 3 DTIE 0 R/W 2 DTS2A 0 R/W 1 DTS1A 0 R/W 0 DTS0A 0 R/W
Data transfer enable Enables or disables data transfer Data transfer size Selects byte or word size
Data transfer interrupt enable Enables or disables the CPU interrupt at the end of the transfer
Data transfer select 0A Selects block transfer mode
Source address increment/decrement Source address increment/ decrement enable These bits select whether the source address register (MARA) is incremented, decremented, or held fixed during the data transfer
Data transfer select 2A and 1A These bits must both be set to 1
DTCRA is initialized to H'00 by a reset and in standby mode.
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Bit 7Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, this bit enables or disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the channel is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the channel waits for transfers to be requested. When the specified number of transfers have been completed, the DTE bit is automatically cleared to 0. When DTE is 0, the channel is disabled and does not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then writing 1.
Bit 7 DTE 0 1 Description Data transfer is disabled (DTE is cleared to 0 when the specified number (Initial value) of transfers have been completed) Data transfer is enabled
If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0. Bit 6Data Transfer Size (DTSZ): Selects the data size of each transfer.
Bit 6 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value)
Bit 5Source Address Increment/Decrement (SAID) and, Bit 4Source Address Increment/Decrement Enable (SAIDE): These bits select whether the source address register (MARA) is incremented, decremented, or held fixed during the data transfer.
Bit 5 SAID 0 Bit 4 SAIDE 0 1 Description MARA is held fixed MARA is incremented after each data transfer * * 1 0 1 If DTSZ = 0, MARA is incremented by 1 after each transfer If DTSZ = 1, MARA is incremented by 2 after each transfer (Initial value)
MARA is held fixed MARA is decremented after each data transfer * * If DTSZ = 0, MARA is decremented by 1 after each transfer If DTSZ = 1, MARA is decremented by 2 after each transfer
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Bit 3Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0.
Bit 3 DTIE 0 1 Description The DEND interrupt requested by DTE is disabled The DEND interrupt requested by DTE is enabled (Initial value)
Bits 2 and 1Data Transfer Select 2A and 1A (DTS2A, DTS1A): A channel operates in full address mode when DTS2A and DTS1A are both set to 1. Bit 0Data Transfer Select 0A (DTS0A): Selects normal mode or block transfer mode.
Bit 0 DTS0A 0 1 Description Normal mode Block transfer mode (Initial value)
Operations in these modes are described in sections 7.4.5, Normal Mode, and 7.4.6, Block Transfer Mode.
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DTCRB
Bit Initial value Read/Write 7 DTME 0 R/W 6 0 R/W 5 DAID 0 R/W 4 DAIDE 0 R/W 3 TMS 0 R/W 2 DTS2B 0 R/W 1 DTS1B 0 R/W 0 DTS0B 0 R/W
Data transfer master enable Enables or disables data transfer, together with the DTE bit, and is cleared to 0 by an interrupt Reserved bit
Transfer mode select Selects whether the block area is the source or destination in block transfer mode Data transfer select 2B to 0B These bits select the data transfer activation source
Destination address increment/decrement Destination address increment/decrement enable These bits select whether the destination address register (MARB) is incremented, decremented, or held fixed during the data transfer
DTCRB is initialized to H'00 by a reset and in standby mode. Bit 7Data Transfer Master Enable (DTME): Together with the DTE bit in DTCRA, this bit enables or disables data transfer. When the DTME and DTE bits are both set to 1, the channel is enabled. When an NMI interrupt occurs DTME is cleared to 0, suspending the transfer so that the CPU can use the bus. The suspended transfer resumes when DTME is set to 1 again. For further information on operation in block transfer mode, see section 7.6.6, NMI Interrupts and Block Transfer Mode. DTME is set to 1 by reading the register while DTME = 0, then writing 1.
Bit 7 DTME 0 1 Description Data transfer is disabled (DTME is cleared to 0 when an NMI interrupt occurs) Data transfer is enabled (Initial value)
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Bit 6Reserved: Although reserved, this bit can be written and read. Bit 5Destination Address Increment/Decrement (DAID) and, Bit 4Destination Address Increment/Decrement Enable (DAIDE): These bits select whether the destination address register (MARB) is incremented, decremented, or held fixed during the data transfer.
Bit 5 DAID 0 Bit 4 DAIDE 0 1 Description MARB is held fixed MARB is incremented after each data transfer * * 1 0 1 If DTSZ = 0, MARB is incremented by 1 after each data transfer If DTSZ = 1, MARB is incremented by 2 after each data transfer (Initial value)
MARB is held fixed MARB is decremented after each data transfer * * If DTSZ = 0, MARB is decremented by 1 after each data transfer If DTSZ = 1, MARB is decremented by 2 after each data transfer
Bit 3Transfer Mode Select (TMS): Selects whether the source or destination is the block area in block transfer mode.
Bit 3 TMS 0 1 Description Destination is the block area in block transfer mode Source is the block area in block transfer mode (Initial value)
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Bits 2 to 0Data Transfer Select 2B to 0B (DTS2B, DTS1B, DTS0B): These bits select the data transfer activation source. The selectable activation sources differ between normal mode and block transfer mode. Normal mode
Bit 2 DTS2B 0 Bit 1 DTS1B 0 Bit 0 DTS0B 0 1 1 0 1 1 0 0 1 1 0 1 Description Auto-request (burst mode) Cannot be used Auto-request (cycle-steal mode) Cannot be used Cannot be used Cannot be used Falling edge of DREQ Low level input at DREQ (Initial value)
Block transfer mode
Bit 2 DTS2B 0 Bit 1 DTS1B 0 Bit 0 DTS0B 0 1 1 0 1 1 0 0 1 1 0 1 Description Compare match/input capture A interrupt from 16-bit timer channel 0 (Initial value) Compare match/input capture A interrupt from 16-bit timer channel 1 Compare match/input capture A interrupt from 16-bit timer channel 2 Conversion-end interrupt from A/D converter Cannot be used Cannot be used Falling edge of DREQ Cannot be used
The same internal interrupt can be selected to activate two or more channels. The channels are activated in a priority order, highest priority first. For the priority order, see section 7.4.9, Multiple-Channel Operation.
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7.4
7.4.1
Operation
Overview
Table 7.5 summarizes the DMAC modes. Table 7.5 DMAC Modes
Activation I/O mode Idle mode Repeat mode Compare match/input capture A interrupt from 16-bit timer channels 0 to 2 Transmit-data-empty and receive-data-full interrupts from SCI channel 0 Conversion-end interrupt from A/D converter External request Full address mode Normal mode Auto-request External request Block transfer mode Compare match/input capture A interrupt from ITU channels 0 to 2 Conversion-end interrupt from A/D converter External request * * A and B channels are paired; up to two channels are available Burst mode transfer or cycle-steal mode transfer can be selected for autorequests. Notes * Up to four channels can operate independently Only the B channels support external requests
Transfer Mode Short address mode
*
A summary of operations in these modes follows. I/O Mode: One byte or word is transferred per request. A designated number of these transfers are executed. A CPU interrupt can be requested at completion of the designated number of transfers. One 24-bit address and one 8-bit address are specified. The transfer direction is determined automatically from the activation source. Idle Mode: One byte or word is transferred per request. A designated number of these transfers are executed. A CPU interrupt can be requested at completion of the designated number of transfers. One 24-bit address and one 8-bit address are specified. The addresses are held fixed. The transfer direction is determined automatically from the activation source.
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Repeat Mode: One byte or word is transferred per request. A designated number of these transfers are executed. When the designated number of transfers are completed, the initial address and counter value are restored and operation continues. No CPU interrupt is requested. One 24-bit address and one 8-bit address are specified. The transfer direction is determined automatically from the activation source. Normal Mode * Auto-request The DMAC is activated by register setup alone, and continues executing transfers until the designated number of transfers have been completed. A CPU interrupt can be requested at completion of the transfers. Both addresses are 24-bit addresses. Cycle-steal mode The bus is released to another bus master after each byte or word is transferred. Burst mode Unless requested by a higher-priority bus master, the bus is not released until the designated number of transfers have been completed. * External request One byte or word is transferred per request. A designated number of these transfers are executed. A CPU interrupt can be requested at completion of the designated number of transfers. Both addresses are 24-bit addresses. Block Transfer Mode: One block of a specified size is transferred per request. A designated number of block transfers are executed. At the end of each block transfer, one address is restored to its initial value. When the designated number of blocks have been transferred, a CPU interrupt can be requested. Both addresses are 24-bit addresses.
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7.4.2
I/O Mode
I/O mode can be selected independently for each channel. One byte or word is transferred at each transfer request in I/O mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR). The direction of transfer is determined automatically from the activation source. The transfer is from the address specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-data-full interrupt or an A/D converter conversion end interrupt, and from the address specified in MAR to the address specified in IOAR otherwise. Table 7.6 indicates the register functions in I/O mode. Table 7.6 Register Functions in I/O Mode
Function Activated by SCI0 ReceiveData-Full Interrupt or A/D Converter Conversion Other End Interrupt Activation
0 MAR
Register
23
Initial Setting
Operation
Destination address register Source address register Transfer counter
Source address register Destination address register
Destination or Incremented or source address decremented once per transfer Source or destination address Number of transfers Held fixed
23 All 1s 15
7 IOAR
0
0 ETCR
Decremented once per transfer until H'0000 is reached and transfer ends
Legend: MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address, which is incremented or decremented as each byte or word is transferred.
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IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not incremented or decremented. Figure 7.2 illustrates how I/O mode operates.
Address T
Transfer
IOAR
1 byte or word is transferred per request
Address B
Legend: L = initial setting of MAR N = initial setting of ETCR Address T = L Address B = L + (-1) DTID * (2DTSZ * N - 1)
Figure 7.2 Operation in I/O Mode The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared and the transfer ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer count is 65,536, obtained by setting ETCR to H'0000.
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Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0, conversion-end interrupts from the A/D converter, and external request signals. For the detailed settings see section 7.2.4, Data Transfer Control Registers (DTCR). Figure 7.3 shows a sample setup procedure for I/O mode.
I/O mode setup 1. Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. 2. Set the transfer count in ETCR. 3. Read DTCR while the DTE bit is cleared to 0. 4. Set the DTCR bits as follows. * Select the DMAC activation source with bits DTS2 to DTS0. * Set or clear the DTIE bit to enable or disable the CPU interrupt at the end of the transfer. * Clear the RPE bit to 0 to select I/O mode. * Select MAR increment or decrement with the DTID bit. * Select byte size or word size with the DTSZ bit. * Set the DTE bit to 1 to enable the transfer.
Set source and destination addresses
1
Set transfer count
2
Read DTCR
3
Set DTCR
4
I/O mode
Figure 7.3 I/O Mode Setup Procedure (Example) 7.4.3 Idle Mode
Idle mode can be selected independently for each channel. One byte or word is transferred at each transfer request in idle mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR). The direction of transfer is determined automatically from the activation source. The transfer is from the address specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-data-full interrupt or an A/D converter conversion end interrupt, and from the address specified in MAR to the address specified in IOAR otherwise.
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Table 7.7 indicates the register functions in idle mode. Table 7.7 Register Functions in Idle Mode
Function Activated by SCI0 ReceiveData-Full Interrupt or A/D Converter Conversion Other End Interrupt Activation
0 MAR 23 All 1s 15 ETCR 7 IOAR 0 0
Register
23
Initial Setting
Operation
Destination address register Source address register Transfer counter
Source address register Destination address register
Destination or Held fixed source address Source or destination address Number of transfers Held fixed
Decremented once per transfer until H'0000 is reached and transfer ends
Legend: MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. MAR and IOAR are not incremented or decremented. Figure 7.4 illustrates how idle mode operates.
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MAR
Transfer
IOAR
1 byte or word is transferred per request
Figure 7.4 Operation in Idle Mode The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared, the transfer ends, and a CPU interrupt is requested. The maximum transfer count is 65,536, obtained by setting ETCR to H'0000. Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0, conversion-end interrupts from the A/D converter, and external request signals. For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR). Figure 7.5 shows a sample setup procedure for idle mode.
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Idle mode setup
Set source and destination addresses
1
Set transfer count
2
1. Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. 2. Set the transfer count in ETCR. 3. Read DTCR while the DTE bit is cleared to 0. 4. Set the DTCR bits as follows. * Select the DMAC activation source with bits DTS2 to DTS0. * Set the DTIE and RPE bits to 1 to select idle mode. * Select byte size or word size with the DTSZ bit. * Set the DTE bit to 1 to enable the transfer.
Read DTCR
3
Set DTCR
4
Idle mode
Figure 7.5 Idle Mode Setup Procedure (Example) 7.4.4 Repeat Mode
Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable timing pattern controller (TPC) in synchronization, for example, with 16-bit timer compare match. Repeat mode can be selected for each channel independently. One byte or word is transferred per request in repeat mode, as in I/O mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR). At the end of the designated number of transfers, MAR and ETCRH are restored to their original values and operation continues. The direction of transfer is determined automatically from the activation source. The transfer is from the address specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-datafull interrupt or an A/D converter conversion end interrupt, and from the address specified in MAR to the address specified in IOAR otherwise. Table 7.8 indicates the register functions in repeat mode.
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Table 7.8
Register Functions in Repeat Mode
Function Activated by SCI0 ReceiveData-Full Interrupt or A/D Converter Conversion Other End Interrupt Activation
0 MAR
Register
23
Initial Setting Transfer destination or transfer source start address
Operation Incremented or decremented at each transfer until ETCRH reaches H'0000, then restored to initial value Held fixed
Destination address register
Source address register
23 All 1s
7 IOAR
0
Source address register Transfer counter
Destination address register
Source or destination address Number of transfers
7
0
ETCRH
7
0
ETCRL
Decremented once per transfer until H'0000 is reached, then reloaded from ETCRL Held fixed
Initial transfer count Legend: MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register
Number of transfers
In repeat mode ETCRH is used as the transfer counter while ETCRL holds the initial transfer count. ETCRH is decremented by 1 at each transfer until it reaches H'00, then is reloaded from ETCRL. MAR is also restored to its initial value, which is calculated from the DTSZ and DTID bits in DTCR. Specifically, MAR is restored as follows: MAR MAR - (-1)
DTID
*2
DTSZ
* ETCRL
ETCRH and ETCRL should be initially set to the same value.
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In repeat mode transfers continue until the CPU clears the DTE bit to 0. After DTE is cleared to 0, if the CPU sets DTE to 1 again, transfers resume from the state at which DTE was cleared. No CPU interrupt is requested. As in I/O mode, MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not incremented or decremented. Figure 7.6 illustrates how repeat mode operates.
Address T
Transfer
IOAR
1 byte or word is transferred per request
Address B
Legend: L = initial setting of MAR N = initial setting of ETCRH and ETCRL Address T = L Address B = L + (-1) DTID * (2DTSZ * N - 1)
Figure 7.6 Operation in Repeat Mode The transfer count is specified as an 8-bit value in ETCRH and ETCRL. The maximum transfer count is 255, obtained by setting both ETCRH and ETCRL to H'FF. Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0, conversion-end interrupts from the A/D converter, and external request signals.
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For the detailed settings see section 7.2.4, Data Transfer Control Registers (DTCR). Figure 7.7 shows a sample setup procedure for repeat mode.
Repeat mode 1. Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. 2. Set the transfer count in both ETCRH and ETCRL. 3. Read DTCR while the DTE bit is cleared to 0. 4. Set the DTCR bits as follows. * Select the DMAC activation source with bits DTS2 to DTS0. * Clear the DTIE bit to 0 and set the RPE bit to 1 to select repeat mode. * Select MAR increment or decrement with the DTID bit. * Select byte size or word size with the DTSZ bit. * Set the DTE bit to 1 to enable the transfer.
Set source and destination addresses
1
Set transfer count
2
Read DTCR
3
Set DTCR
4
Repeat mode
Figure 7.7 Repeat Mode Setup Procedure (Example)
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7.4.5
Normal Mode
In normal mode, the A and B channels are combined. One byte or word is transferred per request. A designated number of these transfers are executed. Addresses are specified in MARA and MARB. Table 7.9 indicates the register functions in I/O mode. Table 7.9
Register
23 MARA 23 MARB 15 ETCRA
Register Functions in Normal Mode
Function
0 Source address register 0 Destination address register 0 Transfer counter
Initial Setting Transfer source start address
Operation Incremented or decremented once per transfer, or held fixed
Transfer destination Incremented or start address decremented once per transfer, or held fixed Number of transfers Decremented once per transfer
Legend: MARA: Memory address register A MARB: Memory address register B ETCRA: Execute transfer count register A
The source and destination addresses are both 24-bit addresses. MARA specifies the source address. MARB specifies the destination address. MARA and MARB can be independently incremented, decremented, or held fixed as data is transferred. The transfer count is specified as a 16-bit value in ETCRA. The ETCRA value is decremented by 1 at each transfer. When the ETCRA value reaches H'0000, the DTE bit is cleared and the transfer ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer count is 65,536, obtained by setting ETCRA to H'0000.
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Figure 7.8 illustrates how normal mode operates.
Address T A
Transfer
Address T B
Address BA
Address B B
Legend: L A = initial setting of MARA L B = initial setting of MARB N = initial setting of ETCRA TA = LA BA = L A + SAIDE * (-1)SAID * (2 DTSZ * N - 1) TB = LB BB = L B + DAIDE * (-1)DAID * (2 DTSZ * N - 1)
Figure 7.8 Operation in Normal Mode Transfers can be requested (activated) by an external request or auto-request. An auto-requested transfer is activated by the register settings alone. The designated number of transfers are executed automatically. Either cycle-steal or burst mode can be selected. In cycle-steal mode, the DMAC releases the bus temporarily after each transfer. In burst mode, the DMAC keeps the bus until the transfers are completed, unless there is a bus request from a higher-priority bus master. For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR).
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Figure 7.9 shows a sample setup procedure for normal mode.
Normal mode
Set initial source address
1
1. 2. 3. 4.
Set initial destination address
2 5.
Set transfer count
3
Set DTCRB (1)
4
Set DTCRA (1)
5
Read DTCRB
6
6. 7. 8. 9.
Set the initial source address in MARA. Set the initial destination address in MARB. Set the transfer count in ETCRA. Set the DTCRB bits as follows. * Clear the DTME bit to 0. * Set the DAID and DAIDE bits to select whether MARB is incremented, decremented, or held fixed. * Select the DMAC activation source with bits DTS2B to DTS0B. Set the DTCRA bits as follows. * Clear the DTE bit to 0. * Select byte or word size with the DTSZ bit. * Set the SAID and SAIDE bits to select whether MARA is incremented, decremented, or held fixed. * Set or clear the DTIE bit to enable or disable the CPU interrupt at the end of the transfer. * Clear the DTS0A bit to 0 and set the DTS2A and DTS1A bits to 1 to select normal mode. Read DTCRB with DTME cleared to 0. Set the DTME bit to 1 in DTCRB. Read DTCRA with DTE cleared to 0. Set the DTE bit to 1 in DTCRA to enable the transfer.
Set DTCRB (2)
7
Read DTCRA
8
Set DTCRA (2)
9
Normal mode Note: Carry out settings 1 to 9 with the DEND interrupt masked in the CPU. If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in which case the transfer will not start.
Figure 7.9 Normal Mode Setup Procedure (Example)
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7.4.6
Block Transfer Mode
In block transfer mode, the A and B channels are combined. One block of a specified size is transferred per request. A designated number of block transfers are executed. Addresses are specified in MARA and MARB. The block area address can be either held fixed or cycled. Table 7.10 indicates the register functions in block transfer mode. Table 7.10 Register Functions in Block Transfer Mode
Register 23 MARA 23 MARB 7 0 0 0 Function Source address register Destination address register Block size counter Initial Setting Transfer source start address Operation Incremented or decremented once per transfer, or held fixed
Transfer destination Incremented or start address decremented once per transfer, or held fixed Block size Decremented once per transfer until H'00 is reached, then reloaded from ETCRL Held fixed
ETCRAH
7
0
Initial block size
Block size
ETCRAL 15 ETCRB Legend: MARA: MARB: ETCRA: ETCRB: 0 Block transfer counter Number of block transfers Decremented once per block transfer until H'0000 is reached and the transfer ends
Memory address register A Memory address register B Execute transfer count register A Execute transfer count register B
The source and destination addresses are both 24-bit addresses. MARA specifies the source address. MARB specifies the destination address. MARA and MARB can be independently incremented, decremented, or held fixed as data is transferred. One of these registers operates as a block area register: even if it is incremented or decremented, it is restored to its initial value at the end of each block transfer. The TMS bit in DTCRB selects whether the block area is the source or destination.
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If M (1 to 255) is the size of the block transferred at each request and N (1 to 65,536) is the number of blocks to be transferred, then ETCRAH and ETCRAL should initially be set to M and ETCRB should initially be set to N. Figure 7.10 illustrates how block transfer mode operates. In this figure, bit TMS is cleared to 0, meaning the block area is the destination.
TA Transfer Block 1 Block area BA
Address T B
Address B B
Block 2 M bytes or words are transferred per request
Block N
Legend: L A = initial setting of MARA L B = initial setting of MARB M = initial setting of ETCRAH and ETCRAL N = initial setting of ETCRB T A = LA B A = L A + SAIDE * (-1)SAID * (2 DTSZ * M - 1) T B = LB B B = L B + DAIDE * (-1)DAID * (2 DTSZ * M - 1)
Figure 7.10 Operation in Block Transfer Mode
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When activated by a transfer request, the DMAC executes a burst transfer. During the transfer MARA and MARB are updated according to the DTCR settings, and ETCRAH is decremented. When ETCRAH reaches H'00, it is reloaded from ETCRAL to restore the initial value. The memory address register of the block area is also restored to its initial value, and ETCRB is decremented. If ETCRB is not H'0000, the DMAC then waits for the next transfer request. ETCRAH and ETCRAL should be initially set to the same value. The above operation is repeated until ETCRB reaches H'0000, at which point the DTE bit is cleared to 0 and the transfer ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. Figure 7.11 shows examples of a block transfer with byte data size when the block area is the destination. In (a), the block area address is cycled. In (b), the block area address is held fixed. Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, by a conversion-end interrupt from the A/D converter, and by external request signals. For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR).
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Start (DTE = DTME = 1) Start (DTE = DTME = 1)
Transfer requested? Yes Get bus
No
Transfer requested? Yes Get bus
No
Read from MARA address MARA = MARA + 1 Write to MARB address MARB = MARB + 1 ETCRAH = ETCRAH - 1 No ETCRAH = H'00 Yes Release bus ETCRAH = ETCRAL MARB = MARB EETCRAL ETCRB = ETCRB - 1 No
Read from MARA address MARA = MARA + 1 Write to MARB address
ETCRAH = ETCRAH - 1 No ETCRAH = H'00 Yes Release bus ETCRAH = ETCRAL ETCRB = ETCRB - 1 No
ETCRB = H'0000 Yes Clear DTE to 0 and end transfer
ETCRB = H'0000 Yes Clear DTE to 0 and end transfer
a. DTSZ = TMS = 0 SAID = DAID = 0 SAIDE = DAIDE = 1
b. DTSZ = TMS = 0 SAID = 0 SAIDE = 1 DAIDE = 0
Figure 7.11 Block Transfer Mode Flowcharts
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Figure 7.12 shows a sample setup procedure for block transfer mode.
Block transfer mode
Set source address
1
Set destination address
2
Set block transfer count
3
Set block size
4
Set DTCRB (1)
5
Set DTCRA (1)
6
Read DTCRB
7
Set the source address in MARA. Set the destination address in MARB. Set the block transfer count in ETCRB. Set the block size (number of bytes or words) in both ETCRAH and ETCRAL. 5. Set the DTCRB bits as follows. * Clear the DTME bit to 0. * Set the DAID and DAIDE bits to select whether MARB is incremented, decremented, or held fixed. * Set or clear the TMS bit to make the block area the source or destination. * Select the DMAC activation source with bits DTS2B to DTS0B. 6. Set the DTCRA bits as follows. * Clear the DTE to 0. * Select byte size or word size with the DTSZ bit. * Set the SAID and SAIDE bits to select whether MARA is incremented, decremented, or held fixed. * Set or clear the DTIE bit to enable or disable the CPU interrupt at the end of the transfer. * Set bits DTS2A to DTS0A all to 1 to select block transfer mode. 7. Read DTCRB with DTME cleared to 0. 8. Set the DTME bit to 1 in DTCRB. 9. Read DTCRA with DTE cleared to 0. 10. Set the DTE bit to 1 in DTCRA to enable the transfer. 1. 2. 3. 4.
Set DTCRB (2)
8
Read DTCRA
9
Set DTCRA (2)
10
Block transfer mode Note: Carry out settings 1 to 10 with the DEND interrupt masked in the CPU. If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in which case the transfer will not start.
Figure 7.12 Block Transfer Mode Setup Procedure (Example)
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7.4.7
DMAC Activation
The DMAC can be activated by an internal interrupt, external request, or auto-request. The available activation sources differ depending on the transfer mode and channel as indicated in table 7.11. Table 7.11 DMAC Activation Sources
Short Address Mode Channels Activation Source Internal interrupts IMIA0 IMIA1 IMIA2 ADI TXI0 RXI0 External requests Falling edge of DREQ Low input at DREQ Auto-request 0A and 1A Yes Yes Yes Yes Yes Yes No No No Channels 0B and 1B Yes Yes Yes Yes Yes Yes Yes Yes No Full Address Mode Normal No No No No No No Yes Yes Yes Block Yes Yes Yes Yes No No Yes No No
Activation by Internal Interrupts: When an interrupt request is selected as a DMAC activation source and the DTE bit is set to 1, that interrupt request is not sent to the CPU. It is not possible for an interrupt request to activate the DMAC and simultaneously generate a CPU interrupt. When the DMAC is activated by an interrupt request, the interrupt request flag is cleared automatically. If the same interrupt is selected to activate two or more channels, the interrupt request flag is cleared when the highest-priority channel is activated, but the transfer request is held pending on the other channels in the DMAC, which are activated in their priority order. Activation by External Request: If an external request (DREQ pin) is selected as an activation source, the DREQ pin becomes an input pin and the corresponding TEND pin becomes an output pin, regardless of the port data direction register (DDR) settings. The DREQ input can be levelsensitive or edge-sensitive.
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In short address mode and normal mode, an external request operates as follows. If edge sensing is selected, one byte or word is transferred each time a high-to-low transition of the DREQ input is detected. If the next edge is input before the transfer is completed, the next transfer may not be executed. If level sensing is selected, the transfer continues while DREQ is low, until the transfer is completed. The bus is released temporarily after each byte or word has been transferred, however. If the DREQ input goes high during a transfer, the transfer is suspended after the current byte or word has been transferred. When DREQ goes low, the request is held internally until one byte or word has been transferred. The TEND signal goes low during the last write cycle. In block transfer mode, an external request operates as follows. Only edge-sensitive transfer requests are possible in block transfer mode. Each time a high-to-low transition of the DREQ input is detected, a block of the specified size is transferred. The TEND signal goes low during the last write cycle in each block. Activation by Auto-Request: The transfer starts as soon as enabled by register setup, and continues until completed. Cycle-steal mode or burst mode can be selected. In cycle-steal mode, the DMAC releases the bus temporarily after transferring each byte or word. Normally, DMAC cycles alternate with CPU cycles. In burst mode, the DMAC keeps the bus until the transfer is completed, unless there is a higherpriority bus request. If there is a higher-priority bus request, the bus is released after the current byte or word has been transferred. 7.4.8 DMAC Bus Cycle
Figure 7.13 shows an example of the timing of the basic DMAC bus cycle. This example shows a word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the DMAC gets the bus from the CPU, after one dead cycle (Td), it reads from the source address and writes to the destination address. During these read and write operations the bus is not released even if there is another bus request. DMAC cycles comply with bus controller settings in the same way as CPU cycles.
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CPU cycle T1 Source address Address bus RD Destination address T2 T1 T2 Td T1 DMAC cycle (1 word transfer) T2 T1 T2 T3 T1 T2 T3 T1 CPU cycle T2 T1 T2
HWR
LWR
Figure 7.13 DMA Transfer Bus Timing (Example) Figure 7.14 shows the timing when the DMAC is activated by low input at a DREQ pin. This example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state access area. The DMAC continues the transfer while the DREQ pin is held low.
DMAC cycle (last transfer cycle) Td T1 T2 T1 T2
CPU cycle T1 T2 T3 Td
DMAC cycle T1 T2 T1 T2
CPU cycle T1 T2
CPU cycle T1 T2
DREQ Address bus RD
Source Destination address address
Source Destination address address
HWR , LWR
TEND
Figure 7.14 Bus Timing of DMA Transfer Requested by Low DREQ Input
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Figure 7.15 shows an auto-requested burst-mode transfer. This example shows a transfer of three words from a 16-bit two-state access area to another 16-bit two-state access area.
CPU cycle T1 Source Destination address address Address bus RD T2 Td T1 T2 T1 T2 DMAC cycle T1 T2 T1 T2 T1 T2 T1 T2 CPU cycle T1 T2
HWR , LWR
Figure 7.15 Burst DMA Bus Timing When the DMAC is activated from a DREQ pin there is a minimum interval of four states from when the transfer is requested until the DMAC starts operating*. The DREQ pin is not sampled during the time between the transfer request and the start of the transfer. In short address mode and normal mode, the pin is next sampled at the end of the read cycle. In block transfer mode, the pin is next sampled at the end of one block transfer. Note: * The minimum response time is also four states when the DMAC is activated by an internal module interrupt.
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Figure 7.16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal mode.
CPU cycle T2 T1 T2
CPU cycle T2 DREQ Address bus RD HWR , LWR Minimum 4 states T1 T2 T1 T2 Td
DMAC cycle T1 T2 T1
DMAC cycle Td T1 T2
Next sampling point
Figure 7.16 Timing of DMAC Activation by Falling Edge of DREQ in Normal Mode
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Figure 7.17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in normal mode.
CPU cycle T2 DREQ Address bus RD HWR , LWR Minimum 4 states Next sampling point T1 T2 T1 T2 Td DMAC cycle T1 T2 T1 T2 T1 CPU cycle T2 T1 T2 T1
Figure 7.17 Timing of DMAC Activation by Low DREQ Level in Normal Mode
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Figure 7.18 shows the timing when the DMAC is activated by the falling edge of DREQ in block transfer mode.
End of 1 block transfer DMAC cycle T1 DREQ Address bus RD HWR , LWR T2 T1 T2 T1 T2 T1 T2 T1 CPU cycle T2 T1 T2 DMAC cycle Td T1 T2
TEND
Next sampling Minimum 4 states
Figure 7.18 Timing of DMAC Activation by Falling Edge of DREQ in Block Transfer Mode
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7.4.9
Multiple-Channel Operation
The DMAC channel priority order is: channel 0 > channel 1 and channel A > channel B. Table 7.12 shows the complete priority order. Table 7.12 Channel Priority Order
Short Address Mode Channel 0A Channel 0B Channel 1A Channel 1B Channel 1 Low Full Address Mode Channel 0 Priority High
If transfers are requested on two or more channels simultaneously, or if a transfer on one channel is requested during a transfer on another channel, the DMAC operates as follows. * When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it starts a transfer on the highest-priority channel at that time. * Once a transfer starts on one channel, requests to other channels are held pending until that channel releases the bus. * After each transfer in short address mode, and each externally-requested or cycle-steal transfer in normal mode, the DMAC releases the bus and returns to step 1. After releasing the bus, if there is a transfer request for another channel, the DMAC requests the bus again. * After completion of a burst-mode transfer, or after transfer of one block in block transfer mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a higher-priority channel or a bus request from a higher-priority bus master, however, the DMAC releases the bus after completing the transfer of the current byte or word. After releasing the bus, if there is a transfer request for another channel, the DMAC requests the bus again. Figure 7.19 shows the timing when channel 0A is set up for I/O mode and channel 1 for burst mode, and a transfer request for channel 0A is received while channel 1 is active.
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DMAC cycle (channel 1) T1 Address bus RD HWR , LWR T2 T1 CPU cycle T2 Td DMAC cycle (channel 0A) T1 T2 T1 T2 T1 CPU cycle T2 Td DMAC cycle (channel 1) T1 T2 T1 T2
Figure 7.19 Timing of Multiple-Channel Operations 7.4.10 External Bus Requests, DRAM Interface, and DMAC
During a DMAC transfer, if the bus right is requested by an external bus request signal (BREQ) or by the DRAM interface (refresh cycle), the DMAC releases the bus after completing the transfer of the current byte or word. If there is a transfer request at this point, the DMAC requests the bus right again. Figure 7.20 shows an example of the timing of insertion of a refresh cycle during a burst transfer on channel 0.
Refresh cycle T2 T1 T2 Td
DMAC cycle (channel 0) T1 Address bus RD HWR T2 T1 T2 T1 T2 T1
DMAC cycle (channel 0) T1 T2 T1 T2 T1 T2
Figure 7.20 Bus Timing of DRAM Interface and DMAC
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7.4.11
NMI Interrupts and DMAC
NMI interrupts do not affect DMAC operations in short address mode. If an NMI interrupt occurs during a transfer in full address mode, the DMAC suspends operations. In full address mode, a channel is enabled when its DTE and DTME bits are both set to 1. NMI input clears the DTME bit to 0. After transferring the current byte or word, the DMAC releases the bus to the CPU. In normal mode, the suspended transfer resumes when the CPU sets the DTME bit to 1 again. Check that the DTE bit is set to 1 and the DTME bit is cleared to 0 before setting the DTME bit to 1. Figure 7.21 shows the procedure for resuming a DMAC transfer in normal mode on channel 0 after the transfer was halted by NMI input.
Resuming DMAC transfer in normal mode
1. Check that DTE = 1 and DTME = 0. 2. Read DTCRB while DTME = 0, then write 1 in the DTME bit. 1
DTE = 1 DTME = 0 Yes Set DTME to 1
No
2
DMA transfer continues
End
Figure 7.21 Procedure for Resuming a DMAC Transfer Halted by NMI (Example) For information about NMI interrupts in block transfer mode, see section 7.6.6, NMI Interrupts and Block Transfer Mode.
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7.4.12
Aborting a DMAC Transfer
When the DTE bit in an active channel is cleared to 0, the DMAC halts after transferring the current byte or word. The DMAC starts again when the DTE bit is set to 1. In full address mode, the DTME bit can be used for the same purpose. Figure 7.22 shows the procedure for aborting a DMAC transfer by software.
DMAC transfer abort
1. Clear the DTE bit to 0 in DTCR. To avoid generating an interrupt when aborting a DMA transfer, clear the DTIE bit to 0 simultaneously. 1
Set DTCR
DMAC transfer aborted
Figure 7.22 Procedure for Aborting a DMAC Transfer
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7.4.13
Exiting Full Address Mode
Figure 7.23 shows the procedure for exiting full address mode and initializing the pair of channels. To set the channels up in another mode after exiting full address mode, follow the setup procedure for the relevant mode.
Exiting full address mode
Halt the channel
1
1. Clear the DTE bit to 0 in DTCRA, or wait for the transfer to end and the DTE bit to be cleared to 0. 2. Clear all DTCRB bits to 0. 3. Clear all DTCRA bits to 0.
Initialize DTCRB
2
Initialize DTCRA
3
Initialized and halted
Figure 7.23 Procedure for Exiting Full Address Mode (Example)
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7.4.14
DMAC States in Reset State, Standby Modes, and Sleep Mode
When the chip is reset or enters hardware standby mode or software standby mode, the DMAC is initialized and halts. DMAC operations continue in sleep mode. Figure 7.24 shows the timing of a cycle-steal transfer in sleep mode.
Sleep mode CPU cycle T2 Address bus RD HWR Td DMAC cycle T1 T2 T1 T2 Td DMAC cycle T1 T2 T1 T2 Td
Figure 7.24 Timing of Cycle-Steal Transfer in Sleep Mode
7.5
Interrupts
The DMAC generates only DMA-end interrupts. Table 7.13 lists the interrupts and their priority. Table 7.13 DMAC Interrupts
Description Interrupt DEND0A DEND0B DEND1A DEND1B Short Address Mode End of transfer on channel 0A End of transfer on channel 0B End of transfer on channel 1A End of transfer on channel 1B Full Address Mode End of transfer on channel 0 End of transfer on channel 1 Low Interrupt Priority High
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Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control register (DTCR). Separate interrupt signals are sent to the interrupt controller. The interrupt priority order among channels is channel 0 > channel 1 and channel A > channel B. Figure 7.25 shows the DMA-end interrupt logic. An interrupt is requested whenever DTE = 0 and DTIE = 1.
DTE DMA-end interrupt DTIE
Figure 7.25 DMA-End Interrupt Logic The DMA-end interrupt for the B channels (DENDB) is unavailable in full address mode. The DTME bit does not affect interrupt operations.
7.6
7.6.1
Usage Notes
Note on Word Data Transfer
Word data cannot be accessed starting at an odd address. When word-size transfer is selected, set even values in the memory and I/O address registers (MAR and IOAR). 7.6.2 DMAC Self-Access
The DMAC itself cannot be accessed during a DMAC cycle. DMAC registers cannot be specified as source or destination addresses.
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7.6.3
Longword Access to Memory Address Registers
A memory address register can be accessed as longword data at the MARR address. Example
MOV.L MOV.L #LBL, ER0 ER0, @MARR
Four byte accesses are performed. Note that the CPU may release the bus between the second byte (MARE) and third byte (MARH). Memory address registers should be written and read only when the DMAC is halted. 7.6.4 Note on Full Address Mode Setup
Full address mode is controlled by two registers: DTCRA and DTCRB. Care must be taken to prevent the B channel from operating in short address mode during the register setup. The enable bits (DTE and DTME) should not be set to 1 until the end of the setup procedure.
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7.6.5
Note on Activating DMAC by Internal Interrupts
When using an internal interrupt to activate the DMAC, make sure that the interrupt selected as the activating source does not occur during the interval after it has been selected but before the DMAC has been enabled. The on-chip supporting module that will generate the interrupt should not be activated until the DMAC has been enabled. If the DMAC must be enabled while the onchip supporting module is active, follow the procedure in figure 7.26.
Enabling of DMAC
Yes Interrupt handling by CPU
Selected interrupt requested? No
1
1. While the DTE bit is cleared to 0, interrupt requests are sent to the CPU. 2. Clear the interrupt enable bit to 0 in the interrupt-generating on-chip supporting module. 3. Enable the DMAC. 4. Enable the DMAC-activating interrupt.
Clear selected interrupt's enable bit to 0
2
Enable DMAC
3
Set selected interrupt's enable bit to 1
4
DMAC operates
Figure 7.26 Procedure for Enabling DMAC while On-Chip Supporting Module Is Operating (Example) If the DTE bit is set to 1 but the DTME bit is cleared to 0, the DMAC is halted and the selected activating source cannot generate a CPU interrupt. If the DMAC is halted by an NMI interrupt, for example, the selected activating source cannot generate CPU interrupts. To terminate DMAC operations in this state, clear the DTE bit to 0 to allow CPU interrupts to be requested. To continue DMAC operations, carry out steps 2 and 4 in figure 7.26 before and after setting the DTME bit to 1.
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7. DMA Controller
When an ITU interrupt activates the DMAC, make sure the next interrupt does not occur before the DMA transfer ends. If one 16-bit timer interrupt activates two or more channels, make sure the next interrupt does not occur before the DMA transfers end on all the activated channels. If the next interrupt occurs before a transfer ends, the channel or channels for which that interrupt was selected may fail to accept further activation requests. 7.6.6 NMI Interrupts and Block Transfer Mode
If an NMI interrupt occurs in block transfer mode, the DMAC operates as follows. * When the NMI interrupt occurs, the DMAC finishes transferring the current byte or word, then clears the DTME bit to 0 and halts. The halt may occur in the middle of a block. It is possible to find whether a transfer was halted in the middle of a block by checking the block size counter. If the block size counter does not have its initial value, the transfer was halted in the middle of a block. * If the transfer is halted in the middle of a block, the activating interrupt flag is cleared to 0. The activation request is not held pending. * While the DTE bit is set to 1 and the DTME bit is cleared to 0, the DMAC is halted and does not accept activating interrupt requests. If an activating interrupt occurs in this state, the DMAC does not operate and does not hold the transfer request pending internally. Neither is a CPU interrupt requested. For this reason, before setting the DTME bit to 1, first clear the enable bit of the activating interrupt to 0. Then, after setting the DTME bit to 1, set the interrupt enable bit to 1 again. See section 7.6.5, Note on Activating DMAC by Internal Interrupts. * When the DTME bit is set to 1, the DMAC waits for the next transfer request. If it was halted in the middle of a block transfer, the rest of the block is transferred when the next transfer request occurs. Otherwise, the next block is transferred when the next transfer request occurs. 7.6.7 Memory and I/O Address Register Values
Table 7.14 indicates the address ranges that can be specified in the memory and I/O address registers (MAR and IOAR). Table 7.14 Address Ranges Specifiable in MAR and IOAR
1-Mbyte Mode MAR IOAR H'00000 to H'FFFFF (0 to 1048575) H'FFF00 to H'FFFFF (1048320 to 1048575) 16-Mbyte Mode H'000000 to H'FFFFFF (0 to 16777215) H'FFFF00 to H'FFFFFF (16776960 to 16777215)
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MAR bits 23 to 20 are ignored in 1-Mbyte mode. 7.6.8 Bus Cycle when Transfer Is Aborted
When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead cycle may occur. This dead cycle does not update the halted channel's address register or counter value. Figure 7.27 shows an example in which an auto-requested transfer in cycle-steal mode on channel 0 is aborted by clearing the DTE bit in channel 0.
DMAC cycle Td Td
CPU cycle T1 T2 Td
DMAC cycle T1 T2 T1 T2 T1
CPU cycle T2 T3
CPU cycle T1 T2
Address bus
RD
HWR, LWR DTE bit is cleared
Figure 7.27 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode 7.6.9 Transfer Requests by A/D Converter
When the A/D converter is set to scan mode and conversion is performed on more than one channel, the A/D converter generates a transfer request when all conversions are completed. The converted data is stored in the appropriate ADDR registers. Block transfer mode and full address mode should therefore be used to transfer all the conversion results at one time.
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8. I/O Ports
Section 8 I/O Ports
8.1 Overview
The H8/3006 and H8/3007 have 6 input/output ports (ports 4, 6, 8, 9, A, and B) and one input-only port (port 7). Table 8.1 summarizes the port functions. The pins in each port are multiplexed as shown in table 8.1. Each port has a data direction register (DDR) for selecting input or output, and a data register (DR) for storing output data. In addition to these registers, port 4 has an input pull-up MOS control register (PCR) for switching input pull-up transistors on and off. Ports 4, 6, and 8 can drive one TTL load and a 90-pF capacitive load. Ports 9, A, and B can drive one TTL load and a 30-pF capacitive load. Ports 4, 6 and 8 to B can drive a darlington transistor pair. Pins P82 to P80, PA7 to PA0 have Schmitt-trigger input circuits. For block diagrams of the ports see appendix C, I/O Port Block Diagrams.
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Table 8.1
Port Port 4
Port Functions
Pins P47 to P40/ D7 to D0 Mode 1 Mode 2 Mode 3 Mode 4
Description * 8-bit I/O port * Built-in input pull-up transistors
Data input/output (D7 to D0) and 8-bit generic input/ output 8-bit bus mode: generic input/output 16-bit bus mode: data input/output
Port 6
* 4-bit I/O port
P67/ P62/BACK P61/BREQ P60/WAIT
Clock output () and generic input Bus control signal input/output (BACK, BREQ, WAIT) and 3-bit generic input/output Analog input (AN7, AN6) to A/D converter, analog output (DA1, DA0) from D/A converter, and generic input Analog input (AN5 to AN0) to A/D converter, and generic input DDR = 0: generic input DDR = 1 (reset value): CS0 output IRQ3 input, CS1 output, external trigger input (ADTRG) to A/D converter, and generic input DDR = 0 (reset value): generic input DDR = 1: CS1 output
Port 7
* 8-bit I/O port
P77/AN7/DA1 P76/AN6/DA0 P75 to P70/ AN5 to AN0
Port 8
* 5-bit I/O port
P84/CS0
* P82 to P80 have Schmitt inputs P83/IRQ3/CS1/ ADTRG
P82/IRQ2/CS2 P81/IRQ1/CS3
IRQ2 and IRQ1 input, CS2 and CS3 output, and generic input DDR = 0 (reset value): generic input DDR = 1: CS2 and CS3 output
P80/IRQ0/RFSH Port 9 * 6-bit I/O port P95/IRQ5/SCK1 P94/IRQ4/SCK0 P93/RxD1 P92/RxD0 P91/TxD1 P90/TxD0
IRQ0 input, RFSH output, and generic input/output Input and output (SCK1, SCK0, RxD1, RxD0, TxD1, TxD0) for serial communication interfaces 1 and 0 (SCI1/0), IRQ5 and IRQ4 input, and 6-bit generic input/output
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8. I/O Ports Port Port A Description * 8-bit I/O port * Schmitt inputs Pins Mode 1 Mode 2 Mode 3 Mode 4
Address output (A20) PA7/TP7/TIOCB2/ Output (TP7) from proA20 grammable timing pattern controller (TPC), input or output (TIOCB2) for 16-bit timer and generic input/output PA6/TP6/TIOCA2/ A21 PA5/TP5/TIOCB1/ A22 PA4/TP4/TIOCA1/ A23 PA3/TP3/TIOCB0/ TCLKD PA2/TP2/TIOCA0/ TCLKC PA1/TP1/TCLKB/ TEND1 PA0/TP0/TCLKA/ TEND0 TPC output (TP6 to TP4), 16-bit timer input and output (TIOCA2, TIOCB1, TIOCA1), and generic input/output TPC output (TP6 to TP4), 16-bit timer input and output (TIOCA2, TIOCB1, TIOCA1), address output (A23 to A21), and generic input/output
TPC output (TP3 to TP0), 16-bit timer input and output (TIOCB0, TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA), 8-bit timer input (TCLKD, TCLKC, TCLKB, TCLKA), output (TEND1, TEND0) from DMA controller (DMAC), and generic input/output
Port B
* 8-bit I/O port
PB7/TP15/RXD2 PB6/TP14/TXD2 PB5/TP13/SCK2/ LCAS PB4/TP12/UCAS PB3/TP11/TMIO3/ DREQ1/CS4 PB2/TP10/TMO2/ CS5 PB1/TP9/TMIO1/ DREQ0/CS6 PB0/TP8/TMO0/ CS7
TPC output (TP15 to TP12), SCI2 input and output (SCK2 , RxD2, TxD2), DRAM interface output (LCAS, UCAS), and generic input/output
TPC output (TP11 to TP8), 8-bit timer input and output (TMIO3, TMO2, TMIO1, TMO0), DMAC input (DREQ1, DREQ0), CS7 to CS4 output, and generic input/output
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8.2
8.2.1
Port 4
Overview
Port 4 is an 8-bit input/output port with the pin configuration shown in figure 8.1. When the bus width control register (ABWCR) designates areas 0 to 7 all as 8-bit-access areas, the chip operates in 8-bit bus mode and port 4 is a generic input/output port. When at least one of areas 0 to 7 is designated as a 16-bit-access area, the chip operates in 16-bit bus mode and port 4 becomes part of the data bus. Port 4 has software-programmable built-in pull-up transistors. Pins in port 4 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor pair.
Port 4 pins P47 /D7 P46 /D6 P45 /D5 Port 4 P44 /D4 P43 /D3 P42 /D2 P41 /D1 P40 /D0 Modes 1 to 4 P47 (input/output)/D7 (input/output) P46 (input/output)/D6 (input/output) P45 (input/output)/D5 (input/output) P44 (input/output)/D4 (input/output) P43 (input/output)/D3 (input/output) P42 (input/output)/D2 (input/output) P41 (input/output)/D1 (input/output) P40 (input/output)/D0 (input/output)
Figure 8.1 Port 4 Pin Configuration
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8.2.2
Register Configuration
Table 8.2 summarizes the registers of port 4. Table 8.2
Address* H'EE003 H'FFFD3 H'EE03E Note: *
Port 4 Registers
Name Port 4 data direction register Port 4 data register Port 4 input pull-up MOS control register Abbreviation R/W P4DDR P4DR P4PCR W R/W R/W Initial Value H'00 H'00 H'00
Lower 20 bits of the address in advanced mode.
Port 4 Data Direction Register (P4DDR): P4DDR is an 8-bit write-only register that can select input or output for each pin in port 4.
Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
P4 7 DDR P4 6 DDR P4 5 DDR P4 4 DDR P4 3 DDR P4 2 DDR P4 1 DDR P4 0 DDR
Port 4 data direction 7 to 0 These bits select input or output for port 4 pins
When all areas are designated as 8-bit-access areas by the bus controller's bus width control register (ABWCR), selecting 8-bit bus mode, port 4 functions as an input/output port. In this case, a pin in port 4 becomes an output port if the corresponding P4DDR bit is set to 1, and an input port if this bit is cleared to 0. When at least one area is designated as a 16-bit-access area, selecting 16-bit bus mode, port 4 functions as part of the data bus, regardless of the P4DDR settings. P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. ABWCR and P4DDR are not initialized in software standby mode. When port 4 functions as a generic input/output port, if a P4DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode.
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Port 4 Data Register (P4DR): P4DR is an 8-bit readable/writable register that stores output data for port 4. When port 4 functions as an output port, the value of this register is output. When a bit in P4DDR is set to 1, if port 4 is read the value of the corresponding P4DR bit is returned. When a bit in P4DDR is cleared to 0, if port 4 is read the corresponding pin level is read.
Bit Initial value Read/Write 7 P4 7 0 R/W 6 P4 6 0 R/W 5 P4 5 0 R/W 4 P4 4 0 R/W 3 P4 3 0 R/W 2 P4 2 0 R/W 1 P4 1 0 R/W 0 P4 0 0 R/W
Port 4 data 7 to 0 These bits store data for port 4 pins
P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Port 4 Input Pull-Up MOS Control Register (P4PCR): P4PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port 4.
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
P4 7 PCR P4 6 PCR P4 5 PCR P4 4 PCR P4 3 PCR P4 2 PCR P4 1 PCR P4 0 PCR
Port 4 input pull-up control 7 to 0 These bits control input pull-up transistors built into port 4
In 8-bit bus mode when a P4DDR bit is cleared to 0 (selecting generic input), if the corresponding P4PCR bit is set to 1, the input pull-up transistor is turned on. P4PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Table 8.3 summarizes the states of the input pull-ups in each operating mode.
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Table 8.3
Mode
Input Pull-Up Transistor States (Port 4)
Reset Off Hardware Standby Mode Off Software Standby Mode On/off Off Other Modes On/off Off
8-bit bus mode 16-bit bus mode
Legend: Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P4PCR = 1 and P4DDR = 0. Otherwise, it is off.
8.3
8.3.1
Port 6
Overview
Port 6 is an 4-bit input/output port that is also used for input and output of bus control signals (BACK, BREQ, WAIT) and for clock () output. The port 6 pin configuration is shown in figure 8.2. The pin in port 6 functions are P67 (generic input)/, P62/BACK, P61/BREQ, and P60/WAIT. See table 8.5 for the selection of the pin functions. See Section 19, Power-Down State, for clock output pin. See Section 6, Bus Controller, for bus control I/O pin (BACK, BREQ and WAIT). Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor pair.
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Port 6 pins P67/ Port 6 P62/BACK P61/BREQ P60/WAIT P67 (input)/(output) P62 (input/output)/BACK (output) P61 (input/output)/BREQ (input) P60 (input/output)/WAIT (input)
Figure 8.2 Port 6 Pin Configuration 8.3.2 Register Configuration
Table 8.4 summarizes the registers of port 6. Table 8.4
Address* H'EE005 H'FFFD5 Note: *
Port 6 Registers
Name Port 6 data direction register Port 6 data register Abbreviation P6DDR P6DR R/W W R/W Initial Value H'80 H'80
Lower 20 bits of the address in advanced mode.
Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select input or output for each pin in port 6. Bits 7 to 3 are reserved. Bit 7 is fixed at 1, and cannot be modified.
Bit Initial value Read/Write 7 1 6 0 W 5 0 W Reserved bit 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
Port 6 data direction 2 to 0 These bits select input or output for port 6 pins
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P67 functions as the clock output pin () or an input port. P67 is the clock input pin () if the PSTOP bit in MSTCRH is cleared to 0 (initial value), and an input port if this bit is set to 1. When P62 to P60 function as input/output ports, the pin becomes an output port if the corresponding P6DDR bit is set to 1, and an input port if this bit is cleared to 0. P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode, it retains its previous setting. When port 6 functions as a generic input/output port, if a P6DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores output data for port 6. When port 6 functions as an output port, the value of this register is output.
Bit Initial value Read/Write 7 P67 * R 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W 3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W 0 P60 0 R/W
Data 7, 2 to 0 for port 6 pins Bits storing data for port 6 pins Reserved bit Note: * Determined by pin P67.
Bit 7 returns 1 if read when the PSTOP bit in MSTCRH is 0, and returns the logic level of pin P67 if read when the PSTOP bit is 1. This bit cannot be modified. Bits 6 to 3 are reserved; they can be read and written to, but cannot be used as ports. The P6DR value is returned if P6DR is read while the corresponding bit (P66DDR to P63DDR) in P6DDR is set to 1, and an undefined value is returned if P6DR is read while the corresponding bit is cleared to 0. For bits 2 to 0, the pin logic level is returned if the bit is read while the corresponding bit in P6DDR is cleared to 0, and the P6DR value is returned if the bit is read while the corresponding bit in P6DDR is set to 1. P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it retains its previous setting.
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Table 8.5
Pin P67/
Port 6 Pin Functions
Pin Functions and Selection Method Bit PSTOP in MSTCRH selects the pin function as follows. PSTOP Pin function 0 output 1 P67 input
P62/BACK
Bit BRLE in BRCR and bit P62DDR select the pin function as follows. BRLE P62DDR Pin function 0 P62 input 0 1 P62 output 1 BACK output
P61/BREQ
Bit BRLE in BRCR and bit P61DDR select the pin function as follows. BRLE P61DDR Pin function 0 P61 input 0 1 P61 output 1 BREQ input
P60/WAIT
Bit WAITE in BCR and bit P60DDR select the pin function as follows. WAITE P60DDR Pin function 0 P60 input 0 1 P60 output 1 0* WAIT input
Note: * Do not set bit P60DDR to 1.
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8.4
8.4.1
Port 7
Overview
Port 7 is an 8-bit input-only port that is also used for analog input to the A/D converter and analog output from the D/A converter. The pin functions are the same in all operating modes. Figure 8.3 shows the pin configuration of port 7. See section 15, A/D Converter, for details of the A/D converter analog input pins, and section 16, D/A Converter, for details of the D/A converter analog output pins.
Port 7 pins P77 (input)/AN 7 (input)/DA 1 (output) P76 (input)/AN 6 (input)/DA 0 (output) P75 (input)/AN 5 (input) Port 7 P74 (input)/AN 4 (input) P73 (input)/AN 3 (input) P72 (input)/AN 2 (input) P71 (input)/AN 1 (input) P70 (input)/AN 0 (input)
Figure 8.3 Port 7 Pin Configuration 8.4.2 Register Configuration
Table 8.6 summarizes the port 7 register. Port 7 is an input-only port, and so has no data direction register. Table 8.6
Address* H'FFFD6 Note: *
Port 7 Data Register
Name Port 7 data register Abbreviation P7DR R/W R Initial Value Undetermined
Lower 20 bits of the address in advanced mode.
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Port 7 Data Register (P7DR)
Bit Initial value Read/Write 7 P77 * R 6 P76 * R 5 P75 * R 4 P74 * R 3 P73 * R 2 P72 * R 1 P71 * R 0 P70 * R
Note: * Determined by pins P7 7 to P70 .
When port 7 is read, the pin logic levels are always read. P7DR cannot be modified.
8.5
8.5.1
Port 8
Overview
Port 8 is a 5-bit input/output port that is also used for CS3 to CS0 output, RFSH output, IRQ3 to IRQ0 input, and A/D converter ADTRG input. Figure 8.4 shows the pin configuration of port 8. See table 8.8 for the selection of pin functions. See section 15, A/D Converter, for a description of the A/D converter's ADTRG input pin. The IRQ3 to IRQ0 functions are selected by IER settings, regardless of whether the pin is used for input or output. Caution is therefore required. For details see section 5, Interrupt Controller. When DRAM is connected to areas 2 to 5, the CS3 and CS2 output pins function as RAS output pins for each area. For details see section 6.5, DRAM Interface. Pins in port 8 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor pair. Pins P82 to P80 have Schmitt-trigger inputs.
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Port 8 pins P84 / CS 0 P83 / CS 1 / IRQ 3 / ADTRG Port 8 P82 / CS 2 / IRQ 2 P81 / CS 3 / IRQ 1 P80 / RFSH /IRQ 0
Pin functions in modes 1 to 4 P84 (input)/ CS 0 (output) P83 (input)/ CS 1 (output)/ IRQ 3 (input) / ADTRG (input) P82 (input)/ CS 2 (output)/ IRQ 2 (input) P81 (input/output)/CS3 (output)/IRQ1 (input) P80 (input/output)/ RFSH (output)/ IRQ 0 (input)
Figure 8.4 Port 8 Pin Configuration 8.5.2 Register Configuration
Table 8.7 summarizes the registers of port 8. Table 8.7 Port 8 Registers
Initial Value Address* H'EE007 H'FFFD7 Note: * Name Port 8 data direction register Port 8 data register Abbreviation P8DDR P8DR R/W W R/W Mode 1 to 4 H'F0 H'E0
Lower 20 bits of the address in advanced mode.
Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select input or output for each pin in port 8. Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified.
Bit Initial value Read/Write 7 Modes 1 to 4 1 6 1 5 1 4 1 W 3 0 W 2 0 W 1 0 W 0 0 W
P84DDR P83DDR P82DDR P81DDR P80DDR
Reserved bits
Port 8 data direction 4 to 0 These bits select input or output for port 8 pins
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When bits in P8DDR bit are set to 1, P84 to P81 become CS0 to CS3 output pins. When bits in P8DDR are cleared to 0, the corresponding pins become input ports. Following a reset P84 functions as the CS0 output, while the other three pins are input ports. When the refresh enable bit (RFSHE) in DRCRA is set to 1, P80 is used for RFSH output. When RFSHE is cleared to 0, P80 becomes an input/output port according to the P8DDR setting. For details see table 8.8. P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P8DDR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode P8DDR retains its previous setting. Therefore, when port 8 functions as an input/output port, if a transition is made to software standby mode while a P8DDR bit is set to 1, the corresponding pin maintains its output state. Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores output data for port 8. When a bit in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR bit is returned. When a bit in P8DDR is cleared to 0, if port 8 is read the corresponding pin level is read. Bits 7 to 5 are reserved. They cannot be modified and always are read as 1.
Bit Initial value Read/Write 7 1 6 1 Reserved bits 5 1 4 P8 4 0 R/W 3 P8 3 0 R/W 2 P8 2 0 R/W 1 P8 1 0 R/W 0 P8 0 0 R/W
Port 8 data 4 to 0 These bits store data for port 8 pins
P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting.
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Table 8.8
Pin P84/CS0
Port 8 Pin Functions
Pin Functions and Selection Method Bit P84DDR selects the pin function as follows. P84DDR Pin function 0 P84 input 1 CS0 output
P83/CS1/IRQ3/ADTRG Bit P83DDR selects the pin function as follows P83DDR Pin function 0 P83 input IRQ3 input ADTRG input P82/CS2/IRQ2 The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, and bit P82DDR, select the pin function as follows. DRAM interface settings P82DDR Pin function (1) in table below 0 P82 input 1 CS2 output IRQ3 input Note: * CS2 is output as RAS2. DRAM interface setting DRAS2 DRAS1 DRAS0 0 0 1 0 (1) 0 1 1 0 0 1 0 (2) 1 1 1 (2) in table below CS2 output* 1 CS1 output
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8. I/O Ports Pin P81/CS3/IRQ1 Pin Functions and Selection Method The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, and bit P81DDR, select the pin function as follows. DRAM interface settings P81DDR Pin function (1) in table below 0 P81 input 1 CS3 output (2) in table below 0 P81 input IRQ1 input Note: * CS3 is output as RAS3. DRAM interface setting DRAS2 DRAS1 DRAS0 P80/RFSH/IRQ0 0 0 1 0 (1) 0 1 1 0 0 1 0 (3) (2) (3) 1 1 1 (2) 1 P81 output (3) in table below CS3 output*
Bit RFSHE in DRCRA and bit P80DDR select the pin function as follows. If areas 2 to 5 are not designated as DRAM space, do not set bit RFSHE in DRCRA to 1. RFSHE P80DDR Pin function 0 P80 input 0 1 P80 output IRQ0 input 1 RFSH output
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8.6
8.6.1
Port 9
Overview
Port 9 is a 6-bit input/output port that is also used for input and output (TxD0, TxD1, RxD0, RxD1, SCK0, SCK1) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ5 and IRQ4 input. See table 8.10 for the selection of pin functions. The IRQ5 and IRQ4 functions are selected by IER settings, regardless of whether the pin is used for input or output. Caution is therefore required. For details see section 5.3.1, External Interrupts. Port 9 has the same set of pin functions in all operating modes. Figure 8.5 shows the pin configuration of port 9. Pins in port 9 can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington transistor pair.
Port 9 pins P95 (input/output)/SCK 1 (input/output)/IRQ 5 (input) P94 (input/output)/SCK 0 (input/output)/IRQ 4 (input) Port 9 P93 (input/output)/RxD1 (input) P92 (input/output)/RxD0 (input) P91 (input/output)/TxD1 (output) P90 (input/output)/TxD0 (output)
Figure 8.5 Port 9 Pin Configuration
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8.6.2
Register Configuration
Table 8.9 summarizes the registers of port 9. Table 8.9
Address* H'EE008 H'FFFD8 Note: *
Port 9 Registers
Name Port 9 data direction register Port 9 data register Abbreviation P9DDR P9DR R/W W R/W Initial Value H'C0 H'C0
Lower 20 bits of the address in advanced mode.
Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select input or output for each pin in port 9. Bits 7 and 6 are reserved. They cannot be modified and always read as 1.
Bit Initial value Read/Write 7 1 6 1 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
P9 5 DDR P9 4 DDR P9 3 DDR P9 2 DDR P9 1 DDR P9 0 DDR
Reserved bits
Port 9 data direction 5 to 0 These bits select input or output for port 9 pins
When a pin in port 9 becomes an output port if the corresponding P9DDR bit is set to 1, and an input port if this bit is cleared to 0. P9DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P9DDR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. When transition is made to software standby mode while a P9DDR bit is set to 1, the corresponding pin maintains its output state. Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores output data for port 9. When port 9 functions as an output port, the value of this register is output. When a bit in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned. When a bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin level is read.
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Bits 7 and 6 are reserved. They cannot be modified and are always read as 1.
Bit Initial value Read/Write 7 1 6 1 5 P9 5 0 R/W 4 P9 4 0 R/W 3 P9 3 0 R/W 2 P9 2 0 R/W 1 P9 1 0 R/W 0 P9 0 0 R/W
Reserved bits
Port 9 data 5 to 0 These bits store data for port 9 pins
P9DR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Table 8.10 Port 9 Pin Functions
Pin P95/SCK1/IRQ5 Pin Functions and Selection Method Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR, and bit P95DDR select the pin function as follows. CKE1 C/A CKE0 P95DDR Pin function 0 P95 input 0 1 P95 output 0 1 SCK1 output IRQ5 input P94/SCK0/IRQ4 Bit C/A in SMR of SCI0, bits CKE0 and CKE1 in SCR, and bit P94DDR select the pin function as follows. CKE1 C/A CKE0 P94DDR Pin function 0 P94 input 0 1 P94 output 0 1 SCK0 output IRQ4 input 0 1 SCK0 output 1 SCK0 input 0 1 SCK1 output 1 SCK1 input
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8. I/O Ports Pin P93/RxD1 Pin Functions and Selection Method Bit RE in SCR of SCI1, bit SMIF in SCMR, and bit P93DDR select the pin function as follows. SMIF RE P93DDR Pin function P92/RxD0 0 P93 input 0 1 P93 output 0 1 RxD1 input 1 RxD1 input
Bit RE in SCR of SCI0, bit SMIF in SCMR, and bit P92DDR select the pin function as follows. SMIF RE P92DDR Pin function 0 P92 input 0 1 P92 output 0 1 RxD0 input 1 RxD0 input
P91/TxD1
Bit TE in SCR of SCI1, bit SMIF in SCMR, and bit P91DDR select the pin function as follows. SMIF TE P91 DDR Pin function 0 P91 input 0 1 P91 output 0 1 1
TxD1 output TxD1 output*
Note: * Functions as the TxD1 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at highimpedance. P90/TxD0 Bit TE in SCR of SCI0, bit SMIF in SCMR, and bit P90DDR select the pin function as follows. SMIF TE P90DDR Pin function 0 P90 input 0 1 P90 output 0 1 1
TxD0 output TxD0 output*
Note: * Functions as the TxD0 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at highimpedance.
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8.7
8.7.1
Port A
Overview
Port A is an 8-bit input/output port that is also used for output (TP7 to TP0) from the programmable timing pattern controller (TPC), input and output, (TIOCB2, TIOCA2, TIOCB1, TIOCA1, TIOCB0, TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit timer, input (TCLKD, TCLKC, TCLKB, TCLKA) to the 8-bit timer, output (TEND1, TEND0) from the DMA controller (DMAC), and address output (A23 to A20). A reset or hardware standby transition leaves port A as an input port, except that in modes 3 and 4, one pin is always used for A20 output. See table 8.12 to 8.14 for the selection of pin functions. Usage of pins for TPC, 16-bit timer, 8-bit timer, and DMAC input and output is described in the sections on those modules. For output of address bits A23 to A21 in modes 3 and 4, see section 6.2.4, Bus Release Control Register (BRCR). Pins not assigned to any of these functions are available for generic input/output. Figure 8.6 shows the pin configuration of port A. Pins in port A can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington transistor pair. Port A has Schmitt-trigger inputs.
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Port A pins PA 7 /TP7 /TIOCB2 /A20 PA 6 /TP6 /TIOCA2 /A21 PA 5 /TP5 /TIOCB1 /A22 PA 4 /TP4 /TIOCA1 /A23 Port A PA 3 /TP3 /TIOCB0 /TCLKD PA 2 /TP2 /TIOCA0 /TCLKC PA 1 /TP1 /TEND1 /TCLKB PA 0 /TP0 /TEND0 /TCLKA Pin functions in modes 1 and 2 PA 7 (input/output)/TP7 (output)/TIOCB 2 (input/output) PA 6 (input/output)/TP6 (output)/TIOCA 2 (input/output) PA 5 (input/output)/TP5 (output)/TIOCB 1 (input/output) PA 4 (input/output)/TP4 (output)/TIOCA 1 (input/output) PA 3 (input/output)/TP3 (output)/TIOCB 0 (input/output)/TCLKD (input) PA 2 (input/output)/TP2 (output)/TIOCA 0 (input/output)/TCLKC (input) PA 1 (input/output)/TP1 (output)/TEND 1 (output)/TCLKB (input) PA 0 (input/output)/TP0 (output)/TEND 0 (output)/TCLKA (input) Pin functions in modes 3 and 4 A 20 (output) PA 6 (input/output)/TP 6 (output)/TIOCA 2 (input/output)/A21 (output) PA 5 (input/output)/TP 5 (output)/TIOCB 1 (input/output)/A22 (output) PA 4 (input/output)/TP 4 (output)/TIOCA 1 (input/output)/A23 (output) PA 3 (input/output)/TP 3 (output)/TIOCB 0 (input/output)/TCLKD (input) PA 2 (input/output)/TP 2 (output)/TIOCA 0 (input/output)/TCLKC (input) PA 1 (input/output)/TP 1 (output)/TEND 1 (output)/TCLKB (input) PA 0 (input/output)/TP 0 (output)/TEND 0 (output)/TCLKA (input)
Figure 8.6 Port A Pin Configuration
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8.7.2
Register Configuration
Table 8.11 summarizes the registers of port A. Table 8.11 Port A Registers
Initial Value Address* H'EE009 H'FFFD9 Note: * Name Port A data direction register Port A data register Abbreviation PADDR PADR R/W W R/W Modes 1, 2 H'00 H'00 Modes 3, 4 H'80 H'00
Lower 20 bits of the address in advanced mode.
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select input or output for each pin in port A. When pins are used for TPC output, the corresponding PADDR bits must also be set.
Bit 7 6 0 W 0 W 5 0 W 0 W 4 0 W 0 W 3 0 W 0 W 2 0 W 0 W 1 0 W 0 W 0 0 W 0 W
PA 7 DDR PA 6 DDR PA 5 DDR PA 4 DDR PA 3 DDR PA 2 DDR PA 1 DDR PA 0 DDR Modes Initial value 1 3, 4, Read/Write Modes Initial value 0 1, 2 Read/Write W
Port A data direction 7 to 0 These bits select input or output for port A pins
A pin in port A becomes an output port if the corresponding PADDR bit is set to 1, and an input port if this bit is cleared to 0. In modes 3 and 4, PA7DDR is fixed at 1 and PA7 functions as an address output pin. PADDR is a write-only register. Its value cannot be read. All bits return 1 when read. PADDR is initialized to H'00 (modes 1 and 2) or H'80 (modes 3 and 4) by a reset and in hardware standby mode. In software standby mode it retains it previous setting. Therefore, if a transition is made to software standby mode while a PADDR bit is set to 1, the corresponding pin maintains its output state.
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Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output data for port A. When port A functions as an output port, the value of this register is output. When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin level is read.
Bit Initial value Read/Write 7 PA 7 0 R/W 6 PA 6 0 R/W 5 PA 5 0 R/W 4 PA 4 0 R/W 3 PA 3 0 R/W 2 PA 2 0 R/W 1 PA 1 0 R/W 0 PA 0 0 R/W
Port A data 7 to 0 These bits store data for port A pins
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Table 8.12 Port A Pin Functions (Modes 1, 2)
Pin PA7/TP7/ TIOCB2 Pin Functions and Selection Method Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, and bit PA7DDR select the pin function as follows. 16-bit timer channel 2 settings PA7DDR NDER7 Pin function (1) in table below TIOCB2 output 0 PA7 input (2) in table below 1 0 PA7 output TIOCB2 input* Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0. 16-bit timer channel 2 settings IOB2 IOB1 IOB0 0 0 (2) 0 0 1 1 (1) (2) 1 1 1 TP7 output
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8. I/O Ports Pin PA6/TP6/ TIOCA2 Pin Functions and Selection Method Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, and bit PA6DDR select the pin function as follows. 16-bit timer channel 2 settings PA6DDR NDER6 Pin function (1) in table below TIOCA2 output 0 PA6 input (2) in table below 1 0 PA6 output TIOCA2 input* Note: * TIOCA2 input when IOA2 = 1. 16-bit timer channel 2 settings PWM2 IOA2 IOA1 IOA0 PA5/TP5/ TIOCB1 0 0 0 0 1 1 (2) (1) 0 1 (2) (1) 1 1 1 TP6 output
Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, and bit PA5DDR select the pin function as follows. 16-bit timer channel 1 settings PA5DDR NDER5 Pin function (1) in table below TIOCB1 output 0 PA5 input (2) in table below 1 0 PA5 output TIOCB1 input* Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0. 16-bit timer channel 1 settings IOB2 IOB1 IOB0 0 0 (2) 0 0 1 1 (1) (2) 1 1 1 TP5 output
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8. I/O Ports Pin PA4/TP4/ TIOCA1 Pin Functions and Selection Method Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, and bit PA4DDR select the pin function as follows. 16-bit timer channel 1 settings PA4DDR NDER4 Pin function (1) in table below TIOCA1 output 0 PA4 input (2) in table below 1 0 PA4 output TIOCA1 input* Note: * TIOCA1 input when IOA2 = 1. 16-bit timer channel 1 settings PWM1 IOA2 IOA1 IOA0 0 0 0 0 1 1 (2) (1) 0 1 (2) (1) 1 1 1 TP4 output
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Table 8.13 Port A Pin Functions (Modes 3, 4)
Pin PA7/TP7/ Pin Functions and Selection Method Always used as A20 output. A20 output
TIOCB2/ A20 Pin function
PA6/TP6/ Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, bit A21E in TIOCA2/A21 BRCR, and bit PA6DDR select the pin function as follows. A21E 16-bit timer channel 2 settings PA6DDR NDER6 Pin function (1) in table below TIOCA2 output 0 PA6 input 1 (2) in table below 1 0 PA6 output TIOCA2 input* Note: * TIOCA2 input when IOA2 = 1. 16-bit timer channel 2 settings PWM2 IOA2 IOA1 IOA0 0 0 0 0 1 1 (2) (1) 0 1 (2) (1) 1 1 1 TP6 output 0 A21 output
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PA5/TP5/ Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, bit A22E in TIOCB1/A22 BRCR, and bit PA5DDR select the pin function as follows. A22E 16-bit timer channel 1 settings PA5DDR NDER5 Pin function (1) in table below TIOCB1 output 0 PA5 input 1 (2) in table below 1 0 PA5 output TIOCB1 input* Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0. 16-bit timer channel 1 settings IOB2 IOB1 IOB0 0 0 (2) 0 0 1 1 (1) (2) 1 1 1 TP5 output 0 A22 output
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PA4/TP4/ Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, bit A23E in TIOCA1/A23 BRCR, and bit PA4DDR select the pin function as follows. A23E 16-bit timer channel 1 settings PA4DDR NDER4 Pin function (1) in table below TIOCA1 output 0 PA4 input 1 (2) in table below 1 0 PA4 output TIOCA1 input* Note: * TIOCA1 input when IOA2 = 1. 16-bit timer channel 1 settings PWM1 IOA2 IOA1 IOA0 0 0 0 0 1 1 (2) (1) 0 1 (2) (1) 1 1 1 TP4 output 0 A23 output
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Table 8.14 Port A Pin Functions (Modes 1 to 4)
Pin PA3/TP3/ TIOCB0/ TCLKD Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOB2 to IOB0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR2 of the 8-bit timer, bit NDER3 in NDERA, and bit PA3DDR select the pin function as follows. 16-bit timer channel 0 settings PA3DDR NDER3 Pin function (1) in table below TIOCB0 output 0 PA3 input
2
(2) in table below 1 0 PA3 output TIOCB0 input* TCLKD input*
1
1 1 TP3 output
Notes: 1. TIOCB0 input when IOB2 = 1 and PWM0 = 0. 2. TCLKD input when TPSC2 = TPSC1 = TPSC0 = 1 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR2 are as shown in (3) in the table below. 16-bit timer channel 0 settings IOB2 IOB1 IOB0 8-bit timer channel 0 settings CKS2 CKS1 CKS0 0 0 0 1 0 0 (2) 0 0 1 1 (1) (2) 1
(4) 1
(3)
1
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8. I/O Ports Pin PA2/TP2/ TIOCA0/ TCLKC Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOA2 to IOA0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR0 of the 8-bit timer, bit NDER2 in NDERA, and bit PA2DDR select the pin function as follows. 16-bit timer channel 0 settings PA2DDR NDER2 Pin function (1) in table below TIOCA0 output 0 PA2 input
2
(2) in table below 1 0 PA2 output TIOCA0 input* TCLKC input*
1
1 1 TP2 output
Notes: 1. TIOCA0 input when IOA2 = 1. 2. TCLKC input when TPSC2 = TPSC1 = 1 and TPSC0 = 0 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR0 are as shown in (3) in the table below. 16-bit timer channel 0 settings PWM0 IOA2 IOA1 IOA0 8-bit timer channel 0 settings CKS2 CKS1 CKS0 0 0 0 1 0 0 0 0 1 1 (2) (1) 0 1 (2) (1) 1
(4) 1
(3)
1
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8. I/O Ports Pin PA1/TP1/ TCLKB/ TEND1 Pin Functions and Selection Method Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR3 of the 8-bit timer, bit NDER1 in NDERA, and bit PA1DDR select the pin function as follows. PA1DDR NDER1 Pin function 0 PA1 input 1 0 PA1 output TCLKB input*
1 2
1 1 TP1 output
TEND1 output*
Notes: 1. TCLKB input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0, and TPSC0 = 1 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR3 are as shown in (1) in the table below. 2. When an external request is specified as a DMAC activation source, TEND1 output regardless of bits PA1DDR and NDER1. 8-bit timer channel 3 settings CKS2 CKS1 CKS0 0 0 0 1 (2) 1 1 (1)
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8. I/O Ports Pin PA0/TP0/ TCLKA/ TEND0 Pin Functions and Selection Method Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR1 of the 8-bit timer, bit NDER0 in NDERA, and bit PA0DDR select the pin function as follows. PA0DDR NDER0 Pin function 0 PA0 input 0 PA0 output TCLKA input*
1 2
1 1 TP0 output
TEND0 output*
Notes: 1. TCLKA input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0 and TPSC0 = 0 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR0 are as shown in (1) in the table below. 2. When an external request is specified as a DMAC activation source, TEND0 output regardless of bits PA0DDR and NDER0. 8-bit timer channel 1 settings CKS2 CKS1 CKS0 0 0 0 1 (2) 1 1 (1)
8.8
8.8.1
Port B
Overview
Port B is an 8-bit input/output port that is also used for output (TP15 to TP8) from the programmable timing pattern controller (TPC), input/output (TMIO3, TMO2, TMIO1, TMO0) by the 8-bit timer, CS7 to CS4 output, input (DREQ1, DREQ0) to the DMA controller (DMAC), input and output (TxD2, RxD2, SCK2) by serial communication interface channel 2 (SCI2), and output (UCAS, LCAS) by the DRAM interface. See table 8.16 for the selection of pin functions. A reset or hardware standby transition leaves port B as an input port. For output of CS7 to CS4 in modes 1 to 4, see section 6.3.4, Chip Select Signals. Pins not assigned to any of these functions are available for generic input/output. When DRAM is connected to areas 2 to 5, the CS4 and CS5 output pins function as RAS output pins for each area. For details see section 6.5, DRAM Interface. Figure 8.7 shows the pin configuration of port B. Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive darlington transistor pair.
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Port B pins PB7/TP15 /RxD2 PB6/TP14 /TxD2 PB5/TP13 /SCK2/LCAS PB4/TP12 /UCAS Port B PB3/TP11 /TMIO3/DREQ1/CS4 PB2/TP10 /TMO2/CS5 PB1/TP9 /TMIO1/DREQ0/CS6 PB0/TP8 /TMO0/CS7
Pin states in modes 1 to 4
PB7 (input/output)/TP15 (output) /RxD2 (input) PB6 (input/output)/TP14 (output) /TxD2 (output) PB5 (input/output)/TP13 (output) /SCK2 (input/output) /LCAS (output) PB4 (input/output)/TP12 (output) /UCAS (output) PB3 (input/output)/TP11 (output) /TMIO3 (input/output) /DREQ1 (input) CS4 (output) PB2 (input/output)/TP10 (output) /TMO2 (output) /CS5 (output) PB1 (input/output)/TP9 (output) /TMIO1 (input/output) /DREQ0 (input) /CS6 (output) PB0 (input/output)/TP8 (output) /TMO0 (output) /CS7 (output)
Figure 8.7 Port B Pin Configuration 8.8.2 Register Configuration
Table 8.15 summarizes the registers of port B. Table 8.15 Port B Registers
Address* H'EE00A H'FFFDA Note: * Name Port B data direction register Port B data register Abbreviation PBDDR PBDR R/W W R/W Initial Value H'00 H'00
Lower 20 bits of the address in advanced mode.
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Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select input or output for each pin in port B. When pins are used for TPC output, the corresponding PBDDR bits must also be set.
Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR
Port B data direction 7 to 0 These bits select input or output for port B pins
When a pin in port B becomes an output port if the corresponding PBDDR bit is set to 1, and an input port if this bit is cleared to 0. PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read. PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. When transition is made to software standby mode while a PBDDR bit is set to 1, the corresponding pin maintains its output state. Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores output data for pins port B. When port B functions as an output port, the value of this register is output. When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin level is read.
Bit Initial value Read/Write 7 PB 7 0 R/W 6 PB 6 0 R/W 5 PB 5 0 R/W 4 PB 4 0 R/W 3 PB 3 0 R/W 2 PB 2 0 R/W 1 PB 1 0 R/W 0 PB 0 0 R/W
Port B data 7 to 0 These bits store data for port B pins
PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting.
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Table 8.16 Port B Pin Functions
Pin PB7/TP15/ RxD2 Pin Functions and Selection Method Bit RE in SCR of SCI2, bit SMIF in SCMR, bit NDER15 in NDERB, and bit PB7DDR select the pin function as follows. SMIF RE PB7DDR NDER15 Pin function PB6/TP14/ TxD2 0 PB7 input 0 1 0 PB7 output 1 1 TP15 output 0 1 RxD2 input 1 RxD2 input
Bit TE in SCR of SCI2, bit SMIF in SCMR, bit NDER14 in NDERB, and bit PB6DDR select the pin function as follows. SMIF TE PB6DDR NDER14 Pin function 0 PB6 input 0 1 0 PB6 output 1 1 TP14 output 0 1 TxD2 output 1 TxD2 output*
Note: * Functions as the TxD2 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high-impedance. PB5/TP13/ Bit C/A in SMR of SCI2, bits CKE0 and CKE1 in SCR, bit NDER13 in NDERB, and SCK2/LCAS bit PB5DDR select the pin function as follows. CKE1 C/A CKE0 PB5DDR NDER13 Pin function 0 PB5 input 0 1 0 PB5 output 1 1 TP13 output 0 1 SCK2 output 0 1 SCK2 output 1 SCK2 input
LCAS output* Note: * LCAS output depending on bits DRAS2 to DRAS0 in DRCRA and bit CSEL in DRCRB, and regardless of bits C/A, CKE0 and CKE1, NDER13, and PB5DDR. For details, see section 6, Bus Controller.
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8. I/O Ports Pin PB4/TP12/ UCAS Pin Functions and Selection Method Bit NDER12 in NDERB and bit PB4DDR select the pin function as follows. PB4DDR NDER12 Pin function 0 PB4 input 1 0 PB4 output UCAS output* Note: * UCAS output depending on bits DRAS2 to DRAS0 in DRCRA and bit CSEL in DRCRB, and regardless of bits NDER12 and PB4DDR. For details, see section 6, Bus Controller. PB3/TP11/ The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and TMIO3/ OS1/0 in 8TCSR3, bits CCLR1 and CCLR0 in 8TCR3, bit CS4E in CSCR, bit DREQ1/CS4 NDER11 in NDERB, and bit PB3DDR select the pin function as follows. DRAM interface settings OIS3/2 and OS1/0 CS4E PB3DDR NDER11 Pin function 0 PB3 input 0 1 0 PB3 output
2
1 1 TP12 output
(1) in table below
(2) in table below Not all 0 1 TMIO3 output CS4 3 output*
All 0
1 1 TP11 output
CS4 output
1
TMIO3 input* DREQ1 input* Notes: 1. TMIO3 input when CCLR1 = CCLR0 = 1.
2. When an external request is specified as a DMAC activation source, DREQ1 input regardless of bits OIS3 and OIS2, OS1 and OS0, CCLR1 and CCLR0, CS4E, NDER11, and PB3DDR. 3. CS4 is output as RAS4. DRAM interface settings DRAS2 DRAS1 DRAS0 0 0 1 0 (1) 0 1 1 0 0 1 0 (2) 1 1 1 (1)
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8. I/O Ports Pin PB2/TP10/ TMO2/CS5 Pin Functions and Selection Method The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in 8TCSR2, bit CS5E in CSCR, bit NDER10 in NDERB, and bit PB2DDR select the pin function as follows. DRAM interface settings OIS3/2 and OS1/0 CS5E PB2DDR NDER10 Pin function 0 PB2 input 0 1 0 PB2 output 1 1 TP10 output (1) in table below (2) in table below Not all 0 1 CS5 output TMO2 output CS5 output*
All 0
Note: * CS5 is output as RAS5. DRAM interface settings DRAS2 DRAS1 DRAS0 0 0 1 0 0 1 1 0 0 1 0 (1) (2) 1 1 1 (1)
Bits OIS3/2 and OS1/0 in 8TCSR1, bits CCLR1 and CCLR0 in 8TCR0, bit CS6E in PB1/TP9/ CSCR, bit NDER9 in NDERB, and bit PB1DDR select the pin function as follows. TMIO1/ DREQ0/CS6 OIS3/2 and OS1/0 CS6E PB1DDR NDER9 Pin function 0 PB1 input 0 1 0 PB1 output 1 1 TP9 output TMIO1 input* Notes: 1. TMIO1 input when CCLR1 = CCLR0 = 1. 2. DREQ0 input when an external request is specified as a DMAC activation source, regardless of bits OIS3/2, OS1/0, CCLR1/0, CS6E, NDER9, PB1 DDR.
1 2
All 0 1 CS6 output
Not all 0 TMIO1 output
DREQ0 input*
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8. I/O Ports Pin PB0/TP8/ TMO0/CS7 Pin Functions and Selection Method Bits OIS3/2 and OS1/0 in 8TCSR0, bit CS7E in CSCR, bit NDER8 in NDERB, and bit PB0DDR select the pin function as follows. OIS3/2 and OS1/0 CS7E PB0DDR NDER8 Pin function 0 PB0 input 0 1 0 PB0 output 1 1 TP8 output All 0 1 CS7 output Not all 0 TMO0 output
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8. I/O Ports
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9. 16-Bit Timer
Section 9 16-Bit Timer
9.1 Overview
The H8/3006 and H8/3007 have built-in 16-bit timer module with three 16-bit counter channels. 9.1.1 Features
16-bit timer features are listed below. * Capability to process up to 6 pulse outputs or 6 pulse inputs * Six general registers (GRs, two per channel) with independently-assignable output compare or input capture functions * Selection of eight counter clock sources for each channel: Internal clocks: , /2, /4, /8 External clocks: TCLKA, TCLKB, TCLKC, TCLKD * Five operating modes selectable in all channels: Waveform output by compare match Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2) Input capture function Rising edge, falling edge, or both edges (selectable) Counter clearing function Counters can be cleared by compare match or input capture Synchronization Two or more timer counters (16TCNTs) can be preset simultaneously, or cleared simultaneously by compare match or input capture. Counter synchronization enables synchronous register input and output. PWM mode PWM output can be provided with an arbitrary duty cycle. With synchronization, up to three-phase PWM output is possible * Phase counting mode selectable in channel 2 Two-phase encoder output can be counted automatically. * High-speed access via internal 16-bit bus The 16TCNTs and GRs can be accessed at high speed via a 16-bit bus. * Any initial timer output value can be set
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9. 16-Bit Timer
* Nine interrupt sources Each channel has two compare match/input capture interrupts and an overflow interrupt. All interrupts can be requested independently. * Output triggering of programmable timing pattern controller (TPC) Compare match/input capture signals from channels 0 to 2 can be used as TPC output triggers. Table 9.1 summarizes the 16-bit timer functions. Table 9.1
Item Clock sources
16-bit timer Functions
Channel 0 Channel 1 Channel 2
Internal clocks: , /2, /4, /8 External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently
General registers (output compare/input capture registers) Input/output pins Counter clearing function
GRA0, GRB0
GRA1, GRB1
GRA2, GRB2
TIOCA0, TIOCB0 GRA0/GRB0 compare match or input capture Available Available Available Available Available Available Available Not available Three sources * Compare match/input capture A0 * Compare match/input capture B0 * Overflow
TIOCA1, TIOCB1 GRA1/GRB1 compare match or input capture Available Available Available Available Available Available Available Not available Three sources * Compare match/input capture A1 * Compare match/input capture B1 * Overflow
TIOCA2, TIOCB2 GRA2/GRB2 compare match or input capture Available Available Available Not available Available Available Available Available Three sources * Compare match/input capture A2 * Compare match/input capture B2 * Overflow
Initial output value setting function Compare match output 0 1 Toggle Input capture function Synchronization PWM mode Phase counting mode Interrupt sources
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9. 16-Bit Timer
9.1.2
Block Diagrams
16-bit timer Block Diagram (Overall): Figure 9.1 is a block diagram of the 16-bit timer.
TCLKA to TCLKD , /2, /4, /8
Clock selector Control logic
IMIA0 to IMIA2 IMIB0 to IMIB2 OVI0 to OVI2
TIOCA0 to TIOCA2 TIOCB0 to TIOCB2 TSTR
16-bit timer channel 2
16-bit timer channel 1
16-bit timer channel 0
TSNC
TOLR TISRA TISRB TISRC
Module data bus Legend: TSTR: Timer start register (8 bits) TSNC: Timer synchro register (8 bits) TMDR: Timer mode register (8 bits) TOLR: Timer output level setting register (8 bits) TISRA: Timer interrupt status register A (8 bits) TISRB: Timer interrupt status register B (8 bits) TISRC: Timer interrupt status register C (8 bits)
Figure 9.1 16-bit timer Block Diagram (Overall)
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Bus interface
TMDR
Internal data bus
9. 16-Bit Timer
Block Diagram of Channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical. Both have the structure shown in figure 9.2.
TCLKA to TCLKD , /2, /4, /8 Clock selector Control logic Comparator
TIOCA0 TIOCB0 IMIA0 IMIB0 OVI0
16TCNT
16TCR
Module data bus Legend: 16TCNT: GRA, GRB: 16TCR: TIOR:
Timer counter (16 bits) General registers A and B (input capture/output compare registers) (16 bits x 2) Timer control register (8 bits) Timer I/O control register (8 bits)
Figure 9.2 Block Diagram of Channels 0 and 1
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TIOR
GRA
GRB
9. 16-Bit Timer
Block Diagram of Channel 2: Figure 9.3 is a block diagram of channel 2
TCLKA to TCLKD , /2, /4, /8 Clock selector Control logic Comparator
TIOCA2 TIOCB2 IMIA2 IMIB2 OVI2
16TCNT2
16TCR2
Module data bus Legend: 16TCNT2: Timer counter 2 (16 bits) GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers) (16 bits x 2) 16TCR2: Timer control register 2 (8 bits) TIOR2: Timer I/O control register 2 (8 bits)
Figure 9.3 Block Diagram of Channel 2
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TIOR2
GRA2
GRB2
9. 16-Bit Timer
9.1.3
Pin Configuration
Table 9.2 summarizes the 16-bit timer pins. Table 9.2 16-bit timer Pins
Abbreviation TCLKA TCLKB TCLKC TCLKD Input/ Output Input Input Input Input Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Function External clock A input pin (phase-A input pin in phase counting mode) External clock B input pin (phase-B input pin in phase counting mode) External clock C input pin External clock D input pin GRA0 output compare or input capture pin PWM output pin in PWM mode GRB0 output compare or input capture pin GRA1 output compare or input capture pin PWM output pin in PWM mode GRB1 output compare or input capture pin GRA2 output compare or input capture pin PWM output pin in PWM mode GRB2 output compare or input capture pin
Channel Name Common Clock input A Clock input B Clock input C Clock input D 0
Input capture/output TIOCA0 compare A0 Input capture/output TIOCB0 compare B0
1
Input capture/output TIOCA1 compare A1 Input capture/output TIOCB1 compare B1
2
Input capture/output TIOCA2 compare A2 Input capture/output TIOCB2 compare B2
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9. 16-Bit Timer
9.1.4
Register Configuration
Table 9.3 summarizes the 16-bit timer registers. Table 9.3
Channel Common
16-bit timer Registers
Address* H'FFF60 H'FFF61 H'FFF62 H'FFF63 H'FFF64 H'FFF65 H'FFF66
1
Name Timer start register Timer synchro register Timer mode register Timer output level setting register Timer interrupt status register A Timer interrupt status register B Timer interrupt status register C Timer control register 0 Timer I/O control register 0 Timer counter 0H Timer counter 0L General register A0H General register A0L General register B0H General register B0L Timer control register 1 Timer I/O control register 1 Timer counter 1H Timer counter 1L General register A1H General register A1L General register B1H General register B1L
Abbreviation TSTR TSNC TMDR TOLR TISRA TISRB TISRC 16TCR0 TIOR0 16TCNT0H 16TCNT0L GRA0H GRA0L GRB0H GRB0L 16TCR1 TIOR1 16TCNT1H 16TCNT1L GRA1H GRA1L GRB1H GRB1L
R/W R/W R/W R/W W
2 2 2
Initial Value H'F8 H'F8 H'98 H'C0
R/(W)* H'88 R/(W)* H'88 R/(W)* H'88 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'80 H'88 H'00 H'00 H'FF H'FF H'FF H'FF H'80 H'88 H'00 H'00 H'FF H'FF H'FF H'FF
0
H'FFF68 H'FFF69 H'FFF6A H'FFF6B H'FFF6C H'FFF6D H'FFF6E H'FFF6F
1
H'FFF70 H'FFF71 H'FFF72 H'FFF73 H'FFF74 H'FFF75 H'FFF76 H'FFF77
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9. 16-Bit Timer Abbreviation 16TCR2 TIOR2 16TCNT2H 16TCNT2L GRA2H GRA2L GRB2H GRB2L Initial Value H'80 H'88 H'00 H'00 H'FF H'FF H'FF H'FF
Channel 2
Address* H'FFF78 H'FFF79 H'FFF7A H'FFF7B H'FFF7C H'FFF7D H'FFF7E H'FFF7F
1
Name Timer control register 2 Timer I/O control register 2 Timer counter 2H Timer counter 2L General register A2H General register A2L General register B2H General register B2L
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Notes: 1. The lower 20 bits of the address in advanced mode are indicated. 2. Only 0 can be written in bits 3 to 0, to clear the flags.
9.2
9.2.1
Register Descriptions
Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that starts and stops the timer counter (16TCNT) in channels 0 to 2.
Bit Initial value Read/Write 7 1 6 1 5 1 Reserved bits 4 1 3 1 2 STR2 0 R/W 1 STR1 0 R/W 0 STR0 0 R/W
Counter start 2 to 0 These bits start and stop 16TCNT2 to 16TCNT0
TSTR is initialized to H'F8 by a reset and in standby mode. Bits 7 to 3Reserved: These bits cannot be modified and are always read as 1. Bit 2Counter Start 2 (STR2): Starts and stops timer counter 2 (16TCNT2).
Bit 2 STR2 0 1 Description 16TCNT2 is halted 16TCNT2 is counting (Initial value)
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9. 16-Bit Timer
Bit 1Counter Start 1 (STR1): Starts and stops timer counter 1 (16TCNT1).
Bit 1 STR1 0 1 Description 16TCNT1 is halted 16TCNT1 is counting (Initial value)
Bit 0Counter Start 0 (STR0): Starts and stops timer counter 0 (16TCNT0).
Bit 0 STR0 0 1 Description 16TCNT0 is halted 16TCNT0 is counting (Initial value)
9.2.2
Timer Synchro Register (TSNC)
TSNC is an 8-bit readable/writable register that selects whether channels 0 to 2 operate independently or synchronously. Channels are synchronized by setting the corresponding bits to 1.
Bit Initial value Read/Write 7 1 6 1 5 1 Reserved bits 4 1 3 1 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W
Timer sync 2 to 0 These bits synchronize channels 2 to 0
TSNC is initialized to H'F8 by a reset and in standby mode. Bits 7 to 3Reserved: These bits cannot be modified and are always read as 1. Bit 2Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or synchronously.
Bit 2 SYNC2 0 1 Description Channel 2's timer counter (16TCNT2) operates independently 16TCNT2 is preset and cleared independently of other channels Channel 2 operates synchronously 16TCNT2 can be synchronously preset and cleared Rev.5.00 Sep. 12, 2007 Page 293 of 764 REJ09B0396-0500 (Initial value)
9. 16-Bit Timer
Bit 1Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or synchronously.
Bit 1 SYNC1 0 1 Description Channel 1's timer counter (16TCNT1) operates independently 16TCNT1 is preset and cleared independently of other channels Channel 1 operates synchronously 16TCNT1 can be synchronously preset and cleared (Initial value)
Bit 0Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or synchronously.
Bit 0 SYNC0 0 1 Description Channel 0's timer counter (16TCNT0) operates independently 16TCNT0 is preset and cleared independently of other channels Channel 0 operates synchronously 16TCNT0 can be synchronously preset and cleared (Initial value)
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9. 16-Bit Timer
9.2.3
Timer Mode Register (TMDR)
TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2. It also selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
Bit Initial value Read/Write 7 1 6 MDF 0 R/W 5 FDIR 0 R/W 4 1 3 1 2 PWM2 0 R/W 1 PWM1 0 R/W 0 PWM0 0 R/W
Reserved bit
PWM mode 2 to 0 These bits select PWM mode for channels 2 to 0
Flag direction Selects the setting condition for the overflow flag (OVF) in TISRC Phase counting mode flag Selects phase counting mode for channel 2 Reserved bit
TMDR is initialized to H'98 by a reset and in standby mode. Bit 7Reserved: This bit cannot be modified and is always read as 1. Bit 6Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in phase counting mode.
Bit 6 MDF 0 1 Description Channel 2 operates normally Channel 2 operates in phase counting mode (Initial value)
When MDF is set to 1 to select phase counting mode, 16TCNT2 operates as an up/down-counter and pins TCLKA and TCLKB become counter clock input pins. 16TCNT2 counts both rising and falling edges of TCLKA and TCLKB, and counts up or down as follows.
Counting Direction TCLKA pin TCLKB pin Low Down-Counting High High Low Up-Counting Low High High Low
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9. 16-Bit Timer
In phase counting mode channel 2 operates as above regardless of the external clock edges selected by bits CKEG1 and CKEG0 and the clock source selected by bits TPSC2 to TPSC0. Phase counting mode takes precedence over these settings. The counter clearing condition selected by the CCLR1 and CCLR0 bits in 16TCR2 and the compare match/input capture settings and interrupt functions of TIOR2, TISRA, TISRB, TISRC remain effective in phase counting mode. Bit 5Flag Direction (FDIR): Designates the setting condition for the OVF flag in TISRC. The FDIR designation is valid in all modes in channel 2.
Bit 5 FDIR 0 1 Description OVF is set to 1 in TISRC when 16TCNT2 overflows or underflows OVF is set to 1 in TISRC when 16TCNT2 overflows (Initial value)
Bits 4 and 3Reserved: These bits cannot be modified and are always read as 1. Bit 2PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode.
Bit 2 PWM2 0 1 Description Channel 2 operates normally Channel 2 operates in PWM mode (Initial value)
When bit PWM2 is set to 1 to select PWM mode, pin TIOCA2 becomes a PWM output pin. The output goes to 1 at compare match with GRA2, and to 0 at compare match with GRB2. Bit 1PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode.
Bit 1 PWM1 0 1 Description Channel 1 operates normally Channel 1 operates in PWM mode (Initial value)
When bit PWM1 is set to 1 to select PWM mode, pin TIOCA1 becomes a PWM output pin. The output goes to 1 at compare match with GRA1, and to 0 at compare match with GRB1.
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9. 16-Bit Timer
Bit 0PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode.
Bit 0 PWM0 0 1 Description Channel 0 operates normally Channel 0 operates in PWM mode (Initial value)
When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The output goes to 1 at compare match with GRA0, and to 0 at compare match with GRB0. 9.2.4 Timer Interrupt Status Register A (TISRA)
TISRA is an 8-bit readable/writable register that indicates GRA compare match or input capture and enables or disables general register compare match and input capture interrupt requests.
Bit 7 Initial value Read/Write 1 6 5 4 3 1 2 IMFA2 0 R/(W)* 1 IMFA1 0 R/(W)* 0 IMFA0 0 R/(W)*
IMIEA2 IMIEA1 IMIEA0 0 R/W 0 R/W 0 R/W
Input capture/compare match flags A2 to A0 Status flags indicating GRA compare match or input capture Reserved bit Input capture/compare match interrupt enable A2 to A0 These bits enable or disable interrupts by the IMFA flags Reserved bit
Note: * Only 0 can be written, to clear the flag.
TISRA is initialized to H'88 by a reset and in standby mode. Bit 7Reserved: This bit cannot be modified and is always read as 1.
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9. 16-Bit Timer
Bit 6Input Capture/Compare Match Interrupt Enable A2 (IMIEA2): Enables or disables the interrupt requested by the IMFA2 flag when IMFA2 is set to 1.
Bit 6 IMIEA2 0 1 Description IMIA2 interrupt requested by IMFA2 flag is disabled IMIA2 interrupt requested by IMFA2 flag is enabled (Initial value)
Bit 5Input Capture/Compare Match Interrupt Enable A1 (IMIEA1): Enables or disables the interrupt requested by the IMFA1 flag when IMFA1 is set to 1.
Bit 5 IMIEA1 0 1 Description IMIA1 interrupt requested by IMFA1 flag is disabled IMIA1 interrupt requested by IMFA1 flag is enabled (Initial value)
Bit 4Input Capture/Compare Match Interrupt Enable A0 (IMIEA0): Enables or disables the interrupt requested by the IMFA0 flag when IMFA0 is set to 1.
Bit 4 IMIEA0 0 1 Description IMIA0 interrupt requested by IMFA0 flag is disabled IMIA0 interrupt requested by IMFA0 flag is enabled (Initial value)
Bit 3Reserved: This bit cannot be modified and is always read as 1. Bit 2Input Capture/Compare Match Flag A2 (IMFA2): This status flag indicates GRA2 compare match or input capture events.
Bit 2 IMFA2 0 Description [Clearing conditions] * * 1 * * Read IMFA2 when IMFA2 =1, then write 0 in IMFA2. DMAC activated by IMIA2 interrupt. 16TCNT2 = GRA2 when GRA2 functions as an output compare register. 16TCNT2 value is transferred to GRA2 by an input capture signal when GRA2 functions as an input capture register. (Initial value)
[Setting conditions]
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9. 16-Bit Timer
Bit 1Input Capture/Compare Match Flag A1 (IMFA1): This status flag indicates GRA1 compare match or input capture events.
Bit 1 IMFA1 0 Description [Clearing conditions] * * 1 * * Read IMFA1 when IMFA1 =1, then write 0 in IMFA1. DMAC activated by IMIA1 interrupt. 16TCNT1 = GRA1 when GRA1 functions as an output compare register. 16TCNT1 value is transferred to GRA1 by an input capture signal when GRA1 functions as an input capture register. (Initial value)
[Setting conditions]
Bit 0Input Capture/Compare Match Flag A0 (IMFA0): This status flag indicates GRA0 compare match or input capture events.
Bit 0 IMFA0 0 Description [Clearing conditions] * * 1 * * Read IMFA0 when IMFA0 =1, then write 0 in IMFA0. DMAC activated by IMIA0 interrupt. 16TCNT0 = GRA0 when GRA0 functions as an output compare register. 16TCNT0 value is transferred to GRA0 by an input capture signal when GRA0 functions as an input capture register. (Initial value)
[Setting conditions]
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9. 16-Bit Timer
9.2.5
Timer Interrupt Status Register B (TISRB)
TISRB is an 8-bit readable/writable register that indicates GRB compare match or input capture and enables or disables general register compare match and input capture interrupt requests.
Bit 7 Initial value Read/Write 1 6 5 4 3 1 2 IMFB2 0 R/(W)* 1 IMFB1 0 R/(W)* 0 IMFB0 0 R/(W)*
IMIEB2 IMIEB1 IMIEB0 0 R/W 0 R/W 0 R/W
Input capture/compare match flags B2 to B0 Status flags indicating GRB compare match or input capture Reserved bit Input capture/compare match interrupt enable B2 to B0 These bits enable or disable interrupts by the IMFB flags Reserved bit
Note: * Only 0 can be written, to clear the flag.
TISRB is initialized to H'88 by a reset and in standby mode. Bit 7Reserved: This bit cannot be modified and is always read as 1. Bit 6Input Capture/Compare Match Interrupt Enable B2 (IMIEB2): Enables or disables the interrupt requested by the IMFB2 flag when IMFB2 is set to 1.
Bit 6 IMIEB2 0 1 Description IMIB2 interrupt requested by IMFB2 flag is disabled IMIB2 interrupt requested by IMFB2 flag is enabled (Initial value)
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9. 16-Bit Timer
Bit 5Input Capture/Compare Match Interrupt Enable B1 (IMIEB1): Enables or disables the interrupt requested by the IMFB1 flag when IMFB1 is set to 1.
Bit 5 IMIEB1 0 1 Description IMIB1 interrupt requested by IMFB1 flag is disabled IMIB1 interrupt requested by IMFB1 flag is enabled (Initial value)
Bit 4Input Capture/Compare Match Interrupt Enable B0 (IMIEB0): Enables or disables the interrupt requested by the IMFB0 flag when IMFB0 is set to 1.
Bit 4 IMIEB0 0 1 Description IMIB0 interrupt requested by IMFB0 flag is disabled IMIB0 interrupt requested by IMFB0 flag is enabled (Initial value)
Bit 3Reserved: This bit cannot be modified and is always read as 1. Bit 2Input Capture/Compare Match Flag B2 (IMFB2): This status flag indicates GRB2 compare match or input capture events.
Bit 2 IMFB2 0 1 Description [Clearing condition] Read IMFB2 when IMFB2 =1, then write 0 in IMFB2. [Setting conditions] * * 16TCNT2 = GRB2 when GRB2 functions as an output compare register. 16TCNT2 value is transferred to GRB2 by an input capture signal when GRB2 functions as an input capture register. (Initial value)
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9. 16-Bit Timer
Bit 1Input Capture/Compare Match Flag B1 (IMFB1): This status flag indicates GRB1 compare match or input capture events.
Bit 1 IMFB1 0 1 Description [Clearing condition] Read IMFB1 when IMFB1 =1, then write 0 in IMFB1. [Setting conditions] * * 16TCNT1 = GRB1 when GRB1 functions as an output compare register. 16TCNT1 value is transferred to GRB1 by an input capture signal when GRB1 functions as an input capture register. (Initial value)
Bit 0Input Capture/Compare Match Flag B0 (IMFB0): This status flag indicates GRB0 compare match or input capture events.
Bit 0 IMFB0 0 1 Description [Clearing condition] Read IMFB0 when IMFB0 =1, then write 0 in IMFB0. [Setting conditions] * * 16TCNT0 = GRB0 when GRB0 functions as an output compare register. 16TCNT0 value is transferred to GRB0 by an input capture signal when GRB0 functions as an input capture register. (Initial value)
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9. 16-Bit Timer
9.2.6
Timer Interrupt Status Register C (TISRC)
TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and enables or disables overflow interrupt requests.
Bit 7 Initial value Read/Write 1 6 OVIE2 0 R/W 5 OVIE1 0 R/W 4 OVIE0 0 R/W 3 1 2 OVF2 0 R/(W)* 1 OVF1 0 R/(W)* 0 OVF0 0 R/(W)*
Overflow flags 2 to 0 Status flags indicating interrupts by OVF flags Reserved bit Overflow interrupt enable 2 to 0 These bits enable or disable interrupts by the OVF flags Reserved bit
Note: * Only 0 can be written, to clear the flag.
TISRC is initialized to H'88 by a reset and in standby mode. Bit 7Reserved: This bit cannot be modified and is always read as 1. Bit 6Overflow Interrupt Enable 2 (OVIE2): Enables or disables the interrupt requested by the OVF2 flag when OVF2 is set to 1.
Bit 6 OVIE2 0 1 Description OVI2 interrupt requested by OVF2 flag is disabled OVI2 interrupt requested by OVF2 flag is enabled (Initial value)
Bit 5Overflow Interrupt Enable 1 (OVIE1): Enables or disables the interrupt requested by the OVF1 flag when OVF1 is set to 1.
Bit 5 OVIE1 0 1 Description OVI1 interrupt requested by OVF1 flag is disabled OVI1 interrupt requested by OVF1 flag is enabled Rev.5.00 Sep. 12, 2007 Page 303 of 764 REJ09B0396-0500 (Initial value)
9. 16-Bit Timer
Bit 4Overflow Interrupt Enable 0 (OVIE0): Enables or disables the interrupt requested by the OVF0 flag when OVF0 is set to 1.
Bit 4 OVIE0 0 1 Description OVI0 interrupt requested by OVF0 flag is disabled OVI0 interrupt requested by OVF0 flag is enabled (Initial value)
Bit 3Reserved: This bit cannot be modified and is always read as 1. Bit 2Overflow Flag 2 (OVF2): This status flag indicates 16TCNT2 overflow.
Bit 2 OVF2 0 1 Description [Clearing condition] Read OVF2 when OVF2 =1, then write 0 in OVF2. (Initial value)
[Setting condition] 16TCNT2 overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF.
Note: 16TCNT underflow occurs when 16TCNT operates as an up/down-counter. Underflow occurs only when channel 2 operates in phase counting mode (MDF = 1 in TMDR).
Bit 1Overflow Flag 1 (OVF1): This status flag indicates 16TCNT1 overflow.
Bit 1 OVF1 0 1 Description [Clearing condition] Read OVF1 when OVF1 =1, then write 0 in OVF1. [Setting condition] 16TCNT1 overflowed from H'FFFF to H'0000. (Initial value)
Bit 0Overflow Flag 0 (OVF0): This status flag indicates 16TCNT0 overflow.
Bit 0 OVF0 0 1 Description [Clearing condition] Read OVF0 when OVF0 =1, then write 0 in OVF0. [Setting condition] 16TCNT0 overflowed from H'FFFF to H'0000. (Initial value)
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9. 16-Bit Timer
9.2.7
Timer Counters (16TCNT)
16TCNT is a 16-bit counter. The 16-bit timer has three 16TCNTs, one for each channel.
Channel 0 1 2 Abbreviation 16TCNT0 16TCNT1 16TCNT2 Phase counting mode: up/down-counter Other modes: up-counter Function Up-counter
Bit Initial value Read/Write
15 0
14 0
13 0
12 0
11 0
10 0
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Each 16TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source. The clock source is selected by bits TPSC2 to TPSC0 in 16TCR. 16TCNT0 and 16TCNT1 are up-counters. 16TCNT2 is an up/down-counter in phase counting mode and an up-counter in other modes. 16TCNT can be cleared to H'0000 by compare match with GRA or GRB or by input capture to GRA or GRB (counter clearing function). When 16TCNT overflows (changes from H'FFFF to H'0000), the OVF flag is set to 1 in TISRC of the corresponding channel. When 16TCNT underflows (changes from H'0000 to H'FFFF), the OVF flag is set to 1 in TISRC of the corresponding channel. The 16TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either word access or byte access. Each 16TCNT is initialized to H'0000 by a reset and in standby mode.
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9. 16-Bit Timer
9.2.8
General Registers (GRA, GRB)
The general registers are 16-bit registers. The 16-bit timer has 6 general registers, two in each channel.
Channel 0 1 2 Abbreviation GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 Function Output compare/input capture register
Bit Initial value Read/Write
15 1
14 1
13 1
12 1
11 1
10 1
9 1
8 1
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
A general register is a 16-bit readable/writable register that can function as either an output compare register or an input capture register. The function is selected by settings in TIOR. When a general register is used as an output compare register, its value is constantly compared with the 16TCNT value. When the two values match (compare match), the IMFA or IMFB flag is set to 1 in TISRA/TISRB. Compare match output can be selected in TIOR. When a general register is used as an input capture register an external input capture signal are detected and the current 16TCNT value is stored in the general register. The corresponding IMFA or IMFB flag in TISRA/TISRB is set to 1 at the same time. The valid edge or edges of the input capture signal are selected in TIOR. TIOR settings are ignored in PWM mode. General registers are linked to the CPU by an internal 16-bit bus and can be written or read by either word access or byte access. General registers are initialized to the output compare function (with no output signal) by a reset and in standby mode. The initial value is H'FFFF.
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9. 16-Bit Timer
9.2.9
Timer Control Registers (16TCR)
16TCR is an 8-bit register. The 16-bit timer has three 16TCRs, one in each channel.
Channel 0 1 2 Abbreviation 16TCR0 16TCR1 16TCR2 Function CR controls the timer counter. The 16TCRs in all channels are functionally identical. When phase counting mode is selected in channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to TPSC0 in 16TCR2 are ignored.
Bit Initial value Read/Write
7 1
6 CCLR1 0 R/W
5 CCLR0 0 R/W
4 0 R/W
3 0 R/W
2 TPSC2 0 R/W
1 TPSC1 0 R/W
0 TPSC0 0 R/W
CKEG1 CKEG0
Timer prescaler 2 to 0 These bits select the counter clock Clock edge 1/0 These bits select external clock edges Counter clear 1/0 These bits select the counter clear source Reserved bit
Each 16TCR is an 8-bit readable/writable register that selects the timer counter clock source, selects the edge or edges of external clock sources, and selects how the counter is cleared. 16TCR is initialized to H'80 by a reset and in standby mode. Bit 7Reserved: This bit cannot be modified and is always read as 1.
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9. 16-Bit Timer
Bits 6 and 5Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select how 16TCNT is cleared.
Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description 16TCNT is not cleared 16TCNT is cleared by GRA compare match or input capture* 16TCNT is cleared by GRB compare match or input capture*
1 1
(Initial value)
Synchronous clear: 16TCNT is cleared in synchronization with other 2 synchronized timers*
Notes: 1. 16TCNT is cleared by compare match when the general register functions as an output compare register, and by input capture when the general register functions as an input capture register. 2. Selected in TSNC.
Bits 4 and 3Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select external clock input edges when an external clock source is used.
Bit 4 CKEG1 0 Bit 3 CKEG0 0 1 1 Description Count rising edges Count falling edges Count both edges (Initial value)
When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in 16TCR2 are ignored. Phase counting takes precedence.
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9. 16-Bit Timer
Bits 2 to 0Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock source.
Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Function Internal clock: Internal clock: /2 Internal clock: /4 Internal clock: /8 External clock A: TCLKA input External clock B: TCLKB input External clock C: TCLKC input External clock D: TCLKD input (Initial value)
When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts the edge or edges selected by bits CKEG1 and CKEG0. When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to TPSC0 in 16TCR2 are ignored. Phase counting takes precedence.
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9. 16-Bit Timer
9.2.10
Timer I/O Control Register (TIOR)
TIOR is an 8-bit register. The 16-bit timer has three TIORs, one in each channel.
Channel Abbreviation Function 0 1 2 TIOR0 TIOR1 TIOR2 TIOR controls the general registers. Some functions differ in PWM mode.
Bit Initial value Read/Write
7 1
6 IOB2 0 R/W
5 IOB1 0 R/W
4 IOB0 0 R/W
3 1
2 IOA2 0 R/W
1 IOA1 0 R/W
0 IOA0 0 R/W
I/O control A2 to A0 These bits select GRA functions Reserved bit I/O control B2 to B0 These bits select GRB functions Reserved bit
Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture function for GRA and GRB, and specifies the functions of the TIORA and TIORC pins. If the output compare function is selected, TIOR also selects the type of output. If input capture is selected, TIOR also selects the edge or edges of the input capture signal. TIOR is initialized to H'88 by a reset and in standby mode. Bit 7Reserved: This bit cannot be modified and is always read as 1.
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9. 16-Bit Timer
Bits 6 to 4I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function.
Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 Notes: 1. After a reset, the output conforms to the TOLR setting until the first compare match. 2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output instead. GRB is an input compare register Function GRB is an output compare register No output at compare match (Initial value)
1 1
0 output at GRB compare match* 1 output at GRB compare match*
Output toggles at GRB compare match 12 (1 output in channel 2)* * GRB captures rising edge of input GRB captures falling edge of input GRB captures both edges of input
Bit 3Reserved: This bit cannot be modified and is always read as 1. Bits 2 to 0I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function.
Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 Notes: 1. After a reset, the output conforms to the TOLR setting until the first compare match. 2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output instead. GRA is an input compare register Function GRA is an output compare register No output at compare match (Initial value)
1 1
0 output at GRA compare match* 1 output at GRA compare match*
Output toggles at GRA compare match 12 (1 output in channel 2)* * GRA captures rising edge of input GRA captures falling edge of input GRA captures both edges of input
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9. 16-Bit Timer
9.2.11
Timer Output Level Setting Register C (TOLR)
TOLR is an 8-bit write-only register that selects the timer output level for channels 0 to 2.
Bit 7 Initial value Read/Write 1 6 1 5 TOB2 0 W 4 TOA2 0 W 3 TOB1 0 W 2 TOA1 0 W 1 TOB0 0 W 0 TOA0 0 W
Output level setting A2 to A0, B2 to B0 These bits set the levels of the timer outputs (TIOCA2 to TIOCA0, and TIOCB2 to TIOCB0) Reserved bits
A TOLR setting can only be made when the corresponding bit in TSTR is 0. TOLR is a write-only register. If it is read, all bits will return a value of 1. TOLR is initialized to H'C0 by a reset and in standby mode. Bits 7 and 6Reserved: These bits cannot be modified. Bit 5Output Level Setting B2 (TOB2): Sets the value of timer output TIOCB2.
Bit 5 TOB2 0 1 Description TIOCB2 is 0 TIOCB2 is 1 (Initial value)
Bit 4Output Level Setting A2 (TOA2): Sets the value of timer output TIOCA2.
Bit 4 TOA2 0 1 Description TIOCA2 is 0 TIOCA2 is 1 (Initial value)
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9. 16-Bit Timer
Bit 3Output Level Setting B1 (TOB1): Sets the value of timer output TIOCB1.
Bit 3 TOB1 0 1 Description TIOCB1 is 0 TIOCB1 is 1 (Initial value)
Bit 2Output Level Setting A1 (TOA1): Sets the value of timer output TIOCA1.
Bit 2 TOA1 0 1 Description TIOCA1 is 0 TIOCA1 is 1 (Initial value)
Bit 1Output Level Setting B0 (TOB0): Sets the value of timer output TIOCB0.
Bit 0 TOB0 0 1 Description TIOCB0 is 0 TIOCB0 is 1 (Initial value)
Bit 0Output Level Setting A0 (TOA0): Sets the value of timer output TIOCA0.
Bit 0 TOA0 0 1 Description TIOCA0 is 0 TIOCA0 is 1 (Initial value)
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9. 16-Bit Timer
9.3
9.3.1
CPU Interface
16-Bit Accessible Registers
The timer counters (16TCNTs), general registers A and B (GRAs and GRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a word at a time, or a byte at a time. Figures 9.4 and 9.5 show examples of word read/write access to a timer counter (16TCNT). Figures 9.6, 9.7, 9.8, and 9.9 show examples of byte read/write access to 16TCNTH and 16TCNTL.
On-chip data bus H CPU L Bus interface H L Module data bus
16TCNTH
16TCNTL
Figure 9.4 Access to Timer Counter (CPU Writes to 16TCNT, Word)
On-chip data bus H CPU L Bus interface H L Module data bus
16TCNTH
16TCNTL
Figure 9.5 Access to Timer Counter (CPU Reads 16TCNT, Word)
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9. 16-Bit Timer
On-chip data bus H CPU L Bus interface H L Module data bus
16TCNTH
16TCNTL
Figure 9.6 Access to Timer Counter (CPU Writes to 16TCNTH, Upper Byte)
On-chip data bus H CPU L Bus interface H L Module data bus
16TCNTH
16TCNTL
Figure 9.7 Access to Timer Counter (CPU Writes to 16TCNTL, Lower Byte)
On-chip data bus H CPU L Bus interface H L Module data bus
16TCNTH
16TCNTL
Figure 9.8 Access to Timer Counter (CPU Reads 16TCNTH, Upper Byte)
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9. 16-Bit Timer
On-chip data bus H CPU L Bus interface H L Module data bus
16TCNTH
16TCNTL
Figure 9.9 Access to Timer Counter (CPU Reads 16TCNTL, Lower Byte) 9.3.2 8-Bit Accessible Registers
The registers other than the timer counters and general registers are 8-bit registers. These registers are linked to the CPU by an internal 8-bit data bus. Figures 9.10 and 9.11 show examples of byte read and write access to a 16TCR. If a word-size data transfer instruction is executed, two byte transfers are performed.
On-chip data bus H CPU L Bus interface H L Module data bus
16TCR
Figure 9.10 16TCR Access (CPU Writes to 16TCR)
On-chip data bus H CPU L Bus interface H L Module data bus
16TCR
Figure 9.11 16TCR Access (CPU Reads 16TCR)
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9. 16-Bit Timer
9.4
9.4.1
Operation
Overview
A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. General registers A and B can be used for input capture or output compare. Synchronous Operation: The timer counters in designated channels are preset synchronously. Data written to the timer counter in any one of these channels is simultaneously written to the timer counters in the other channels as well. The timer counters can also be cleared synchronously if so designated by the CCLR1 and CCLR0 bits in the 16TCRs. PWM Mode: A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare match A and to 0 at compare match B. The duty cycle can be varied from 0% to 100% depending on the settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB automatically become output compare registers. Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and TCLKB is detected and 16TCNT2 counts up or down accordingly. When phase counting mode is selected TCLKA and TCLKB become clock input pins and 16TCNT2 operates as an up/downcounter. 9.4.2 Basic Functions
Counter Operation: When one of bits STR0 to STR2 is set to 1 in the timer start register (TSTR), the timer counter (16TCNT) in the corresponding channel starts counting. The counting can be free-running or periodic. * Sample setup procedure for counter Figure 9.12 shows a sample procedure for setting up a counter.
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9. 16-Bit Timer
Counter setup
Select counter clock
1
Type of counting? Yes Periodic counting
No
Free-running counting
Select counter clear source
2
Select output compare register function
3
Set period
4
Start counter Periodic counter
5
Start counter Free-running counter
5
Figure 9.12 Counter Setup Procedure (Example) 1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in 16TCR to select the desired edge(s) of the external clock signal. 2. For periodic counting, set CCLR1 and CCLR0 in 16TCR to have 16TCNT cleared at GRA compare match or GRB compare match. 3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected in step 2. 4. Write the count period in GRA or GRB, whichever was selected in step 2. 5. Set the STR bit to 1 in TSTR to start the timer counter.
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9. 16-Bit Timer
* Free-running and periodic counter operation A reset leaves the counters (16TCNTs) in 16-bit timer channels 0 to 2 all set as free-running counters. A free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC. After the overflow, the counter continues counting up from H'0000. Figure 9.13 illustrates free-running counting.
16TCNT value H'FFFF
H'0000 STR0 to STR2 bit OVF
Time
Figure 9.13 Free-Running Counter Operation When a channel is set to have its counter cleared by compare match, in that channel 16TCNT operates as a periodic counter. Select the output compare function of GRA or GRB, set bit CCLR1 or CCLR0 in 16TCR to have the counter cleared by compare match, and set the count period in GRA or GRB. After these settings, the counter starts counting up as a periodic counter when the corresponding bit is set to 1 in TSTR. When the count matches GRA or GRB, the IMFA or IMFB flag is set to 1 in TISRA/TISRB and the counter is cleared to H'0000. If the corresponding IMIEA or IMIEB bit is set to 1 in TISRA/TISRB, a CPU interrupt is requested at this time. After the compare match, 16TCNT continues counting up from H'0000. Figure 9.14 illustrates periodic counting.
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9. 16-Bit Timer
16TCNT value GR
Counter cleared by general register compare match
H'0000 STR bit IMF
Time
Figure 9.14 Periodic Counter Operation * 16TCNT count timing Internal clock source Bits TPSC2 to TPSC0 in 16TCR select the system clock () or one of three internal clock sources obtained by prescaling the system clock (/2, /4, /8). Figure 9.15 shows the timing.
Internal clock 16TCNT input clock 16TCNT N-1 N N+1
Figure 9.15 Count Timing for Internal Clock Sources External clock source Bits TPSC2 to TPSC0 in 16TCR select an external clock input pin (TCLKA to TCLKD), and its valid edge or edges are selected by bits CKEG1 and CKEG0. The rising edge, falling edge, or both edges can be selected. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be counted correctly.
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9. 16-Bit Timer
Figure 9.16 shows the timing when both edges are detected.
External clock input 16TCNT input clock 16TCNT N-1 N N+1
Figure 9.16 Count Timing for External Clock Sources (when Both Edges Are Detected) Waveform Output by Compare Match: In 16-bit timer channels 0, 1 compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the output can only go to 0 or go to 1. * Sample setup procedure for waveform output by compare match Figure 9.17 shows an example of the setup procedure for waveform output by compare match.
Output setup 1. Select the compare match output mode (0, 1, or toggle) in TIOR. When a waveform output mode is selected, the pin switches from its generic input/ output function to the output compare function (TIOCA or TIOCB). An output compare pin outputs the value set in TOLR until the first compare match occurs. 2. Set a value in GRA or GRB to designate the compare match timing.
Select waveform output mode
1
Set output timing
2
Start counter
3
3. Set the STR bit to 1 in TSTR to start the timer counter.
Waveform output
Figure 9.17 Setup Procedure for Waveform Output by Compare Match (Example)
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9. 16-Bit Timer
* Examples of waveform output Figure 9.18 shows examples of 0 and 1 output. 16TCNT operates as a free-running counter, 0 output is selected for compare match A, and 1 output is selected for compare match B. When the pin is already at the selected output level, the pin level does not change.
16TCNT value H'FFFF GRB GRA H'0000 TIOCB Time No change No change 1 output
TIOCA
No change
No change
0 output
Figure 9.18 0 and 1 Output (TOA = 1, TOB = 0) Figure 9.19 shows examples of toggle output. 16TCNT operates as a periodic counter, cleared by compare match B. Toggle output is selected for both compare match A and B.
16TCNT value GRB
Counter cleared by compare match with GRB
GRA
H'0000 TIOCB
Time Toggle output Toggle output
TIOCA
Figure 9.19 Toggle Output (TOA = 1, TOB = 0)
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9. 16-Bit Timer
* Output compare output timing The compare match signal is generated in the last state in which 16TCNT and the general register match (when 16TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB). When 16TCNT matches a general register, the compare match signal is not generated until the next counter clock pulse. Figure 9.20 shows the output compare timing.
16TCNT input clock 16TCNT N N+1
GR Compare match signal TIOCA, TIOCB
N
Figure 9.20 Output Compare Output Timing Input Capture Function: The 16TCNT value can be captured into a general register when a transition occurs at an input capture/output compare pin (TIOCA or TIOCB). Capture can take place on the rising edge, falling edge, or both edges. The input capture function can be used to measure pulse width or period.
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9. 16-Bit Timer
* Sample setup procedure for input capture Figure 9.21 shows a sample procedure for setting up input capture.
Input selection 1. Set TIOR to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal. Clear the DDR bit to 0 before making these TIOR settings. 1
Select input-capture input
Start counter
2
2. Set the STR bit to 1 in TSTR to start the timer counter.
Input capture
Figure 9.21 Setup Procedure for Input Capture (Example) * Examples of input capture Figure 9.22 illustrates input capture when the falling edge of TIOCB and both edges of TIOCA are selected as capture edges. 16TCNT is cleared by input capture into GRB.
16TCNT value H'0180 H'0160 H'0005 H'0000 TIOCB
TIOCA
GRA
H'0005
H'0160
GRB
H'0180
Figure 9.22 Input Capture (Example)
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9. 16-Bit Timer
* Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 9.23 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges.
Input-capture input
Input capture signal
16TCNT
N
GRA, GRB
N
Figure 9.23 Input Capture Signal Timing
9.4.3
Synchronization
The synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). With appropriate 16TCR settings, two or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization enables additional general registers to be associated with a single time base. Synchronization can be selected for all channels (0 to 2).
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9. 16-Bit Timer
Sample Setup Procedure for Synchronization: Figure 9.24 shows a sample procedure for setting up synchronization.
Setup for synchronization Select synchronization 1
Synchronous preset
Synchronous clear
Write to 16TCNT
2
Clearing synchronized to this channel? Yes Select counter clear source
No
3
Select counter clear source
4
Start counter
5
Start counter
5
Synchronous preset
Counter clear
Synchronous clear
1. Set the SYNC bits to 1 in TSNC for the channels to be synchronized. 2. When a value is written in 16TCNT in one of the synchronized channels, the same value is simultaneously written in 16TCNT in the other channels. 3. Set the CCLR1 or CCLR0 bit in 16TCR to have the counter cleared by compare match or input capture. 4. Set the CCLR1 and CCLR0 bits in 16TCR to have the counter cleared synchronously. 5. Set the STR bits in TSTR to 1 to start the synchronized counters.
Figure 9.24 Setup Procedure for Synchronization (Example)
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9. 16-Bit Timer
Example of Synchronization: Figure 9.25 shows an example of synchronization. Channels 0, 1, and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by compare match with GRB0. A three-phase PWM waveform is output from pins TIOCA0, TIOCA1, and TIOCA2. For further information on PWM mode, see section 9.4.4, PWM Mode.
Value of 16TCNT0 to 16TCNT2 Synchronous clearing by GRB0 compare match GRB0 GRB1 GRA0 GRB2 GRA1 GRA2 H'0000 TIOCA0
TIOCA1
TIOCA2
Figure 9.25 Synchronization (Example) 9.4.4 PWM Mode
In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin. GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which the PWM output changes to 0. If either GRA or GRB is selected as the counter clear source, a PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin. PWM mode can be selected in all channels (0 to 2). Table 9.4 summarizes the PWM output pins and corresponding registers. If the same value is set in GRA and GRB, the output does not change when compare match occurs.
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9. 16-Bit Timer
Table 9.4
Channel 0 1 2
PWM Output Pins and Registers
Output Pin TIOCA0 TIOCA1 TIOCA2 1 Output GRA0 GRA1 GRA2 0 Output GRB0 GRB1 GRB2
Sample Setup Procedure for PWM Mode: Figure 9.26 shows a sample procedure for setting up PWM mode.
PWM mode
Select counter clock
1
Select counter clear source
2
Set GRA
3
Set GRB
4
Select PWM mode
5
Start counter
6
PWM mode
1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in 16TCR to select the desired edge(s) of the external clock signal. 2. Set bits CCLR1 and CCLR0 in 16TCR to select the counter clear source. 3. Set the time at which the PWM waveform should go to 1 in GRA. 4. Set the time at which the PWM waveform should go to 0 in GRB. 5. Set the PWM bit in TMDR to select PWM mode. When PWM mode is selected, regardless of the TIOR contents, GRA and GRB become output compare registers specifying the times at which the PWM output goes to 1 and 0. The TIOCA pin automatically becomes the PWM output pin. The TIOCB pin conforms to the settings of bits IOB1 and IOB0 in TIOR. If TIOCB output is not desired, clear both IOB1 and IOB0 to 0. 6. Set the STR bit to 1 in TSTR to start the timer counter.
Figure 9.26 Setup Procedure for PWM Mode (Example)
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9. 16-Bit Timer
Examples of PWM Mode: Figure 9.27 shows examples of operation in PWM mode. In PWM mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with GRB. In the examples shown, 16TCNT is cleared by compare match with GRA or GRB. Synchronized operation and free-running counting are also possible.
16TCNT value Counter cleared by compare match A GRA
GRB
H'0000
Time
TIOCA a. Counter cleared by GRA (TOA = 1)
16TCNT value Counter cleared by compare match B GRB
GRA
H'0000
Time
TIOCA b. Counter cleared by GRB (TOA = 0)
Figure 9.27 PWM Mode (Example 1) Figure 9.28 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB,
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9. 16-Bit Timer
the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a higher value than GRA, the duty cycle is 100%.
16TCNT value GRB Counter cleared by compare match B
GRA
H'0000
Time
TIOCA
Write to GRA
Write to GRA
a. 0% duty cycle (TOA = 0) 16TCNT value GRA Counter cleared by compare match A
GRB
H'0000
Time
TIOCA
Write to GRB
Write to GRB
b. 100% duty cycle (TOA = 1)
Figure 9.28 PWM Mode (Example 2)
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9. 16-Bit Timer
9.4.5
Phase Counting Mode
In phase counting mode the phase difference between two external clock inputs (at the TCLKA and TCLKB pins) is detected, and 16TCNT2 counts up or down accordingly. In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock input pins and 16TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to TPSC0, CKEG1, and CKEG0 in 16TCR2. Settings of bits CCLR1, CCLR0 in 16TCR2, and settings in TIOR2, TISRA, TISRB, TISRC, STR2 in TSTR, GRA2, and GRB2 are valid. The input capture and output compare functions can be used, and interrupts can be generated. Phase counting is available only in channel 2. Sample Setup Procedure for Phase Counting Mode: Figure 9.29 shows a sample procedure for setting up phase counting mode.
Phase counting mode
Select phase counting mode
1
Select flag setting condition
2
1. Set the MDF bit in TMDR to 1 to select phase counting mode. 2. Select the flag setting condition with the FDIR bit in TMDR. 3. Set the STR2 bit to 1 in TSTR to start the timer counter.
Start counter
3
Phase counting mode
Figure 9.29 Setup Procedure for Phase Counting Mode (Example)
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9. 16-Bit Timer
Example of Phase Counting Mode: Figure 9.30 shows an example of operations in phase counting mode. Table 9.5 lists the up-counting and down-counting conditions for 16TCNT2. In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states.
16TCNT2 value Counting up Counting down
TCLKB TCLKA
Figure 9.30 Operation in Phase Counting Mode (Example) Table 9.5 Up/Down Counting Conditions
Down-Counting High Low High Low Up-Counting High Low Low High
Counting Direction TCLKB pin TCLKA pin
Phase difference
Phase difference
Pulse width
Pulse width
TCLKA
TCLKB Phase difference and overlap: at least 1.5 states Pulse width: at least 2.5 states
Overlap
Overlap
Figure 9.31 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
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9. 16-Bit Timer
9.4.6
Setting Initial Value of 16-Bit Timer Output
Any desired value can be specified for the initial 16-bit timer output value when a timer count operation is started by making a setting in TOLR. Figure 9.32 shows the timing for setting the initial output value with TOLR. Only write to TOLR when the corresponding bit in TSTR is cleared to 0.
T1 T2 T3
Address bus
TOLR address
TOLR
N
16-bit timer output pin
N
Figure 9.32 Example of Timing for Setting Initial Value of 16-Bit Timer Output by Writing to TOLR
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9. 16-Bit Timer
9.5
Interrupts
The 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 9.5.1 Setting of Status Flags
Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when 16TCNT matches a general register (GR). The compare match signal is generated in the last state in which the values match (when 16TCNT is updated from the matching count to the next count). Therefore, when 16TCNT matches a general register, the compare match signal is not generated until the next 16TCNT clock input. Figure 9.33 shows the timing of the setting of IMFA and IMFB.
16TCNT input clock
16TCNT
N
N+1
GR
N
Compare match signal
IMF
IMI
Figure 9.33 Timing of Setting of IMFA and IMFB by Compare Match
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9. 16-Bit Timer
Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an input capture signal. The 16TCNT contents are simultaneously transferred to the corresponding general register. Figure 9.34 shows the timing.
Input capture signal
IMF
16TCNT
N
GR
N
IMI
Figure 9.34 Timing of Setting of IMFA and IMFB by Input Capture Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when 16TCNT overflows from H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 9.35 shows the timing.
16TCNT
Overflow signal
OVF
OVI
Figure 9.35 Timing of Setting of OVF
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9. 16-Bit Timer
9.5.2
Timing of Clearing of Status Flags
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. Figure 9.36 shows the timing.
TISR write cycle T1 T2 T3
Address
TISR address
IMF, OVF
Figure 9.36 Timing of Clearing of Status Flags 9.5.3 Interrupt Sources and DMA Controller Activation
Each 16-bit timer channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are nine interrupt sources of three kinds, all independently vectored. An interrupt is requested when the interrupt request flag are set to 1. The priority order of the channels can be modified in interrupt priority register A (IPRA). For details see section 5, Interrupt Controller. Compare match/input capture A interrupts in channels 0 to 2 can activate the DMA controller (DMAC). When the DMAC is activated a CPU interrupt is not requested. Table 9.6 lists the interrupt sources.
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9. 16-Bit Timer
Table 9.6
Channel 0
16-bit timer Interrupt Sources
Interrupt Source IMIA0 IMIB0 OVI0 Description Compare match/input capture A0 Compare match/input capture B0 Overflow 0 Compare match/input capture A1 Compare match/input capture B1 Overflow 1 Compare match/input capture A2 Compare match/input capture B2 Overflow 2 DMAC Activatable Yes No No Yes No No Yes No No Low Priority* High
1
IMIA1 IMIB1 OVI1
2
IMIA2 IMIB2 OVI2
Note:
*
The priority immediately after a reset is indicated. Inter-channel priorities can be changed by settings in IPRA.
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9. 16-Bit Timer
9.6
Usage Notes
This section describes contention and other matters requiring special attention during 16-bit timer operations. Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T3 state of a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 9.37.
16TCNT write cycle T1 T2 T3
Address bus
16TCNT address
Internal write signal
Counter clear signal
16TCNT
N
H'0000
Figure 9.37 Contention between 16TCNT Write and Clear
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9. 16-Bit Timer
Contention between 16TCNT Word Write and Increment: If an increment pulse occurs in the T3 state of a 16TCNT word write cycle, writing takes priority and 16TCNT is not incremented. Figure 9.38 shows the timing in this case.
16TCNT word write cycle T1 T2 T3
Address bus
16TCNT address
Internal write signal
16TCNT input clock
16TCNT
N
M 16TCNT write data
Figure 9.38 Contention between 16TCNT Word Write and Increment
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9. 16-Bit Timer
Contention between 16TCNT Byte Write and Increment: If an increment pulse occurs in the T2 or T3 state of a 16TCNT byte write cycle, writing takes priority and 16TCNT is not incremented. The 16TCNT byte that was not written retains its previous value. See figure 9.39, which shows an increment pulse occurring in the T2 state of a byte write to 16TCNTH.
16TCNTH byte write cycle T1 T2 T3
Address bus
16TCNTH address
Internal write signal
16TCNT input clock
16TCNTH
N 16TCNT write data
M
16TCNTL
X
X+1
X
Figure 9.39 Contention between 16TCNT Byte Write and Increment
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9. 16-Bit Timer
Contention between General Register Write and Compare Match: If a compare match occurs in the T3 state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 9.40.
General register write cycle T1 T2 T3
Address bus
GR address
Internal write signal
16TCNT
N
N+1
GR
N
M General register write data
Compare match signal
Inhibited
Figure 9.40 Contention between General Register Write and Compare Match
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9. 16-Bit Timer
Contention between 16TCNT Write and Overflow or Underflow: If an overflow occurs in the T3 state of a 16TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set to 1. The same holds for underflow. See figure 9.41.
16TCNT write cycle T1 T2 T3
Address bus
16TCNT address
Internal write signal
16TCNT input clock
Overflow signal
16TCNT
H'FFFF 16TCNT write data
M
OVF
Figure 9.41 Contention between 16TCNT Write and Overflow
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9. 16-Bit Timer
Contention between General Register Read and Input Capture: If an input capture signal occurs during the T3 state of a general register read cycle, the value before input capture is read. See figure 9.42.
General register read cycle T1 T2 T3
Address bus
GR address
Internal read signal
Input capture signal
GR
X
M
Internal data bus
X
Figure 9.42 Contention between General Register Read and Input Capture
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9. 16-Bit Timer
Contention between Counter Clearing by Input Capture and Counter Increment: If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The value before the counter is cleared is transferred to the general register. See figure 9.43.
Input capture signal
Counter clear signal
16TCNT input clock
16TCNT
N
H'0000
GR
N
Figure 9.43 Contention between Counter Clearing by Input Capture and Counter Increment
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9. 16-Bit Timer
Contention between General Register Write and Input Capture: If an input capture signal occurs in the T3 state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 9.44.
General register write cycle T1 T2 T3
Address bus
GR address
Internal write signal
Input capture signal
16TCNT
M
GR
M
Figure 9.44 Contention between General Register Write and Input Capture Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is cleared in the last state at which the 16TCNT value matches the general register value, at the time when this value would normally be updated to the next count. The actual counter frequency is therefore given by the following formula:
f= (N +1)
(f: counter frequency. : system clock frequency. N: value set in general register.)
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9. 16-Bit Timer
Note on Writes in Synchronized Operation: When channels are synchronized, if a 16TCNT value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (Example) When channels 1 and 2 are synchronized
* Byte write to channel 1 or byte write to channel 2 Write A to upper byte of channel 1
16TCNT1 16TCNT2
W Y
X Z
16TCNT1 16TCNT2
A A
X X
Upper byte Lower byte
Write A to lower byte of channel 2 16TCNT1 16TCNT2
Upper byte Lower byte Y Y A A
Upper byte Lower byte * Word write to channel 1 or word write to channel 2 16TCNT1 16TCNT2 W Y X Z Write AB word to channel 1 or 2 16TCNT1 16TCNT2 A A B B
Upper byte Lower byte
Upper byte Lower byte
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9. 16-Bit Timer
16-bit timer Operating Modes Table 9.7 (a) 16-bit timer Operating Modes (Channel 0)
Register Settings TSNC Operating Mode Synchronous preset PWM mode Output compare A Synchronization MDF TMDR FDIR PWM PWM0 = 1 PWM0 = 0 IOA2 = 0 Other bits unrestricted IOB2 = 0 Other bits unrestricted PWM0 = 0 IOA2 = 1 Other bits unrestricted IOB2 = 1 Other bits unrestricted CCLR1 = 0 CCLR0 = 1 CCLR1 = 1 CCLR0 = 0 CCLR1 = 1 CCLR0 = 1 * IOA TIOR0 IOB 16TCR0 Clear Select Clock Select
SYNC0 = 1
Output compare B
Input capture A
Input capture B
PWM0 = 0
Counter By compare clearing match/input capture A By compare match/input capture B Synchronous clear

SYNC0 = 1
Legend: Setting available (valid) Setting does not affect this mode Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
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9. 16-Bit Timer
Table 9.7 (b)
16-bit timer Operating Modes (Channel 1)
Register Settings TSNC TMDR MDF FDIR PWM PWM1 = 1 PWM1 = 0 IOA2 = 0 Other bits unrestricted IOB2 = 0 Other bits unrestricted PWM1 = 0 IOA2 = 1 Other bits unrestricted IOB2 = 1 Other bits unrestricted CCLR1 = 0 CCLR0 = 1 CCLR1 = 1 CCLR0 = 0 CCLR1 = 1 CCLR0 = 1 * IOA TIOR1 IOB 16TCR1 Clear Select Clock Select
Operating Mode Synchronous preset PWM mode Output compare A
Synchronization
SYNC1 = 1
Output compare B
Input capture A
Input capture B
PWM1 = 0
Counter By compare clearing match/input capture A By compare match/input capture B Synchronous clear

SYNC1 = 1
Legend: Setting available (valid) Setting does not affect this mode Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
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9. 16-Bit Timer
Table 9.7 (c)
16-bit timer Operating Modes (Channel 2)
Register Settings TSNC TMDR MDF FDIR PWM PWM2 = 1 PWM2 = 0 IOA2 = 0 Other bits unrestricted IOB2 = 0 Other bits unrestricted PWM2 = 0 IOA2 = 1 Other bits unrestricted IOB2 = 1 Other bits unrestricted CCLR1 = 0 CCLR0 = 1 CCLR1 = 1 CCLR0 = 0 CCLR1 = 1 CCLR0 = 1 * IOA TIOR2 IOB 16TCR2 Clear Select Clock Select
Operating Mode Synchronous preset PWM mode Output compare A
Synchronization SYNC2 = 1
Output compare B
Input capture A
Input capture B
PWM2 = 0
Counter By compare clearing match/input capture A By compare match/input capture B Synchronous clear Phase counting mode Legend: Setting available (valid) Setting does not affect this mode SYNC2 = 1
MDF = 1
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
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9. 16-Bit Timer
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10. 8-Bit Timers
Section 10 8-Bit Timers
10.1 Overview
The H8/3006 and H8/3007 have a built-in 8-bit timer module with four channels (TMR0, TMR1, TMR2, and TMR3), based on 8-bit counters. Each channel has an 8-bit timer counter (8TCNT) and two 8-bit time constant registers (TCORA and TCORB) that are constantly compared with the 8TCNT value to detect compare match events. The timers can be used as multifunctional timers in a variety of applications, including the generation of a rectangular-wave output with an arbitrary duty cycle. 10.1.1 Features
The features of the 8-bit timer module are listed below. * Selection of four clock sources The counters can be driven by one of three internal clock signals (/8, /64, or /8192) or an external clock input (enabling use as an external event counter). * Selection of three ways to clear the counters The counters can be cleared on compare match A or B, or input capture B. * Timer output controlled by two compare match signals The timer output signal in each channel is controlled by two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM output. * A/D converter can be activated by a compare match * Two channels can be cascaded Channels 0 and 1 can be operated as the upper and lower halves of a 16-bit timer (16-bit count mode). Channels 2 and 3 can be operated as the upper and lower halves of a 16-bit timer (16-bit count mode). Channel 1 can count channel 0 compare match events (compare match count mode). Channel 3 can count channel 2 compare match events (compare match count mode). * Input capture function can be set 8-bit or 16-bit input capture operation is available. * Twelve interrupt sources There are twelve interrupt sources: four compare match sources, four compare match/input capture sources, four overflow sources.
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10. 8-Bit Timers
Two of the compare match sources and two of the combined compare match/input capture sources each have an independent interrupt vector. The remaining compare match interrupts, combined compare match/input capture interrupts, and overflow interrupts have one interrupt vector for two sources. 10.1.2 Block Diagram
The 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0 and 1, and group 1 comprising channels 2 and 3. Figure 10.1 shows a block diagram of 8-bit timer group 0.
External clock sources TCLKA TCLKC Internal clock sources /8 /64 /8192
Clock select
Clock 1 Clock 0 TCORA0 Compare match A1 Compare match A0 Comparator A0 Overflow 1 Overflow 0 8TCNT0 8TCNT1 Comparator A1 TCORA1
TMO0 TMIO1 Control logic
Compare match B1 Compare match B0 Comparator B0 Input capture B1 TCORB0
Comparator B1
TCORB1
8TCSR0
8TCSR1
8TCR0 CMIA0 CMIB0 CMIA1/CMIB1 OVI0/OVI1 Interrupt signals Legend: TCORA: TCORB: 8TCNT: 8TCSR: 8TCR: Timer constant register A Timer constant register B Timer counter Timer control/status register Timer control register
8TCR1
Figure 10.1 Block Diagram of 8-Bit Timer Unit (Two Channels: Group 0)
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Internal bus
10. 8-Bit Timers
10.1.3
Pin Configuration
Table 10.1 summarizes the input/output pins of the 8-bit timer module. Table 10.1 8-Bit Timer Pins
Group 0 Channel Name 0 Timer output Timer clock input 1 Abbreviation I/O TMO0 TCLKC Input/output
Output Compare match output Input I/O Input Counter external clock input Compare match output/input capture input Counter external clock input
Timer input/output TMIO1 Timer clock input TCLKA TMO2 TCLKD
1
2
Timer output Timer clock input
Output Compare match output Input I/O Input Counter external clock input Compare match output/input capture input Counter external clock input
3
Timer input/output TMIO3 Timer clock input TCLKB
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10. 8-Bit Timers
10.1.4
Register Configuration
Table 10.2 summarizes the registers of the 8-bit timer module. Table 10.2 8-Bit Timer Registers
Channel Address* 0 H'FFF80 H'FFF82 H'FFF84 H'FFF86 H'FFF88 1 H'FFF81 H'FFF83 H'FFF85 H'FFF87 H'FFF89 2 H'FFF90 H'FFF92 H'FFF94 H'FFF96 H'FFF98 3 H'FFF91 H'FFF93 H'FFF95 H'FFF97 H'FFF99
1
Name Timer control register 0 Timer control/status register 0 Timer constant register A0 Timer constant register B0 Timer counter 0 Timer control register 1 Timer control/status register 1 Timer constant register A1 Timer constant register B1 Timer counter 1 Timer control register 2 Timer control/status register 2 Timer constant register A2 Timer constant register B2 Timer counter 2 Timer control register 3 Timer control/status register 3 Timer constant register A3 Timer constant register B3 Timer counter 3
Abbreviation R/W 8TCR0 8TCSR0 TCORA0 TCORB0 8TCNT0 8TCR1 8TCSR1 TCORA1 TCORB1 8TCNT1 8TCR2 8TCSR2 TCORA2 TCORB2 8TCNT2 8TCR3 8TCSR3 TCORA3 TCORB3 8TCNT3 R/W
2
Initial value H'00
R/(W)* H'00 R/W R/W R/W R/W
2
H'FF H'FF H'00 H'00
R/(W)* H'00 R/W R/W R/W R/W
2
H'FF H'FF H'00 H'00
R/(W)* H'10 R/W R/W R/W R/W
2
H'FF H'FF H'00 H'00
R/(W)* H'00 R/W R/W R/W H'FF H'FF H'00
Notes: 1. Indicates the lower 20 bits of the address in advanced mode. 2. Only 0 can be written to bits 7 to 5, to clear these flags.
Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the channel 0 register as the upper 8 bits and the channel 1 register as the lower 8 bits, so they can be accessed together by word access. Similarly, each pair of registers for channel 2 and channel 3 comprises a 16-bit register with the channel 2 register as the upper 8 bits and the channel 3 register as the lower 8 bits, so they can be accessed together by word access.
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10. 8-Bit Timers
10.2
10.2.1
Register Descriptions
Timer Counters (8TCNT)
8TCNT0 Bit 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 8TCNT1 4 0 3 0 2 0 1 0 0 0
Initial value Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8TCNT2 8TCNT3 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Bit Initial value Read/Write
15 0
14 0
13 0
12 0
11 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The timer counters (8TCNT) are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. The clock source is selected by clock select bits 2 to 0 (CKS2 to CKS0) in the timer control register (8TCR). The CPU can always read or write to the timer counters. The 8TCNT0 and 8TCNT1 pair, and the 8TCNT2 and 8TCNT3 pair, can each be accessed as a 16-bit register by word access. 8TCNT can be cleared by an input capture signal or compare match signal. Counter clear bits 1 and 0 (CCLR1 and CCLR0) in 8TCR select the method of clearing. When 8TCNT overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status register (8TCSR) is set to 1. Each 8TCNT is initialized to H'00 by a reset and in standby mode.
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10. 8-Bit Timers
10.2.2
Time Constant Registers A (TCORA)
TCORA0 Bit 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 TCORA1 4 1 3 1 2 1 1 1 0 1
Initial value Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORA2 TCORA3 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
Bit Initial value Read/Write
15 1
14 1
13 1
12 1
11 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORA0 to TCORA3 are 8-bit readable/writable registers. The TCORA0 and TCORA1 pair, and the TCORA2 and TCORA3 pair, can each be accessed as a 16-bit register by word access. The TCORA value is constantly compared with the 8TCNT value. When a match is detected, the corresponding compare match flag A (CMFA) is set to 1 in 8TCSR. The timer output can be freely controlled by these compare match signals and the settings of output select bits 1 and 0 (OS1, OS0) in 8TCSR. Each TCORA register is initialized to H'FF by a reset and in standby mode.
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10. 8-Bit Timers
10.2.3
Time Constant Registers B (TCORB)
TCORB0 Bit 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 TCORB1 4 1 3 1 2 1 1 1 0 1
Initial value Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB2 TCORB3 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
Bit Initial value Read/Write
15 1
14 1
13 1
12 1
11 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORB0 to TCORB3 are 8-bit readable/writable registers. The TCORB0 and TCORB1 pair, and the TCORB2 and TCORB3 pair, can each be accessed as a 16-bit register by word access. The TCORB value is constantly compared with the 8TCNT value. When a match is detected, the corresponding compare match flag B (CMFB) is set to 1 in 8TCSR*. The timer output can be freely controlled by these compare match signals and the settings of output/input capture edge select bits 3 and 2 (OIS3, OIS2) in 8TCSR. When TCORB is used for input capture, it stores the 8TCNT value on detection of an external input capture signal. At this time, the CMFB flag is set to 1 in the corresponding 8TCSR register. The detected edge of the input capture signal is set in 8TCSR. Each TCORB register is initialized to H'FF by a reset and in standby mode. Note: * When channel 1 and channel 3 are designated for TCORB input capture, the CMFB flag is not set by a channel 0 or channel 2 compare match B.
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10. 8-Bit Timers
10.2.4
Timer Control Register (8TCR)
Bit 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
Initial value Read/Write
8TCR is an 8-bit readable/writable register that selects the input clock source and the time at which 8TCNT is cleared, and enables interrupts. 8TCR is initialized to H'00 by a reset and in standby mode. For the timing, see section 10.4, Operation. Bit 7Compare Match Interrupt Enable B (CMIEB): Enables or disables the CMIB interrupt request when the CMFB flag is set to 1 in 8TCSR.
Bit 7 CMIEB 0 1 Description CMIB interrupt requested by CMFB is disabled CMIB interrupt requested by CMFB is enabled (Initial value)
Bit 6Compare Match Interrupt Enable A (CMIEA): Enables or disables the CMIA interrupt request when the CMFA flag is set to 1 in 8TCSR.
Bit 6 CMIEA 0 1 Description CMIA interrupt requested by CMFA is disabled CMIA interrupt requested by CMFA is enabled (Initial value)
Bit 5Timer Overflow Interrupt Enable (OVIE): Enables or disables the OVI interrupt request when the OVF flag is set to 1 in 8TCSR.
Bit 5 OVIE 0 1 Description OVI interrupt requested by OVF is disabled OVI interrupt requested by OVF is enabled (Initial value)
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10. 8-Bit Timers
Bits 4 and 3Counter Clear 1 and 0 (CCLR1, CCLR0): These bits specify the 8TCNT clearing source. Compare match A or B, or input capture B, can be selected as the clearing source.
Bit 4 CCLR1 0 Bit 3 CCLR0 0 1 1 0 1 Description Clearing is disabled Cleared by compare match A Cleared by compare match B/input capture B Cleared by input capture B (Initial value)
Note: When input capture B is set as the 8TCNT1 and 8TCNT3 counter clear source, 8TCNT0 and 8TCNT2 are not cleared by compare match B.
Bits 2 to 0Clock Select 2 to 0 (CSK2 to CSK0): These bits select whether the clock input to 8TCNT is an internal or external clock. Three internal clocks can be selected, all divided from the system clock (): /8, /64, and /8192. The rising edge of the selected internal clock triggers the count. When use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges.
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10. 8-Bit Timers
When CKS2, CKS1, CKS0 = 1, 0, 0, channels 0 and 1 and channels 2 and 3 are cascaded. The incrementing clock source is different when 8TCR0 and 8TCR2 are set, and when 8TCR1 and 8TCR3 are set.
Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 Description Clock input disabled Internal clock, counted on falling edge of /8 Internal clock, counted on falling edge of /64 Internal clock, counted on falling edge of /8192 Channel 0 (16-bit count mode): Count on 8TCNT1 overflow 1 signal* Channel 1 (compare match count mode): Count on 8TCNT0 1 compare match A* Channel 2 (16-bit count mode): Count on 8TCNT3 overflow 2 signal* Channel 3 (compare match count mode): Count on 8TCNT2 2 compare match A* 1 1 0 1 External clock, counted on rising edge External clock, counted on falling edge External clock, counted on both rising and falling edges (Initial value)
Notes: 1. If the clock input of channel 0 is the 8TCNT1 overflow signal and that of channel 1 is the 8TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. 2. If the clock input of channel 2 is the 8TCNT3 overflow signal and that of channel 3 is the 8TCNT2 compare match signal, no incrementing clock is generated. Do not use this setting.
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10. 8-Bit Timers
10.2.5 8TCSR0
Bit
Timer Control/Status Registers (8TCSR)
7 CMFB 0 R/(W)*
6 CMFA 0 R/(W)*
5 OVF 0 R/(W)*
4 ADTE 0 R/W
3 OIS3 0 R/W
2 OIS2 0 R/W
1 OS1 0 R/W
0 OS0 0 R/W
Initial value Read/Write
8TCSR2
Bit Initial value Read/Write 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 1 3 OIS3 0 R/W 2 OIS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W
8TCSR1, 8TCSR3
Bit Initial value Read/Write Note: * 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ICE 0 R/W 3 OIS3 0 R/W 2 OIS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W
Only 0 can be written to bits 7 to 5, to clear these flags.
The timer control/status registers (8TCSR) are 8-bit registers that indicate compare match/input capture and timer overflow statuses, and control compare match output/input capture edge selection. Each 8TCSR is initialized to H'00 by a reset and in standby mode.
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Bit 7Compare Match/Input Capture Flag B (CMFB): Status flag that indicates the occurrence of a TCORB compare match or input capture.
Bit 7 CMFB 0 1 Description [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB [Setting conditions] * * Note: * 8TCNT = TCORB* The 8TCNT value is transferred to TCORB by an input capture signal when TCORB functions as an input capture register (Initial value)
When bit ICE is set to 1 in 8TCSR1 and 8TCSR3, the CMFB flag is not set when 8TCNT0 = TCORB0 or 8TCNT2 = TCORB2.
Bit 6Compare Match Flag A (CMFA): Status flag that indicates the occurrence of a TCORA compare match.
Bit 6 CMFA 0 1 Description Clearing condition Read CMFA when CMFA = 1, then write 0 in CMFA Setting condition 8TCNT = TCORA (Initial value)
Bit 5Timer Overflow Flag (OVF): Status flag that indicates that the 8TCNT has overflowed (H'FF H'00).
Bit 5 OVF 0 1 Description Clearing condition Read OVF when OVF = 1, then write 0 in OVF Setting condition 8TCNT overflows from H'FF to H'00 (Initial value)
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Bit 4A/D Trigger Enable (ADTE) (8TCSR0): In combination with TRGE in the A/D control register (ADCR), enables or disables A/D converter start requests by compare match A or an external trigger. Bit 4 of 8TCSR2 is reserved, but can be read and written.
TRGE* 0 Bit 4 ADTE 0 1 1 0 1 Note: * Description A/D converter start requests by compare match A or an external trigger pin (ADTRG) input are disabled (Initial value) A/D converter start requests by compare match A or an external trigger pin (ADTRG) input are disabled A/D converter start requests by an external trigger pin (ADTRG) are enabled, and A/D converter start requests by compare match A are disabled A/D converter start requests by compare match A are enabled, and A/D converter start requests by an external trigger pin (ADTRG) are disabled
TRGE is bit 7 of the A/D control register (ADCR).
Bit 4Reserved (In 8TCSR1): This bit is a reserved bit, but can be read and written. Bit 4Input Capture Enable (ICE) (In 8TCSR1 and 8TCSR3): Selects the function of TCORB1 and TCORB3.
Bit 4 ICE 0 1 Description TCORB1 and TCORB3 are compare match registers TCORB1 and TCORB3 are input capture registers (Initial value)
When bit ICE is set to 1 in 8TCSR1 or 8TCSR3, the operation of the TCORA and TCORB registers in channels 0 to 3 is as shown in the tables below.
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Table 10.3 Operation of Channels 0 and 1 when Bit ICE is Set to 1 in 8TCSR1 Register
Register Register Function Status Flag Change Timer Output Capture Input Interrupt Request CMIA0 interrupt request generated by compare match CMIB0 interrupt request not generated by compare match CMIA1 interrupt request generated by compare match CMIB1 interrupt request generated by input capture
TCORA0 Compare match CMFA changed from 0 TMO0 output operation to 1 in 8TCSR0 by controllable compare match TCORB0 Compare match CMFB not changed operation from 0 to 1 in 8TCSR0 by compare match No output from TMO0
TCORA1 Compare match CMFA changed from 0 TMIO1 is dedicated operation to 1 in 8TCSR1 by input capture pin compare match TCORB1 Input capture operation CMFB changed from 0 TMIO1 is dedicated to 1 in 8TCSR1 by input input capture pin capture
Table 10.4 Operation of Channels 2 and 3 when Bit ICE is Set to 1 in 8TCSR3 Register
Register Register Function Status Flag Change Timer Output Capture Input Interrupt Request CMIA2 interrupt request generated by compare match CMIB2 interrupt request not generated by compare match CMIA3 interrupt request generated by compare match CMIB3 interrupt request generated by input capture
TCORA2 Compare match CMFA changed from 0 TMO2 output operation to 1 in 8TCSR2 by controllable compare match TCORB2 Compare match CMFB not changed operation from 0 to 1 in 8TCSR2 by compare match No output from TMO2
TCORA3 Compare match CMFA changed from 0 TMIO3 is dedicated operation to 1 in 8TCSR3 by input capture pin compare match TCORB3 Input capture operation CMFB changed from 0 TMIO3 is dedicated to 1 in 8TCSR3 by input input capture pin capture
Bits 3 and 2Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination with the ICE bit in 8TCSR1 (8TCSR3), these bits select the compare match B output level or the input capture input detected edge.
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The function of TCORB1 (TCORB3) depends on the setting of bit 4 of 8TCSR1 (8TCSR3). TCORB0 and TCORB2 function as compare match registers regardless of the setting of bit 4 of 8TCSR1 (8TCSR3).
ICE Bit in 8TCSR1 Bit 3 (8TCSR3) OIS3 0 0 Bit 2 OIS2 0 1 1 0 1 1 0 0 1 1 0 1
Description No change when compare match B occurs 0 is output when compare match B occurs 1 is output when compare match B occurs Output is inverted when compare match B occurs (toggle output) TCORB input capture on rising edge TCORB input capture on falling edge TCORB input capture on both rising and falling edges (Initial value)
* When the compare match register function is used, the timer output priority order is: toggle output > 1 output > 0 output. * If compare match A and B occur simultaneously, the output changes in accordance with the higher-priority compare match. * When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled. Bits 1 and 0Output Select A1 and A0 (OS1, OS0): These bits select the compare match A output level.
Bit 1 OS1 0 Bit 0 OS0 0 1 1 0 1 Description No change when compare match A occurs 0 is output when compare match A occurs 1 is output when compare match A occurs Output is inverted when compare match A occurs (toggle output) (Initial value)
* When the compare match register function is used, the timer output priority order is: toggle output > 1 output > 0 output. * If compare match A and B occur simultaneously, the output changes in accordance with the higher-priority compare match. * When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
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10. 8-Bit Timers
10.3
10.3.1
CPU Interface
8-Bit Registers
8TCNT, TCORA, TCORB, 8TCR, and 8TCSR are 8-bit registers. These registers are connected to the CPU by an internal 16-bit data bus and can be read and written a word at a time or a byte at a time. Figures 10.2 and 10.3 show the operation in word read and write accesses to 8TCNT. Figures 10.4 to 10.7 show the operation in byte read and write accesses to 8TCNT0 and 8TCNT1.
Internal data bus H C P U L Bus interface H L Module data bus
8TCNT0 8TCNT1
Figure 10.2 8TCNT Access Operation (CPU Writes to 8TCNT, Word)
Internal data bus H C P U L Bus interface H L Module data bus
8TCNT0 8TCNT1
Figure 10.3 8TCNT Access Operation (CPU Reads 8TCNT, Word)
Internal data bus H C P U L Bus interface H L Module data bus
8TCNT0 8TCNT1
Figure 10.4 8TCNTH Access Operation (CPU Writes to 8TCNTH, Upper Byte)
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Internal data bus H C P U L Bus interface H L Module data bus
8TCNT0 8TCNT1
Figure 10.5 8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte)
Internal data bus H C P U L Bus interface H L Module data bus
8TCNT0 8TCNT1
Figure 10.6 8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte)
Internal data bus H C P U L Bus interface H L Module data bus
8TCNT0 8TCNT1
Figure 10.7 8TCNT1 Access Operation (CPU Reads 8TCNT1, Lower Byte)
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10.4
10.4.1
Operation
8TCNT Count Timing
8TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (/8, /64, or /8192) divided from the system clock () can be selected by setting bits CKS2 to CKS0 in 8TCR. Figure 10.8 shows the count timing.
Internal clock
8TCNT input clock
8TCNT
N-1
N
N+1
Figure 10.8 Count Timing for Internal Clock Input Note: Even when the same internal clock is selected for both the 16- and 8-bit timers, they do not operate in the same manner because the count-up edge differs. External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in 8TCR: on the rising edge, the falling edge, and both rising and falling edges. The pulse width of the external clock signal must be at least 1.5 serial clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be counted correctly.
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Figure 10.9 shows the timing for incrementation on both edges of the external clock signal.
External clock input
8TCNT input clock
8TCNT
N-1
N
N+1
Figure 10.9 Count Timing for External Clock Input (When Detecting the Both Edges) 10.4.2 Compare Match Timing
Timer Output Timing: When compare match A or B occurs, the timer output is as specified by the OIS3, OIS2, OS1, and OS0 bits in 8TCSR (unchanged, 0 output, 1 output, or toggle output). Figure 10.10 shows the timing when the output is set to toggle on compare match A.
Compare match A signal
Timer output
Figure 10.10 Timing of Timer Output
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Clear by Compare Match: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR, 8TCNT can be cleared when compare match A or B occurs. Figure 10.11 shows the timing of this operation.
Compare match signal
8TCNT
N
H'00
Figure 10.11 Timing of Clear by Compare Match Clear by Input Capture: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR, 8TCNT can be cleared when input capture B occurs. Figure 10.12 shows the timing of this operation.
Input capture input
Input capture signal
8TCNT
N
H '00
Figure 10.12 Timing of Clear by Input Capture
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10.4.3
Input Capture Signal Timing
Input capture on the rising edge, falling edge, or both edges can be selected by settings in 8TCSR. Figure 10.13 shows the timing when the rising edge is selected. The pulse width of the input capture input signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected.
Input capture input
Input capture signal
8TCNT
N
TCORB
N
Figure 10.13 Timing of Input Capture Input Signal
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10.4.4
Timing of Status Flag Setting
Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: CMFA and CMFB in 8TCSR are set to 1 by the compare match signal output when the TCOR and 8TCNT values match. The compare match signal is generated in the last state of the match (when the matched 8TCNT count value is updated). Therefore, after the 8TCNT and TCOR values match, the compare match signal is not generated until an incrementing clock pulse is generated. Figure 10.14 shows the timing in this case.
8TCNT TCOR
N N
N+1
Compare match signal
CMF
Figure 10.14 CMF Flag Setting Timing when Compare Match Occurs Timing of CMFB Flag Setting when Input Capture Occurs: On generation of an input capture signal, the CMFB flag is set to 1 and at the same time the 8TCNT value is transferred to TCORB. Figure 10.15 shows the timing in this case.
8TCNT TCORB
N N
Input capture signal
CMFB
Figure 10.15 CMFB Flag Setting Timing when Input Capture Occurs
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Timing of Overflow Flag (OVF) Setting: The OVF flag in 8TCSR is set to 1 by the overflow signal generated when 8TCNT overflows (from H'FF to H'00). Figure 10.16 shows the timing in this case.
8TCNT
H'FF
H'00
Overflow signal
OVF
Figure 10.16 Timing of OVF Setting 10.4.5 Operation with Cascaded Connection
If bits CKS2 to CKS0 are set to (100) in either 8TCR0 or 8TCR1, the 8-bit timers of channels 0 and 1 are cascaded. With this configuration, the two timers can be used as a single 16-bit timer (16-bit count mode), or channel 0 8-bit timer compare matches can be counted in channel 1 (compare match count mode). In this case, the timer operates as below. Similarly, if bits CKS2 to CKS0 are set to (100) in either 8TCR2 or 8TCR3, the 8-bit timers of channels 2 and 3 are cascaded. With this configuration, the two timers can be used as a single 16-bit timer (16-bit count mode), or channel 2 8-bit timer compare matches can be counted in channel 3 (compare match count mode). Timer operation in these cases is described below. 16-Bit Count Mode * Channels 0 and 1: When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. Setting when Compare Match Occurs * The CMF flag is set to 1 in 8TCR0 when a 16-bit compare match occurs. * The CMF flag is set to 1 in 8TCR1 when a lower 8-bit compare match occurs. * TMO0 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR0 is in accordance with the 16-bit compare match conditions. * TMIO1 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR1 is in accordance with the lower 8-bit compare match conditions.
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Setting when Input Capture Occurs * The CMFB flag is set to 1 in 8TCR0 and 8TCR1 when the ICE bit is 1 in 8TCSR1 and input capture occurs. * TMIO1 pin input capture input signal edge detection is selected by bits OIS3 and OIS2 in 8TCSR0. Counter Clear Specification * If counter clear on compare match or input capture has been selected by the CCLR1 and CCLR0 bits in 8TCR0, the 16-bit counter (both 8TCNT0 and 8TCNT1) is cleared. * The settings of the CCLR1 and CCLR0 bits in 8TCR1 are ignored. The lower 8 bits cannot be cleared independently. OVF Flag Operation * The OVF flag is set to 1 in 8TCSR0 when the 16-bit counter (8TCNT0 and 8TCNT1) overflows (from H'FFFF to H'0000). * The OVF flag is set to 1 in 8TCSR1 when the 8-bit counter (8TCNT1) overflows (from H'FF to H'00). * Channels 2 and 3: When bits CKS2 to CKS0 are set to (100) in 8TCR2, the timer functions as a single 16-bit timer with channel 2 occupying the upper 8 bits and channel 3 occupying the lower 8 bits. Setting when Compare Match Occurs * The CMF flag is set to 1 in 8TCR2 when a 16-bit compare match occurs. * The CMF flag is set to 1 in 8TCR3 when a lower 8-bit compare match occurs. * TMO2 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR2 is in accordance with the 16-bit compare match conditions. * TMIO3 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR3 is in accordance with the lower 8-bit compare match conditions. Setting when Input Capture Occurs * The CMFB flag is set to 1 in 8TCR2 and 8TCR3 when the ICE bit is 1 in 8TCSR3 and input capture occurs. * TMIO3 pin input capture input signal edge detection is selected by bits OIS3 and OIS2 in 8TCSR2. Counter Clear Specification * If counter clear on compare match has been selected by the CCLR1 and CCLR0 bits in 8TCR2, the 16-bit counter (both 8TCNT2 and 8TCNT3) is cleared. * The settings of the CCLR1 and CCLR0 bits in 8TCR3 are ignored. The lower 8 bits cannot be cleared independently.
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OVF Flag Operation * The OVF flag is set to 1 in 8TCSR2 when the 16-bit counter (8TCNT2 and 8TCNT3) overflows (from H'FFFF to H'0000). * The OVF flag is set to 1 in 8TCSR3 when the 8-bit counter (8TCNT3) overflows (from H'FF to H'00). Compare Match Count Mode * Channels 0 and 1: When bits CKS2 to CKS0 are set to (100) in 8TCR1, 8TCNT1 counts channel 0 compare match A events. Channels 0 and 1 are controlled independently. CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in accordance with the settings for each channel. * Channels 2 and 3: When bits CKS2 to CKS0 are set to (100) in 8TCR3, 8TCNT3 counts channel 2 compare match A events. Channels 2 and 3 are controlled independently. CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in accordance with the settings for each channel. Caution: Do not set 16-bit count mode and compare match count mode simultaneously within the same group, as the 8TCNT input clock will not be generated and the counters will not operate. 10.4.6 Input Capture Setting
The 8TCNT value can be transferred to TCORB on detection of an input edge on the input capture/output compare pin (TMIO1 or TMIO3). Rising edge, falling edge, or both edge detection can be selected. In 16-bit count mode, 16-bit input capture can be used. Setting Input Capture Operation in 8-Bit Timer Mode (Normal Operation) * Channel 1: Set TCORB1 as an 8-bit input capture register with the ICE bit in 8TCSR1. Select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (TMIO1) with bits OIS3 and OIS2 in 8TCSR1. Select the input clock with bits CKS2 to CKS0 in 8TCR1, and start the 8TCNT count. * Channel 3: Set TCORB3 as an 8-bit input capture register with the ICE bit in 8TCSR3. Select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (TMIO3) with bits OIS3 and OIS2 in 8TCSR3.
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Select the input clock with bits CKS2 to CKS0 in 8TCR3, and start the 8TCNT count. Note: When TCORB1 in channel 1 is used for input capture, TCORB0 in channel 0 cannot be used as a compare match register. Similarly, when TCORB3 in channel 3 is used for input capture, TCORB2 in channel 2 cannot be used as a compare match register. Setting Input Capture Operation in 16-Bit Count Mode * Channels 0 and 1: In 16-bit count mode, TCORB0 and TCORB1 function as a 16-bit input capture register when the ICE bit is set to 1 in 8TCSR1. Select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (TMIO1) with bits OIS3 and OIS2 in 8TCSR0. (In 16-bit count mode, the settings of bits OIS3 and OIS2 in 8TCSR1 are ignored.) Select the input clock with bits CKS2 to CKS0 in 8TCR1, and start the 8TCNT count. * Channels 2 and 3: In 16-bit count mode, TCORB2 and TCORB3 function as a 16-bit input capture register when the ICE bit is set to 1 in 8TCSR3. Select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (TMIO3) with bits OIS3 and OIS2 in 8TCSR2. (In 16-bit count mode, the settings of bits OIS3 and OIS2 in 8TCSR3 are ignored.) Select the input clock with bits CKS2 to CKS0 in 8TCR3, and start the 8TCNT count.
10.5
10.5.1
Interrupt
Interrupt Source
The 8-bit timer unit can generate three types of interrupt: compare match A and B (CMIA and CMIB) and overflow (OVI). Table 10.5 shows the interrupt sources and their priority order. Each interrupt source is enabled or disabled by the corresponding interrupt enable bit in 8TCR. A separate interrupt request signal is sent to the interrupt controller by each interrupt source. Table 10.5 Types of 8-Bit Timer Interrupt Sources and Priority Order
Interrupt Source CMIA CMIB TOVI Description Interrupt by CMFA Interrupt by CMFB Interrupt by OVF Low Priority High
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For compare match interrupts CMIA1/CMIB1 and CMIA3/CMIB3 and the overflow interrupts (TOVI0/TOVI1 and TOVI2/TOVI3), one vector is shared by two interrupts. Table 10.6 lists the interrupt sources. Table 10.6 8-Bit Timer Interrupt Sources
Channel 0 Interrupt Source CMIA0 CMIB0 1 0, 1 2 CMIA1/CMIB1 TOVI0/TOVI1 CMIA2 CMIB2 3 2, 3 CMIA3/CMIB3 TOVI2/TOVI3 Description TCORA0 compare match TCORB0 compare match/input capture TCORA1 compare match, or TCORB1 compare match/input capture Counter 0 or counter 1 overflow TCORA2 compare match TCORB2 compare match/input capture TCORA3 compare match, or TCORB3 compare match/input capture Counter 2 or counter 3 overflow
10.5.2
A/D Converter Activation
The A/D converter can only be activated by channel 0 compare match A. When the CMFA flag in 8TCSR0 is set to 1 and the ADTE bit is also set to 1, activation of the A/D converter will be requested on generation of channel 0 compare match A. If the TRGE bit in ADCR is set to 1 at this time, the A/D converter will be activated. When ADTE bit in 8TCSR0 is set to 1, the A/D converter external trigger pin (ADTRG) input is disabled.
10.6
8-Bit Timer Application Example
Figure 10.17 shows how the 8-bit timer module can be used to output pulses with any desired duty cycle. The settings for this example are as follows: * Clear the CCLR1 bit to 0 and set the CCLR0 bit to 1 in 8TCR so that 8TCNT is cleared by a TCORA compare match. * Set bits OIS3, OIS2, OS1, and OS0 to (0110) in 8TCSR so that 1 is output on a TCORA compare match and 0 is output on a TCORB compare match. The above settings enable a waveform with the cycle determined by TCORA and the pulse width detected by TCORB to be output without software intervention.
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8TCNT H'FF TCORA TCORB H'00 Counter clear
TMO
Figure 10.17 Example of Pulse Output
10.7
Usage Notes
Note that the following kinds of contention can occur in 8-bit timer operation. 10.7.1 Contention between 8TCNT Write and Clear
If a timer counter clear signal occurs in the T3 state of a 8TCNT write cycle, clearing of the counter takes priority and the write is not performed. Figure 10.18 shows the timing in this case.
8TCNT write cycle T1 T2 T3
Address bus
8TCNT address
Internal write signal
Counter clear signal
8TCNT
N
H'00
Figure 10.18 Contention between 8TCNT Write and Clear
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10.7.2
Contention between 8TCNT Write and Increment
If an increment pulse occurs in the T3 state of a 8TCNT write cycle, writing takes priority and 8TCNT is not incremented. Figure 10.19 shows the timing in this case.
8TCNT write cycle T1 T2 T3
Address bus
8TCNT address
Internal write signal
8TCNT input clock
8TCNT
N 8TCNT write data
M
Figure 10.19 Contention between 8TCNT Write and Increment
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10.7.3
Contention between TCOR Write and Compare Match
If a compare match occurs in the T3 state of a TCOR write cycle, writing takes priority and the compare match signal is inhibited. Figure 10.20 shows the timing in this case.
TCOR write cycle T1 T2 T3
Address bus
TCOR address
Internal write signal
8TCNT
N
N+1
TCOR
N TCOR write data
M
Compare match signal
Inhibited
Figure 10.20 Contention between TCOR Write and Compare Match
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10.7.4
Contention between TCOR Read and Input Capture
If an input capture signal occurs in the T3 state of a TCOR read cycle, the value before input capture is read. Figure 10.21 shows the timing in this case.
TCORB read cycle T1 T2 T3
Address bus
TCORB address
Internal read signal
Input capture signal
TCORB
N
M
Internal data bus
N
Figure 10.21 Contention between TCOR Read and Input Capture
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10.7.5
Contention between Counter Clearing by Input Capture and Counter Increment
If an input capture signal and counter increment signal occur simultaneously, counter clearing by the input capture signal takes priority and the counter is not incremented. The value before the counter is cleared is transferred to TCORB. Figure 10.22 shows the timing in this case.
T1 T2 T3
Input capture signal
Counter clear signal
8TCNT internal clock
8TCNT
N
H'00
TCORB
X
N
Figure 10.22 Contention between Counter Clearing by Input Capture and Counter Increment
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10.7.6
Contention between TCOR Write and Input Capture
If an input capture signal occurs in the T3 state of a TCOR write cycle, input capture takes priority and the write to TCOR is not performed. Figure 10.23 shows the timing in this case.
TCOR write cycle T1 T2 T3
Address bus
TCOR address
Internal write signal
Input capture signal
8TCNT
M
TCOR
X
M
Figure 10.23 Contention between TCOR Write and Input Capture
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10.7.7
Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection)
If an increment pulse occurs in the T2 or T3 state of a 8TCNT byte write cycle in 16-bit count mode, writing takes priority and 8TCNT is not incremented. The byte data for which a write was not performed retains its previous value. Figure 10.24 shows the timing when an increment pulse occurs in the T2 state of a byte write to 8TCNTH.
8TCNTH byte write cycle T1 T2 T3
Address bus
8TCNTH address
Internal write signal
8TCNT input clock
8TCNTH
N
8TCNT write data
8TCNTL
X
X+1
Figure 10.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
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10.7.8
Contention between Compare Matches A and B
If compare matches A and B occur at the same time, the 8-bit timer operates according to the relative priority of the output states set for compare match A and compare match B, as shown in Table 10.5. Table 10.5 Timer Output Priority Order
Output Setting Toggle output 1 output 0 output No change Low Priority High
10.7.9
8TCNT Operation at Internal Clock Source Switchover
Switching internal clock sources may cause 8TCNT to increment, depending on the switchover timing. Table 10.6 shows the relation between the time of the switchover (by writing to bits CKS1 and CKS0) and the operation of 8TCNT. The 8TCNT input clock is generated from the internal clock source by detecting the rising edge of the internal clock. If a switchover is made from a low clock source to a high clock source, as in case No. 3 in Table 10.6, the switchover will be regarded as a falling edge, a 8TCNT clock pulse will be generated, and 8TCNT will be incremented. 8TCNT may also be incremented when switching between internal and external clocks.
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10. 8-Bit Timers
Table 10.6 Internal Clock Switchover and 8TCNT Operation
No. 1 CKS1 and CKS0 Write Timing High high switchover*
1
8TCNT Operation
Old clock source
New clock source
8TCNT clock
8TCNT
N CKS bits rewritten
N+1
2
High low switchover*
2
Old clock source
New clock source
8TCNT clock
8TCNT
N
N+1
N+2
CKS bits rewritten
3
Low high switchover*
3
Old clock source
New clock source
8TCNT clock
*4
8TCNT
N
N+1
N+2
CKS bits rewritten
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10. 8-Bit Timers No. 4 CKS1 and CKS0 Write Timing Low low switchover*
4
8TCNT Operation
Old clock source
New clock source
8TCNT clock
8TCNT
N
N+1 CKS bits rewritten
N+2
Notes: 1. Including switchovers from a high clock source to the halted state, and from the halted state to a high clock source. 2. Including switchover from the halted state to a low clock source. 3. Including switchover from a low clock source to the halted state. 4. The switchover is regarded as a rising edge, causing 8TCNT to increment.
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10. 8-Bit Timers
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11. Programmable Timing Pattern Controller (TPC)
Section 11 Programmable Timing Pattern Controller (TPC)
11.1 Overview
The H8/3006 and H8/3007 have a built-in programmable timing pattern controller (TPC) that provides pulse outputs by using the 16-bit timer as a time base. The TPC pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently. 11.1.1 Features
TPC features are listed below. * 16-bit output data Maximum 16-bit data can be output. TPC output can be enabled on a bit-by-bit basis. * Four output groups Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs. * Selectable output trigger signals Output trigger signals can be selected for each group from the compare match signals of three 16-bit timer channels. * Non-overlap mode A non-overlap margin can be provided between pulse outputs. * Can operate together with the DMA controller (DMAC) The compare-match signals selected as trigger signals can activate the DMAC for sequential output of data without CPU intervention.
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11. Programmable Timing Pattern Controller (TPC)
11.1.2
Block Diagram
Figure 11.1 shows a block diagram of the TPC.
16-bit timer compare match signals
PADDR Control logic NDERA TPMR
PBDDR NDERB TPCR
TP15 TP14 TP13 TP12 TP11 TP10 TP 9 TP 8 TP 7 TP 6 TP 5 TP 4 TP 3 TP 2 TP 1 TP 0 Legend: TPMR: TPCR: NDERB: NDERA: PBDDR: PADDR: NDRB: NDRA: PBDR: PADR:
Pulse output pins, group 3 PBDR Pulse output pins, group 2 NDRB
Internal data bus
Pulse output pins, group 1 PADR Pulse output pins, group 0 NDRA
TPC output mode register TPC output control register Next data enable register B Next data enable register A Port B data direction register Port A data direction register Next data register B Next data register A Port B data register Port A data register
Figure 11.1 TPC Block Diagram
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11. Programmable Timing Pattern Controller (TPC)
11.1.3
Pin Configuration
Table 11.1 summarizes the TPC output pins. Table 11.1 TPC Pins
Name TPC output 0 TPC output 1 TPC output 2 TPC output 3 TPC output 4 TPC output 5 TPC output 6 TPC output 7 TPC output 8 TPC output 9 TPC output 10 TPC output 11 TPC output 12 TPC output 13 TPC output 14 TPC output 15 Symbol TP0 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Group 3 pulse output Group 2 pulse output Group 1 pulse output Function Group 0 pulse output
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11. Programmable Timing Pattern Controller (TPC)
11.1.4
Register Configuration
Table 11.2 summarizes the TPC registers. Table 11.2 TPC Registers
Address* H'EE009 H'FFFD9 H'EE00A H'FFFDA H'FFFA0 H'FFFA1 H'FFFA2 H'FFFA3 H'FFFA5/ 3 H'FFFA7* H'FFFA4/ 3 H'FFFA6*
1
Name Port A data direction register Port A data register Port B data direction register Port B data register TPC output mode register TPC output control register Next data enable register B Next data enable register A Next data register A Next data register B
Abbreviation PADDR PADR PBDDR PBDR TPMR TPCR NDERB NDERA NDRA NDRB
R/W W R/(W)* W R/(W)* R/W R/W R/W R/W R/W R/W
2 2
Function H'00 H'00 H'00 H'00 H'F0 H'FF H'00 H'00 H'00 H'00
Notes: 1. Lower 20 bits of the address in advanced mode. 2. Bits used for TPC output cannot be written. 3. The NDRA address is H'FFFA5 when the same output trigger is selected for TPC output groups 0 and 1 by settings in TPCR. When the output triggers are different, the NDRA address is H'FFFA7 for group 0 and H'FFFA5 for group 1. Similarly, the address of NDRB is H'FFFA4 when the same output trigger is selected for TPC output groups 2 and 3 by settings in TPCR. When the output triggers are different, the NDRB address is H'FFFA6 for group 2 and H'FFFA4 for group 3.
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11. Programmable Timing Pattern Controller (TPC)
11.2
11.2.1
Register Descriptions
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that selects input or output for each pin in port A.
Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
PA 7 DDR PA 6 DDR PA 5 DDR PA 4 DDR PA 3 DDR PA 2 DDR PA 1 DDR PA 0 DDR
Port A data direction 7 to 0 These bits select input or output for port A pins
Port A is multiplexed with pins TP7 to TP0. Bits corresponding to pins used for TPC output must be set to 1. For further information about PADDR, see section 8.7, Port A. 11.2.2 Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when these TPC output groups are used.
Bit Initial value Read/Write 7 PA 0 R/(W) *
7
6 PA 0 R/(W) *
6
5 PA 0 R/(W) *
5
4 PA 0 R/(W) *
4
3 PA 0 R/(W) *
3
2 PA 0 R/(W) *
2
1 PA 0 R/(W) *
1
0 PA 0 R/(W) *
0
Port A data 7 to 0 These bits store output data for TPC output groups 0 and 1 Note: * Bits selected for TPC output by NDERA settings become read-only bits.
For further information about PADR, see section 8.7, Port A.
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11. Programmable Timing Pattern Controller (TPC)
11.2.3
Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register that selects input or output for each pin in port B.
Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR
Port B data direction 7 to 0 These bits select input or output for port B pins
Port B is multiplexed with pins TP15 to TP8. Bits corresponding to pins used for TPC output must be set to 1. For further information about PBDDR, see section 8.8, Port B. 11.2.4 Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when these TPC output groups are used.
Bit Initial value Read/Write 7 PB 7 0 R/(W)* 6 PB 6 0 R/(W) * 5 PB 5 0 R/(W)* 4 PB 4 0 R/(W)* 3 PB 3 0 R/(W)* 2 PB 2 0 R/(W)* 1 PB 1 0 R/(W)* 0 PB 0 0 R/(W)*
Port B data 7 to 0 These bits store output data for TPC output groups 2 and 3 Note: * Bits selected for TPC output by NDERB settings become read-only bits.
For further information about PBDR, see section 8.8, Port B.
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11. Programmable Timing Pattern Controller (TPC)
11.2.5
Next Data Register A (NDRA)
NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP7 to TP0). During TPC output, when an 16-bit timer compare match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or different output triggers. NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by the same compare match event, the NDRA address is H'FFFA5. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FFFA7 consists entirely of reserved bits that cannot be modified and always read 1. Address H'FFFA5
Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W
Next data 7 to 4 These bits store the next output data for TPC output group 1
Next data 3 to 0 These bits store the next output data for TPC output group 0
Address H'FFFA7
Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
Reserved bits
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11. Programmable Timing Pattern Controller (TPC)
Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5 and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address H'FFFA5 and bits 7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always read 1. Address H'FFFA5
Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 1 2 1 1 1 0 1
Next data 7 to 4 These bits store the next output data for TPC output group 1
Reserved bits
Address H'FFFA7
Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W
Reserved bits
Next data 3 to 0 These bits store the next output data for TPC output group 0
11.2.6
Next Data Register B (NDRB)
NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP15 to TP8). During TPC output, when an 16-bit timer compare match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The address of NDRB differs depending on whether TPC output groups 2 and 3 have the same output trigger or different output triggers. NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode.
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11. Programmable Timing Pattern Controller (TPC)
Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by the same compare match event, the NDRB address is H'FFFA4. The upper 4 bits belong to group 3 and the lower 4 bits to group 2. Address H'FFFA6 consists entirely of reserved bits that cannot be modified and always read 1. Address H'FFFA4
Bit Initial value Read/Write 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W
Next data 15 to 12 These bits store the next output data for TPC output group 3
Next data 11 to 8 These bits store the next output data for TPC output group 2
Address H'FFFA6
Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
Reserved bits
Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFFA4 and the address of the lower 4 bits (group 2) is H'FFFA6. Bits 3 to 0 of address H'FFFA4 and bits 7 to 4 of address H'FFFA6 are reserved bits that cannot be modified and always read 1. Address H'FFFA4
Bit Initial value Read/Write 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 1 2 1 1 1 0 1
Next data 15 to 12 These bits store the next output data for TPC output group 3
Reserved bits
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11. Programmable Timing Pattern Controller (TPC)
Address H'FFFA6
Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W
Reserved bits
Next data 11 to 8 These bits store the next output data for TPC output group 2
11.2.7
Next Data Enable Register A (NDERA)
NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis.
Bit Initial value Read/Write 7 NDER7 0 R/W 6 NDER6 0 R/W 5 NDER5 0 R/W 4 NDER4 0 R/W 3 NDER3 0 R/W 2 NDER2 0 R/W 1 NDER1 0 R/W 0 NDER0 0 R/W
Next data enable 7 to 0 These bits enable or disable TPC output groups 1 and 0
If a bit is enabled for TPC output by NDERA, then when the 16-bit timer compare match event selected in the TPC output control register (TPCR) occurs, the NDRA value is automatically transferred to the corresponding PADR bit, updating the output value. If TPC output is disabled, the bit value is not transferred from NDRA to PADR and the output value does not change. NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis.
Bits 7 to 0 NDER7 to NDER0 0 1 Description TPC outputs TP7 to TP0 are disabled (NDR7 to NDR0 are not transferred to PA7 to PA0) TPC outputs TP7 to TP0 are enabled (NDR7 to NDR0 are transferred to PA7 to PA0) (Initial value)
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11. Programmable Timing Pattern Controller (TPC)
11.2.8
Next Data Enable Register B (NDERB)
NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis.
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 NDER8 0 R/W
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9
Next data enable 15 to 8 These bits enable or disable TPC output groups 3 and 2
If a bit is enabled for TPC output by NDERB, then when the 16-bit timer compare match event selected in the TPC output control register (TPCR) occurs, the NDRB value is automatically transferred to the corresponding PBDR bit, updating the output value. If TPC output is disabled, the bit value is not transferred from NDRB to PBDR and the output value does not change. NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis.
Bits 7 to 0 NDER15 to NDER8 0 1 Description TPC outputs TP15 to TP8 are disabled (NDR15 to NDR8 are not transferred to PB7 to PB0) TPC outputs TP15 to TP8 are enabled (NDR15 to NDR8 are transferred to PB7 to PB0) (Initial value)
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11. Programmable Timing Pattern Controller (TPC)
11.2.9
TPC Output Control Register (TPCR)
TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis.
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
Group 3 compare match select 1 and 0 These bits select the compare match Group 2 compare event that triggers match select 1 and 0 TPC output group 3 These bits select (TP15 to TP12 ) the compare match Group 1 compare event that triggers match select 1 and 0 TPC output group 2 These bits select (TP11 to TP 8 ) the compare match Group 0 compare event that triggers match select 1 and 0 TPC output group 1 These bits select (TP7 to TP4 ) the compare match event that triggers TPC output group 0 (TP3 to TP0 )
TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 and 6Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match event that triggers TPC output group 3 (TP15 to TP12).
Bit 7 G3CMS1 0 Bit 6 G3CMS0 0 1 1 0 1 Description TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 0 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 1 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 2 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 2 (Initial value)
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11. Programmable Timing Pattern Controller (TPC)
Bits 5 and 4Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match event that triggers TPC output group 2 (TP11 to TP8).
Bit 5 G2CMS1 0 Bit 4 G2CMS0 0 1 1 0 1 Description TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 0 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 1 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 2 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 2 (Initial value)
Bits 3 and 2Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match event that triggers TPC output group 1 (TP7 to TP4).
Bit 3 G1CMS1 0 Bit 2 G1CMS0 0 1 1 0 1 Description TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 0 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 1 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 2 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 2 (Initial value)
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11. Programmable Timing Pattern Controller (TPC)
Bits 1 and 0Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits select the compare match event that triggers TPC output group 0 (TP3 to TP0).
Bit 1 G0CMS1 0 Bit 0 G0CMS0 0 1 1 0 1 Description TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 0 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 1 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 2 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 2 (Initial value)
11.2.10 TPC Output Mode Register (TPMR) TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group.
Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
G3NOV G2NOV
G1NOV G0NOV
Reserved bits Group 3 non-overlap Selects non-overlapping TPC output for group 3 (TP15 to TP12) Group 2 non-overlap Selects non-overlapping TPC output for group 2 (TP11 to TP8 ) Group 1 non-overlap Selects non-overlapping TPC output for group 1 (TP7 to TP4 ) Group 0 non-overlap Selects non-overlapping TPC output for group 0 (TP3 to TP0 )
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11. Programmable Timing Pattern Controller (TPC)
The output trigger period of a non-overlapping TPC output waveform is set in general register B (GRB) in the 16-bit timer channel selected for output triggering. The non-overlap margin is set in general register A (GRA). The output values change at compare match A and B. For details see section 11.3.4, Non-Overlapping TPC Output. TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 4Reserved: These bits cannot be modified and are always read as 1. Bit 3Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP15 to TP12).
Bit 3 G3NOV 0 1 Description Normal TPC output in group 3 (output values change at compare match A in the selected 16-bit timer channel) Non-overlapping TPC output in group 3 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel) (Initial value)
Bit 2Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for group 2 (TP11 to TP8).
Bit 2 G2NOV 0 1 Description Normal TPC output in group 2 (output values change at compare match A in the selected 16-bit timer channel) Non-overlapping TPC output in group 2 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel) (Initial value)
Bit 1Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping TPC output for group 1 (TP7 to TP4).
Bit 1 G1NOV 0 1 Description Normal TPC output in group 1 (output values change at compare match A in the selected 16-bit timer channel) Non-overlapping TPC output in group 1 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel) (Initial value)
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11. Programmable Timing Pattern Controller (TPC)
Bit 0Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for group 0 (TP3 to TP0).
Bit 0 G0NOV 0 1 Description Normal TPC output in group 0 (output values change at compare match A in the selected 16-bit timer channel) Non-overlapping TPC output in group 0 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel) (Initial value)
11.3
11.3.1
Operation
Overview
When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents. When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit contents are transferred to PADR or PBDR to update the output values. Figure 11.2 illustrates the TPC output operation. Table 11.3 summarizes the TPC operating conditions.
DDR Q
NDER Q Output trigger signal
C Q TPC output pin DR D Q NDR D Internal data bus
Figure 11.2 TPC Output Operation
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11. Programmable Timing Pattern Controller (TPC)
Table 11.3 TPC Operating Conditions
NDER 0 DDR 0 1 1 0 1 Pin Function Generic input port Generic output port Generic input port (but the DR bit is a read-only bit, and when compare match occurs, the NDR bit value is transferred to the DR bit) TPC pulse output
Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and NDRB before the next compare match. For information on non-overlapping operation, see section 11.3.4, Non-Overlapping TPC Output. 11.3.2 Output Timing
If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when the selected compare match event occurs. Figure 11.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A.
16TCNT
N
N+1
GRA Compare match A signal
N
NDRB
n
PBDR TP8 to TP15
m m
n n
Figure 11.3 Timing of Transfer of Next Data Register Contents and Output (Example)
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11. Programmable Timing Pattern Controller (TPC)
11.3.3
Normal TPC Output
Sample Setup Procedure for Normal TPC Output: Figure 11.4 shows a sample procedure for setting up normal TPC output.
Normal TPC output
Select GR functions Set GRA value Select counting operation Select interrupt request
1 2 3 4
1.
16-bit timer setup
Set initial output data Select port output Port and TPC setup Enable TPC output Select TPC output trigger Set next TPC output data 16-bit timer setup
5 6 7 8 9
Start counter
10
Set TIOR to make GRA an output compare register (with output inhibited). 2. Set the TPC output trigger period. 3. Select the counter clock source with bits TPSC2 to TPSC0 in 16TCR. Select the counter clear source with bits CCLR1 and CCLR0. 4. Enable the IMFA interrupt in TISRA. The DMAC can also be set up to transfer data to the next data register. 5. Set the initial output values in the DR bits of the input/output port pins to be used for TPC output. 6. Set the DDR bits of the input/output port pins to be used for TPC output to 1. 7. Set the NDER bits of the pins to be used for TPC output to 1. 8. Select the 16-bit timer compare match event to be used as the TPC output trigger in TPCR. 9. Set the next TPC output values in the NDR bits. 10. Set the STR bit to 1 in TSTR to start the timer counter. 11. At each IMFA interrupt, set the next output values in the NDR bits.
Compare match? Yes Set next TPC output data
No
11
Figure 11.4 Setup Procedure for Normal TPC Output (Example)
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11. Programmable Timing Pattern Controller (TPC)
Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 11.5 shows an example in which the TPC is used for cyclic five-phase pulse output.
TCNT value TCNT GRA Compare match
H'0000 NDRB 80 C0 40 60 20 30 10 18 08 88 80 C0 40
Time
PBDR
00
80
C0
40
60
20
30
10
18
08
88
80
C0
TP15
TP14 TP13 TP12
TP11
* * * *
The 16-bit timer channel to be used as the output trigger channel is set up so that GRA is an output compare register and the counter will be cleared by compare match A. The trigger period is set in GRA. The IMIEA bit is set to 1 in TISRA to enable the compare match A interrupt. H'F8 is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger. Output data H'80 is written in NDRB. The timer counter in this 16-bit timer channel is started. When compare match A occurs, the NDRB contents are transferred to PBDR and output. The compare match/input capture A (IMFA) interrupt service routine writes the next output data (H'C0) in NDRB. Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88E at successive IMFA interrupts. If the DMAC is set for activation by this interrupt, pulse output can be obtained without loading the CPU.
Figure 11.5 Normal TPC Output Example (Five-Phase Pulse Output)
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11. Programmable Timing Pattern Controller (TPC)
11.3.4
Non-Overlapping TPC Output
Sample Setup Procedure for Non-Overlapping TPC Output: Figure 11.6 shows a sample procedure for setting up non-overlapping TPC output.
Non-overlapping TPC output Select GR functions Set GR values Select counting operation Select interrupt requests 1 2 3 4 1. Set TIOR to make GRA and GRB output compare registers (with output inhibited). 2. Set the TPC output trigger period in GRB and the non-overlap margin in GRA. 3. Select the counter clock source with bits TPSC2 to TPSC0 in 16TCR. Select the counter clear source with bits CCLR1 and CCLR0. 4. Enable the IMFA interrupt in TISRA. The DMAC can also be set up to transfer data to the next data register. 5. Set the initial output values in the DR bits of the input/output port pins to be used for TPC output. 6. Set the DDR bits of the input/output port pins to be used for TPC output to 1. 7. Set the NDER bits of the pins to be used for TPC output to 1. 8. In TPCR, select the 16-bit timer compare match event to be used as the TPC output trigger. 9. In TPMR, select the groups that will operate in non-overlap mode. 10. Set the next TPC output values in the NDR bits. 11. Set the STR bit to 1 in TSTR to start the timer counter. 12. At each IMFA interrupt, write the next output value in the NDR bits.
16-bit timer setup
Set initial output data Set up TPC output Enable TPC transfer Port and TPC setup Select TPC transfer trigger Select non-overlapping groups Set next TPC output data
5 6 7 8 9 10
16-bit timer setup
Start counter
11
Compare match A? Yes Set next TPC output data
No
12
Figure 11.6 Setup Procedure for Non-Overlapping TPC Output (Example)
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11. Programmable Timing Pattern Controller (TPC)
Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary NonOverlapping Output): Figure 11.7 shows an example of the use of TPC output for four-phase complementary non-overlapping pulse output.
16TCNT value GRB GRA H'0000 NDRB 95 65 59 56 95 65 Time 16TCNT
PBDR
00
95
05
65
41
59
50
56
14
95
05
65
Non-overlap margin TP15
TP14 TP13 TP12
TP11 TP10 TP9 TP8 * The 16-bit timer channel to be used as the output trigger channel is set up so that GRA and GRB are output compare registers and the counter will be cleared by compare match B. The TPC output trigger period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TISRA to enable IMFA interrupts. * H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger. Bits G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is written in NDRB. * The timer counter in this 16-bit timer channel is started. When compare match B occurs, outputs change from 1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB. * Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95... at successive IMFA interrupts. If the DMAC is set for activation by this interrupt, pulse output can be obtained without loading the CPU.
Figure 11.7 Non-Overlapping TPC Output Example (Four-Phase Complementary Non-Overlapping Pulse Output)
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11. Programmable Timing Pattern Controller (TPC)
11.3.5
TPC Output Triggering by Input Capture
TPC output can be triggered by 16-bit timer input capture as well as by compare match. If GRA functions as an input capture register in the 16-bit timer channel selected in TPCR, TPC output will be triggered by the input capture signal. Figure 11.8 shows the timing.
TIOC pin Input capture signal NDR N
DR
M
N
Figure 11.8 TPC Output Triggering by Input Capture (Example)
11.4
11.4.1
Usage Notes
Operation of TPC Output Pins
TP0 to TP15 are multiplexed with 16-bit timer, DMAC, address bus, and other pin functions. When 16-bit timer, DMAC, or address output is enabled, the corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin. Pin functions should be changed only under conditions in which the output trigger event will not occur.
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11. Programmable Timing Pattern Controller (TPC)
11.4.2
Note on Non-Overlapping Output
During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as follows. 1. NDR bits are always transferred to DR bits at compare match A. 2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 11.9 illustrates the non-overlapping TPC output operation.
DDR Q
NDER Q Compare match A Compare match B
C Q TPC output pin DR D Q NDR D
Figure 11.9 Non-Overlapping TPC Output Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the IMFA interrupt service routine write the next data in NDR, or by having the IMFA interrupt activate the DMAC. The next data must be written before the next compare match B occurs. Figure 11.10 shows the timing relationships.
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11. Programmable Timing Pattern Controller (TPC)
Compare match A Compare match B NDR write NDR write
NDR
DR 0 output 0/1 output Write to NDR in this interval Do not write to NDR in this interval Do not write to NDR in this interval 0 output 0/1 output Write to NDR in this interval
Figure 11.10 Non-Overlapping Operation and NDR Write Timing
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12. Watchdog Timer
Section 12 Watchdog Timer
12.1 Overview
The H8/3006 and H8/3007 have an on-chip watchdog timer (WDT). The WDT has two selectable functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an interval timer. As a watchdog timer, it generates a reset signal for the H8/3006 and H8/3007 chip if a system crash allows the timer counter (TCNT) to overflow before being rewritten. In interval timer operation, an interval timer interrupt is requested at each TCNT overflow. 12.1.1 Features
WDT features are listed below. * Selection of eight counter clock sources /2, /32, /64, /128, /256, /512, /2048, or /4096 * Interval timer option * Timer counter overflow generates a reset signal or interrupt. The reset signal is generated in watchdog timer operation. An interval timer interrupt is generated in interval timer operation. * Watchdog timer reset signal resets the entire H8/3006 and H8/3007 internally, and can also be output externally. The reset signal generated by timer counter overflow during watchdog timer operation resets the entire H8/3006 and H8/3007 internally. An external reset signal can be output from the RESO pin to reset other system devices simultaneously.
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12. Watchdog Timer
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the WDT.
Overflow TCNT Interrupt signal (interval timer) Interrupt control TCSR Read/ write control Internal data bus
RSTCSR
Internal clock sources /2 /32 /64 Clock Clock selector /128 /256 /512 /2048 /4096
Reset (internal, external)
Reset control
Legend: TCNT: Timer counter TCSR: Timer control/status register RSTCSR: Reset control/status register
Figure 12.1 WDT Block Diagram 12.1.3 Pin Configuration
Table 12.1 describes the WDT output pin. Table 12.1 WDT Pin
Name Reset output Note: * Abbreviation RESO I/O Output* Function External output of the watchdog timer reset signal
Open-drain output.
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12. Watchdog Timer
12.1.4
Register Configuration
Table 12.2 summarizes the WDT registers. Table 12.2 WDT Registers
Address* Write*
2 1
Read
Name
Abbreviation TCSR TCNT RSTCSR
R/W R/(W)* R/W R/(W)*
3 3
Initial Value H'18 H'00 H'3F
H'FFF8C H'FFF8C Timer control/status register H'FFF8D Timer counter H'FFF8E H'FFF8F Reset control/status register
Notes: 1. Lower 20 bits of the address in advanced mode. 2. Write word data starting at this address. 3. Only 0 can be written in bit 7, to clear the flag.
12.2
12.2.1
Register Descriptions
Timer Counter (TCNT)
TCNT is an 8-bit readable and writable up-counter.
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Note: TCNT is write-protected by a password. For details see section 12.2.4, Notes on Register Access.
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), the OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0.
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12. Watchdog Timer
12.2.2
Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and clock source.
Bit Initial value Read/Write 7 OVF 0 R/(W) * 6 WT/IT 0 R/W 5 TME 0 R/W 4 1 3 1 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
Clock select These bits select the TCNT clock source Reserved bits Timer enable Selects whether TCNT runs or halts Timer mode select Selects the mode Overflow flag Status flag indicating overflow Notes: TCSR is write-protected by a password. For details see section 12.2.4, Notes on Register Access. * Only 0 can be written, to clear the flag.
Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values. Bit 7Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed from H'FF to H'00.
Bit 7 OVF 0 1 Description [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 in OVF [Setting condition] Set when TCNT changes from H'FF to H'00 Rev.5.00 Sep. 12, 2007 Page 416 of 764 REJ09B0396-0500 (Initial value)
12. Watchdog Timer
Bit 6Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when TCNT overflows.
Bit 6 WT/IT 0 1 Description Interval timer: requests interval timer interrupts Watchdog timer: generates a reset signal (Initial value)
Bit 5Timer Enable (TME): Selects whether TCNT runs or is halted. When WT/IT = 1, clear the software standby bit (SSBY) to 0 in SYSCR before setting TME. When setting SSBY to 1, TME should be cleared to 0.
Bit 5 TME 0 1 Description TCNT is initialized to H'00 and halted TCNT is counting (Initial value)
Bits 4 and 3Reserved: These bits cannot be modified and are always read as 1. Bits 2 to 0Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources, obtained by prescaling the system clock (), for input to TCNT.
Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Description /2 /32 /64 /128 /256 /512 /2048 /4096 (Initial value)
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12. Watchdog Timer
12.2.3
Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been generated by watchdog timer overflow, and controls external output of the reset signal.
Bit Initial value Read/Write 7 WRST 0 R/(W)* 6 RSTOE 0 R/W 5 1 4 1 3 1 2 1 1 1 0 1
Reserved bits Reset output enable Enables or disables external output of the reset signal Watchdog timer reset Indicates that a reset signal has been generated Notes: RSTCSR is write-protected by a password. For details see section 12.2.4, Notes on Register Access. * Only 0 can be written in bit 7, to clear the flag.
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by reset signals generated by watchdog timer overflow. Bit 7Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3006 and H8/3007 chip internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to initialize external system devices.
Bit 7 WRST 0 Description [Clearing condition] Reset signal at RES pin. Read WRST when WRST =1, then write 0 in WRST. 1 [Setting condition] Set when TCNT overflow generates a reset signal during watchdog timer operation (Initial value)
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12. Watchdog Timer
Bit 6Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of the reset signal generated if TCNT overflows during watchdog timer operation.
Bit 6 RSTOE Description 0 1 Reset signal is not output externally Reset signal is output externally (Initial value)
Bits 5 to 0Reserved: These bits cannot be modified and are always read as 1. 12.2.4 Notes on Register Access
The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte instructions. Figure 12.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must contain H'5A (password for TCNT) or H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT or TCSR.
TCNT write Address H'FFF8C * 15 H'5A 87 Write data 0
TCSR write Address H'FFF8C *
15 H'A5
87 Write data
0
Note: * Lower 20 bits of the address in advanced mode.
Figure 12.2 Format of Data Written to TCNT and TCSR Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be written by byte transfer instructions. Figure 12.3 shows the format of data written to RSTCSR. To write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte. The data (H'00) in the lower byte is written to RSTCSR, clearing the WRST bit to 0. To write to the RSTOE bit, the upper byte must contain H'5A and the lower byte must contain the write data. Writing this word transfers a write data value into the RSTOE bit.
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12. Watchdog Timer
Writing 0 in WRST bit Address H'FFF8E* 15 H'A5 87 H'00 0
Writing to RSTOE bit Address H'FFF8E*
15 H'5A
87 Write data
0
Note: * Lower 20 bits of the address in advanced mode.
Figure 12.3 Format of Data Written to RSTCSR Reading TCNT, TCSR, and RSTCSR: For reads of TCNT, TCSR, and RSTCSR, address H'FFF8C is assigned to TCSR, address H'FFF8D to TCNT, and address H'FFF8F to RSTCSR. These registers are therefore read like other registers. Byte transfer instructions can be used for reading. Table 12.3 lists the read addresses of TCNT, TCSR, and RSTCSR. Table 12.3 Read Addresses of TCNT, TCSR, and RSTCSR
Address* H'FFF8C H'FFF8D H'FFF8F Note: * Register TCSR TCNT RSTCSR Lower 20 bits of the address in advanced mode.
12.3
Operation
Operations when the WDT is used as a watchdog timer and as an interval timer are described below. 12.3.1 Watchdog Timer Operation
Figure 12.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and overflows due to a system crash etc., the H8/3006 and H8/3007 are internally reset for a duration of 518 states. The watchdog reset signal can be externally output from the RESO pin to reset external system devices. The reset signal is output externally for 132 states. External output can be enabled or disabled by the RSTOE bit in RSTCSR.
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12. Watchdog Timer
A watchdog reset has the same vector as a reset generated by input at the RES pin. Software can distinguish a RES reset from a watchdog reset by checking the WRST bit in RSTCSR. If a RES reset and a watchdog reset occur simultaneously, the RES reset takes priority.
WDT overflow
H'FF TCNT count value H'00
TME set to 1
OVF = 1 Start Internal reset signal H'00 written in TCNT Reset H'00 written in TCNT
518 states RESO
132 states
Figure 12.4 Operation in Watchdog Timer Mode
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12. Watchdog Timer
12.3.2
Interval Timer Operation
Figure 12.5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each TCNT overflow. This function can be used to generate interval timer interrupts at regular intervals.
H'FF
TCNT count value Time t H'00 WT/ IT = 0 TME = 1
Interval timer interrupt
Interval timer interrupt
Interval timer interrupt
Interval timer interrupt
Figure 12.5 Interval Timer Operation 12.3.3 Timing of Setting of Overflow Flag (OVF)
Figure 12.6 shows the timing of setting of the OVF flag. The OVF flag is set to 1 when TCNT overflows. At the same time, a reset signal is generated in watchdog timer operation, or an interval timer interrupt is generated in interval timer operation.
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 12.6 Timing of Setting of OVF
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12. Watchdog Timer
12.3.4
Timing of Setting of Watchdog Timer Reset Bit (WRST)
The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR. Figure 12.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is generated for the entire H8/3006 and H8/3007 chip. This internal reset signal clears OVF to 0, but the WRST bit remains set to 1. The reset routine must therefore clear the WRST bit.
TCNT
H'FF
H'00
Overflow signal
OVF
WDT internal reset
WRST
Figure 12.7 Timing of Setting of WRST Bit and Internal Reset
12.4
Interrupts
During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR.
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12. Watchdog Timer
12.5
Usage Notes
Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer count is not incremented. See figure 12.8.
CPU: TCNT write cycle T1 T2 T3
TCNT
Internal write signal
TCNT input clock
TCNT
N
M Counter write data
Figure 12.8 Contention between TCNT Write and Count up Changing CKS2 to CKS0 Bit: Halt TCNT by clearing the TME bit to 0 in TCSR before changing the values of bits CKS2 to CKS0.
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13. Serial Communication Interface
Section 13 Serial Communication Interface
13.1 Overview
The H8/3006 and H8/3007 have a serial communication interface (SCI) with three independent channels. All three channels have identical functions. The SCI can communicate in both asynchronous and synchronous mode. It also has a multiprocessor communication function for serial communication among two or more processors. When the SCI is not used, it can be halted to conserve power. Each SCI channel can be halted independently. For details, see section 19.6, Module Standby Function. The SCI also has a smart card interface function conforming to the ISO/IEC 7816-3 (Identification Card) standard. This function supports serial communication with a smart card. Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 13.1.1 Features
SCI features are listed below. * Selection of synchronous or asynchronous mode for serial communication Asynchronous mode Serial data communication is synchronized one channel at a time. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), asynchronous communication interface adapter (ACIA), or other chip that employs standard asynchronous communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data transfer formats. Data length: Stop bit length: Parity: Multiprocessor bit: Break detection: 7 or 8 bits 1 or 2 bits even/odd/none 1 or 0 by reading the RxD level directly when a framing error occurs
Receive error detection: parity, overrun, and framing errors
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13. Serial Communication Interface
Synchronous mode Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a synchronous communication function. There is a single serial data communication format. Data length: * Full-duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. The transmitting and receiving sections are both double-buffered, so serial data can be transmitted and received continuously. * The following settings can be made for the serial data to be transferred: LSB-first or MSB-first transfer Inversion of data logic level * Built-in baud rate generator with selectable bit rates * Selectable transmit/receive clock sources: internal clock from baud rate generator, or external clock from the SCK pin * Four types of interrupts Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested independently. The transmit-data-empty and receive-data-full interrupts from SCI0 can activate the DMA controller (DMAC) to transfer data. Features of the smart card interface are listed below. * Asynchronous communication Data length: 8 bits Parity bits generated and checked Error signal output in receive mode (parity error) Error signal detect and automatic data retransmit in transmit mode Supports both direct convention and inverse convention * Built-in baud rate generator with selectable bit rates * Three types of interrupts Transmit-data-empty, receive-data-full, and transmit/receive-error interrupts are requested independently. The transmit-data-empty and receive-data-full interrupts can activate the DMA controller (DMAC) to transfer data. 8 bits Receive error detection: overrun errors
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13. Serial Communication Interface
13.1.2
Block Diagram
Figure 13.1 shows a block diagram of the SCI.
Module data bus
Bus interface
Internal data bus
RDR
TDR
SSR SCR SMR SCMR
Transmit/receive control
BRR Baud rate generator / 4 /16 /64
RxD
RSR
TSR
TxD
Parity generate Parity check
Clock External clock TEI TXI RXI ERI
SCK
Legend: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register SCMR: Smart card mode register
Figure 13.1 SCI Block Diagram
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13. Serial Communication Interface
13.1.3
Pin Configuration
The SCI has serial pins for each channel as listed in table 13.1. Table 13.1 SCI Pins
Channel Name 0 Serial clock pin Receive data pin Transmit data pin 1 Serial clock pin Receive data pin Transmit data pin 2 Serial clock pin Receive data pin Transmit data pin Abbreviation SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 I/O Input/output Input Output Input/output Input Output Input/output Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output
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13. Serial Communication Interface
13.1.4
Register Configuration
The SCI has internal registers as listed in table 13.2. These registers select asynchronous or synchronous mode, specify the data format and bit rate, control the transmitter and receiver sections, and specify switching between the serial communication interface and smart card interface. Table 13.2 SCI Registers
Channel 0 Address* H'FFFB0 H'FFFB1 H'FFFB2 H'FFFB3 H'FFFB4 H'FFFB5 H'FFFB6 1 H'FFFB8 H'FFFB9 H'FFFBA H'FFFBB H'FFFBC H'FFFBD H'FFFBE 2 H'FFFC0 H'FFFC1 H'FFFC2 H'FFFC3 H'FFFC4 H'FFFC5 H'FFFC6
1
Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register
Abbreviation SMR BRR SCR TDR SSR RDR SCMR SMR BRR SCR TDR SSR RDR SCMR SMR BRR SCR TDR SSR RDR SCMR
R/W R/W R/W R/W R/W
2
Initial Value H'00 H'FF H'00 H'FF
R/(W)* H'84 R R/W R/W R/W R/W R/W
2
H'00 H'F2 H'00 H'FF H'00 H'FF
R/(W)* H'84 R R/W R/W R/W R/W R/W
2
H'00 H'F2 H'00 H'FF H'00 H'FF
R/(W)* H'84 R R/W H'00 H'F2
Notes: 1. Indicates the lower 20 bits of the address in advanced mode. 2. Only 0 can be written, to clear flags.
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13. Serial Communication Interface
13.2
13.2.1
Register Descriptions
Receive Shift Register (RSR)
RSR is the register that receives serial data.
Bit
7
6
5
4
3
2
1
0
Read/Write

The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first, thereby converting the data to parallel data. When one byte of data has been received, it is automatically transferred to RDR. The CPU cannot read or write RSR directly. 13.2.2 Receive Data Register (RDR)
RDR is the register that stores received serial data.
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
When the SCI has received one byte of serial data, it transfers the received data from RSR into RDR for storage, completing the receive operation. RSR is then ready to receive the next data. This double-buffering allows data to be received continuously. RDR is a read-only register. Its contents cannot be modified by the CPU. RDR is initialized to H'00 by a reset and in standby mode.
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13. Serial Communication Interface
13.2.3
Transmit Shift Register (TSR)
TSR is the register that transmits serial data.
Bit 7 6 5 4 3 2 1 0
Read/Write

The SCI loads transmit data from TDR to TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from TDR into TSR and starts transmitting it. If the TDRE flag is set to 1 in SSR, however, the SCI does not load the TDR contents into TSR. The CPU cannot read or write TSR directly. 13.2.4 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for serial transmission.
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
When the SCI detects that TSR is empty, it moves transmit data written in TDR from TDR into TSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in TDR during serial transmission from TSR. The CPU can always read and write TDR. TDR is initialized to H'FF by a reset and in standby mode.
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13. Serial Communication Interface
13.2.5
Serial Mode Register (SMR)
SMR is an 8-bit register that specifies the SCI's serial communication format and selects the clock source for the baud rate generator.
Bit 7 C/A Initial value Read/Write 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Clock select 1/0 These bits select the baud rate generator's clock source Multiprocessor mode Selects the multiprocessor function
Stop bit length Selects the stop bit length
Parity mode Selects even or odd parity
Parity enable Selects whether a parity bit is added
Character length Selects character length in asynchronous mode Communication mode Selects asynchronous or synchronous mode
The CPU can always read and write SMR. SMR is initialized to H'00 by a reset and in standby mode.
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13. Serial Communication Interface
Bit 7Communication Mode (C/A)/GSM Mode (GM): The function of this bit differs for the normal serial communication interface and for the smart card interface. Its function is switched with the SMIF bit in SCMR. For serial communication interface (SMIF bit in SCMR cleared to 0): Selects whether the SCI operates in asynchronous or synchronous mode.
Bit 7 C/A 0 1 Description Asynchronous mode Synchronous mode (Initial value)
For smart card interface (SMIF bit in SCMR set to 1): Selects GSM mode for the smart card interface.
Bit 7 GM 0 1 Description The TEND flag is set 12.5 etu after the start bit The TEND flag is set 11.0 etu after the start bit (Initial value)
Note: etu: Elementary time unit (time required to transmit one bit)
Bit 6Character Length (CHR): Selects 7-bit or 8-bits data length in asynchronous mode. In synchronous mode, the data length is 8 bits regardless of the CHR setting,
Bit 6 CHR 0 1 Note: * Description 8-bit data 7-bit data* When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. (Initial value)
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13. Serial Communication Interface
Bit 5Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous mode, the parity bit is neither added nor checked, regardless of the PE bit setting.
Bit 5 PE 0 1 Note: * Description Parity bit not added or checked Parity bit added and checked* When PE bit is set to 1, an even or odd parity bit is added to transmit data according to the even or odd parity mode selection by the O/E bit, and the parity bit in receive data is checked to see that it matches the even or odd mode selected by the O/E bit. (Initial value)
Bit 4Parity Mode (O/E): Selects even or odd parity. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is ignored in synchronous mode, or when parity addition and checking is disabled in asynchronous mode.
Bit 4 O/E 0 1 Description Even parity* Odd parity*
2 1
(Initial value)
Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. Receive data must have an even number of 1s in the received character and parity bit combined. 2. When odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. Receive data must have an odd number of 1s in the received character and parity bit combined.
Bit 3Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This setting is used only in asynchronous mode. In synchronous mod no stop bit is added, so the STOP bit setting is ignored.
Bit 3 STOP 0 1 Description 1 stop bit*
1 2
(Initial value)
2 stop bits*
Notes: 1. One stop bit (with value 1) is added to the end of each transmitted character. 2. Two stop bits (with value 1) are added to the end of each transmitted character.
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13. Serial Communication Interface
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit. If the second stop bit is 0, it is treated as the start bit of the next incoming character. Bit 2Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is valid only in asynchronous mode. It is ignored in synchronous mode. For further information on the multiprocessor communication function, see section 13.3.3, Multiprocessor Communication.
Bit 2 MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value)
Bits 1 and 0Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the onchip baud rate generator. Four clock sources are available: , /4, /16, and /64. For the relationship between the clock source, bit rate register setting, and baud rate, see section 13.2.8, Bit Rate Register (BRR).
Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1 Description /4 /16 /64 (Initial value)
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13. Serial Communication Interface
13.2.6
Serial Control Register (SCR)
SCR register enables or disables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source.
Bit 7 TIE Initial value Read/Write 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Clock enable 1/0 These bits select the SCI clock source
Transmit-end interrupt enable Enables or disables transmit-end interrupts (TEI)
Multiprocessor interrupt enable Enables or disables multiprocessor interrupts
Receive enable Enables or disables the receiver Transmit enable Enables or disables the transmitter Receive interrupt enable Enables or disables receive-data-full interrupts (RXI) and receive-error interrupts (ERI) Transmit interrupt enable Enables or disables transmit-data-empty interrupts (TXI)
The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby mode.
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Bit 7Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from TDR to TSR.
Bit 7 TIE 0 1 Note: * Description Transmit-data-empty interrupt request (TXI) is disabled* Transmit-data-empty interrupt request (TXI) is enabled TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then clearing it to 0; or by clearing the TIE bit to 0. (Initial value)
Bit 6Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI) requested when the RDRF flag in SSR is set to 1 due to transfer of serial receive data from RSR to RDR; also enables or disables the receive-error interrupt (ERI).
Bit 6 RIE 0 1 Note: * Description Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled* (Initial value) Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled RXI and ERI interrupt requests can be cleared by reading the value 1 from the RDRF, FER, PER, or ORER flag, then clearing the flag to 0; or by clearing the RIE bit to 0.
Bit 5Transmit Enable (TE): Enables or disables the start of SCI serial transmitting operations.
Bit 5 TE 0 1 Description Transmitting disabled* Transmitting enabled*
1
(Initial value)
2
Notes: 1. The TDRE flag is fixed at 1 in SSR. 2. In the enabled state, serial transmission starts when the TDRE flag in SSR is cleared to 0 after writing of transmit data into TDR. Select the transmit format in SMR before setting the TE bit to 1.
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Bit 4Receive Enable (RE): Enables or disables the start of SCI serial receiving operations.
Bit 4 RE 0 1 Description Receiving disabled* Receiving enabled*
1
(Initial value)
2
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These flags retain their previous values. 2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode. Select the receive format in SMR before setting the RE bit to 1.
Bit 3Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in SMR. The MPIE bit setting is ignored in synchronous mode or when the MP bit is cleared to 0.
Bit 3 MPIE 0 Description Multiprocessor interrupts are disabled (normal receive operation) (Initial value) [Clearing conditions] * * 1 The MPIE bit is cleared to 0 MPB = 1 in received data
Multiprocessor interrupts are enabled* Receive-data-full interrupts (RXI), receive-error interrupts (ERI), and setting of the RDRF, FER, and ORER status flags in SSR are disabled until data with the multiprocessor bit set to 1 is received.
Note:
*
The SCI does not transfer receive data from RSR to RDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in SSR. When it receives data in which MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the MPIE bit to 0, enables RXI and ERI interrupts (if the TIE and RIE bits in SCR are set to 1), and allows the FER and ORER flags to be set.
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Bit 2Transmit-End interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted.
Bit 2 TEIE 0 1 Note: * Description Transmit-end interrupt requests (TEI) are disabled* Transmit-end interrupt requests (TEI) are enabled* TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR, then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by clearing the TEIE bit to 0. (Initial value)
Bits 1 and 0Clock Enable 1 and 0 (CKE1, CKE0): The function of these bits differs for the normal serial communication interface and for the smart card interface. Their function is switched with the SMIF bit in SCMR. For serial communication interface (SMIF bit in SCMR cleared to 0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the settings of CKE1 and CKE0, the SCK pin can be used for generic input/output, serial clock output, or serial clock input. The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external clock source is selected (CKE1 = 1). Select the SCI operating mode in SMR before setting the CKE1 and CKE0 bits. For further details on selection of the SCI clock source, see table 13.9 in section 13.3, Operation.
Bit 1 Bit 0 CKE1 CKE0 Description 0 0 Asynchronous mode Synchronous mode 0 1 Asynchronous mode Synchronous mode 1 0 Asynchronous mode Synchronous mode 1 1 Asynchronous mode Synchronous mode Internal clock, SCK pin available for generic input/output* Internal clock, SCK pin used for serial clock output* Internal clock, SCK pin used for clock output*
2 1 1
Internal clock, SCK pin used for serial clock output External clock, SCK pin used for clock input*
3
External clock, SCK pin used for serial clock input External clock, SCK pin used for clock input*
3
External clock, SCK pin used for serial clock input
Notes: 1. Initial value 2. The output clock frequency is the same as the bit rate. 3. The input clock frequency is 16 times the bit rate. Rev.5.00 Sep. 12, 2007 Page 439 of 764 REJ09B0396-0500
13. Serial Communication Interface
For smart card interface (SMIF bit in SCMR set to 1): These bits, together with the GM bit in SMR, determine whether the SCK pin is used for generic input/output or as the serial clock output pin.
SMR GM 0 0 1 1 1 1 Bit 1 Bit 0 CKE1 CKE0 Description 0 0 0 0 1 1 0 1 0 1 0 1 SCK pin available for generic input/output SCK pin used for clock output SCK pin output fixed low SCK pin used for clock output SCK pin output fixed high SCK pin used for clock output (Initial value)
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13.2.7
Serial Status Register (SSR)
SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate the operating status of the SCI.
Bit 7 TDRE Initial value Read/Write 1 R/(W)*1 6 RDRF 0 5 4 3 PER 0 R/(W)*
1
2 TEND 1 R
1 MPB 0 R
0 MPBT 0 R/W Multiprocessor bit transfer Value of multiprocessor bit to be transmitted
ORER FER/ERS 0 0 R/(W)*1
R/(W)*1 R/(W)*1
Multiprocessor bit Stores the received multiprocessor bit value Transmit end*2 Status flag indicating end of transmission Parity error Status flag indicating detection of a receive parity error Framing error (FER)/Error signal status (ERS)*2 Status flag indicating detection of a receive framing error, or flag indicating detection of an error signal Overrun error Status flag indicating detection of a receive overrun error Receive data register full Status flag indicating that data has been received and stored in RDR Transmit data register empty Status flag indicating that transmit data has been transferred from TDR into TSR and new data can be written in TDR Notes: 1. 2. Only 0 can be written, to clear the flag. Function differs between the normal serial communication interface and the smart card interface.
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The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER, and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The TEND and MPB flags are read-only bits that cannot be written. SSR is initialized to H'84 by a reset and in standby mode. Bit 7Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from TDR into TSR and the next serial data can be written in TDR.
Bit 7 TDRE 0 Description TDR contains valid transmit data [Clearing conditions] * * 1 Read TDRE when TDRE = 1, then write 0 in TDRE The DMAC writes data in TDR (Initial value)
TDR does not contain valid transmit data [Setting conditions] * * * The chip is reset or enters standby mode The TE bit in SCR is cleared to 0
TDR contents are loaded into TSR, so new data can be written in TDR
Bit 6Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.
Bit 6 RDRF 0 Description RDR does not contain new receive data [Clearing conditions] * * * 1 The chip is reset or enters standby mode Read RDRF when RDRF = 1, then write 0 in RDRF The DMAC reads data from RDR (Initial value)
RDR contains new receive data [Setting condition] Serial data is received normally and transferred from RSR to RDR
Note: The RDR contents and the RDRF flag are not affected by detection of receive errors or by clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still set to 1 when reception of the next data ends, an overrun error will occur and the receive data will be lost.
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Bit 5Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error.
Bit 5 ORER 0 Description Receiving is in progress or has ended normally* [Clearing conditions] * * 1 The chip is reset or enters standby mode Read ORER when ORER = 1, then write 0 in ORER
2 1
(Initial value)
A receive overrun error occurred* [Setting condition]
Reception of the next serial data ends when RDRF = 1 Notes: 1. Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its previous value. 2. RDR continues to hold the receive data prior to the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In synchronous mode, serial transmitting is also disabled.
Bit 4Framing Error (FER)/Error Signal Status (ERS): The function of this bit differs for the normal serial communication interface and for the smart card interface. Its function is switched with the SMIF bit in SCMR. For serial communication interface (SMIF bit in SCMR cleared to 0): Indicates that data reception ended abnormally due to a framing error in asynchronous mode.
Bit 4 FER 0 Description Receiving is in progress or has ended normally* [Clearing conditions] * * 1 The chip is reset or enters standby mode Read FER when FER = 1, then write 0 in FER
1
(Initial value)
A receive framing error occurred [Setting condition] The stop bit at the end of the receive data is checked and found to be 0*
2
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous value. 2. When the stop bit length is 2 bits, only the first bit is checked. The second stop bit is not checked. When a framing error occurs the SCI transfers the receive data into RDR but does not set the RDRF flag. Serial receiving cannot continue while the FER flag is set to 1. In synchronous mode, serial transmitting is also disabled. Rev.5.00 Sep. 12, 2007 Page 443 of 764 REJ09B0396-0500
13. Serial Communication Interface
For smart card interface (SMIF bit in SCMR set to 1): Indicates the status of the error signal sent back from the receiving side during transmission. Framing errors are not detected in smart card interface mode.
Bit 4 ERS 0 Description Normal reception, no error signal* [Clearing conditions] * * 1 The chip is reset or enters standby mode Read ERS when ERS = 1, then write 0 in ERS (Initial value)
An error signal has been sent from the receiving side indicating detection of a parity error [Setting condition] The error signal is low when sampled
Note:
*
Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous value.
Bit 3Parity Error (PER): Indicates that data reception ended abnormally due to a parity error in asynchronous mode.
Bit 3 PER 0 Description Receiving is in progress or has ended normally* [Clearing conditions] * * 1 The chip is reset or enters standby mode Read PER when PER = 1, then write 0 in PER
2 1
(Initial value)
A receive parity error occurred* [Setting condition]
The number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of O/E in SMR Notes: 1. Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous value. 2. When a parity error occurs the SCI transfers the receive data into RDR but does not set the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In synchronous mode, serial transmitting is also disabled.
Bit 2Transmit End (TEND): The function of this bit differs for the normal serial communication interface and for the smart card interface. Its function is switched with the SMIF bit in SCMR.
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13. Serial Communication Interface
For serial communication interface (SMIF bit in SCMR cleared to 0): Indicates that when the last bit of a serial character was transmitted TDR did not contain valid transmit data, so transmission has ended. The TEND flag is a read-only bit and cannot be written.
Bit 2 TEND 0 Description Transmission is in progress [Clearing conditions] * * 1 Read TDRE when TDRE = 1, then write 0 in TDRE The DMAC writes data in TDR (Initial value)
End of transmission [Setting conditions] * * * The chip is reset or enters standby mode The TE bit in SCR is cleared to 0
TDRE is 1 when the last bit of a 1-byte serial transmit character is transmitted
For smart card interface (SMIF bit in SCMR set to 1): Indicates that when the last bit of a serial character was transmitted TDR did not contain valid transmit data, so transmission has ended. The TEND flag is a read-only bit and cannot be written.
Bit 2 TEND 0 Description Transmission is in progress [Clearing conditions] * * 1 Read TDRE when TDRE = 1, then write 0 in TDRE The DMAC writes data in TDR (Initial value)
End of transmission [Setting conditions] * * * The chip is reset or enters standby mode
The TE bit is cleared to 0 in SCR and the FER/ERS bit is also cleared to 0 TDRE is 1 and FER/ERS is 0 (normal transmission) 2.5 etu (when GM = 0) or 1.0 etu (when GM = 1) after a 1-byte serial character is transmitted
Note: etu: Elementary time unit (time required to transmit one bit)
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Bit 1Multiprocessor bit (MPB): Stores the value of the multiprocessor bit in the receive data when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit, and cannot be written.
Bit 1 MPB 0 1 Note: * Description Multiprocessor bit value in receive data is 0* Multiprocessor bit value in receive data is 1 If the RE bit in SCR is cleared to 0 when a multiprocessor format is selected, MPB retains its previous value. (Initial value)
Bit 0Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format in selected for transmitting in asynchronous mode. The MPBT bit setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the SCI cannot transmit.
Bit 0 MPBT 0 1 Description Multiprocessor bit value in transmit data is 0 Multiprocessor bit value in transmit data is 1 (Initial value)
13.2.8
Bit Rate Register (BRR)
BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR that select the baud rate generator clock source, determines the serial communication bit rate.
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
The CPU can always read and write BRR. BRR is initialized to H'FF by a reset and in standby mode. Each SCI channel has independent baud rate generator control, so different values can be set in the three channels. Table 13.3 shows examples of BRR settings in asynchronous mode. Table 13.4 shows examples of BRR settings in synchronous mode.
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13. Serial Communication Interface
Table 13.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode
(MHz) Bit Rate (bit/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 1 1 0 0 0 0 0 0 0 0 0 2 N Error (%) n 1 1 0 0 0 0 0 0 0 0 0 2.097152 N Error (%) n 1 1 0 0 0 0 0 0 0 0 0 (MHz) Bit Rate (bit/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 1 1 0 0 0 0 0 0 0 3.6864 N 64 Error (%) n 0.07 2 1 1 0 0 0 0 0 0 0 0 N 70 4 Error (%) n 0.03 2 1 1 0 0 0 0 0 0 0 0 N 86 4.9152 Error (%) n 0.31 2 2 1 1 0 0 0 0 0 0 0 N 88 64 5 Error (%) -0.25 0.16 N 148 -0.04 108 0.21 217 0.21 108 0.21 54 26 13 6 2 1 1 -0.70 1.14 -2.48 -2.48 13.78 4.86 -14.67 2.4576 Error (%) n 1 1 1 0 0 0 0 0 0 0 N 174 -0.26 127 0.00 255 0.00 127 0.00 63 31 15 7 3 1 1 0.00 0.00 0.00 0.00 0.00 22.88 0.00 3 Error (%)
141 0.03 103 0.16 207 0.16 103 0.16 51 25 12 6 2 1 1 0.16 0.16 0.16 -6.99 8.51 0.00 -18.62
212 0.03 155 0.16 77 0.16
155 0.16 77 38 19 9 4 2 0.16 0.16 -2.34 -2.34 -2.34 0.00
191 0.00 95 0.00
207 0.16 103 0.16 207 0.16 103 0.16 51 25 12 6 3 2 0.16 0.16 0.16 -6.99 0.00 8.51
255 0.00 127 0.00 255 0.00 127 0.00 63 31 15 7 4 3 0.00 0.00 0.00 0.00 -1.70 0.00
129 0.16 64 0.16
191 0.00 95 47 23 11 5 2 0.00 0.00 0.00 0.00 0.00 0.00
129 0.16 64 32 15 7 4 3 0.16 -1.36 1.73 1.73 0.00 1.73
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13. Serial Communication Interface (MHz) Bit Rate (bit/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 1 1 0 0 0 0 0 0 0 6 N Error (%) n 2 2 1 1 0 0 0 0 0 0 0 N 106 -0.44 77 0.16 6.144 Error (%) n 2 2 1 1 0 0 0 0 0 0 0 N 7.3728 Error (%) n 2 2 1 1 0 0 0 0 0 0 0 N 130 -0.07 95 0.00 8 Error (%)
108 0.08 79 0.00
141 0.03 103 0.16 207 0.16 103 0.16 207 0.16 103 0.16 51 25 12 7 6 0.16 0.16 0.16 0.00 -6.99
155 0.16 77 0.16
159 0.00 79 0.00
191 0.00 95 0.00
155 0.16 77 38 19 9 5 4 0.16 0.16 -2.34 -2.34 0.00 -2.34
159 0.00 79 39 19 9 5 4 0.00 0.00 0.00 0.00 2.40 0.00
191 0.00 95 47 23 11 6 5 0.00 0.00 0.00 0.00 5.33 0.00
(MHz) Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 9.8304 n 2 2 1 1 0 0 0 0 0 0 0 N Error (%) n 2 2 2 1 1 0 0 0 0 0 0 N 174 -0.26 127 0.00 255 0.00 127 0.00 255 0.00 127 0.00 63 31 15 9 7 0.00 0.00 0.00 -1.70 0.00 10 Error (%) n 2 2 2 1 1 0 0 0 0 0 0 N 177 -0.25 129 0.16 64 0.16 12 Error (%) n 2 2 2 1 1 0 0 0 0 0 0 N 12.288 Error (%)
212 0.03 155 0.16 77 0.16
217 0.08 159 0.00 79 0.00
129 0.16 64 0.16
155 0.16 77 0.16
159 0.00 79 0.00
129 0.16 64 32 15 9 7 0.16 -1.36 1.73 0.00 1.73
155 0.16 77 38 19 11 9 0.16 0.16 -2.34 0.00 -2.34
159 0.00 79 39 19 11 9 0.00 0.00 0.00 2.40 0.00
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13. Serial Communication Interface (MHz) Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 13 nN Error n N (%) 14 14.7456 Error n N (%) 0.70 3 70 16 Error n N (%) 0.03 3 79 18 Error n N (%) -0.12 3 88 3 64 20 Error (%) -0.25 0.16
Error n N (%)
2 230 -0.08 2 248 -0.17 3 64 2 168 0.16 2 84 2 181 0.16 0.16 -0.43 2 90 -0.43 1 90 -0.43 0 90 0.76 0.76 0.00 0 45 0 22 0 13
2 191 0.00 2 95 0.00
2 207 0.16 2 103 0.16 1 207 0.16 1 103 0.16 0 207 0.16 0 103 0.16 0 51 0 25 0.16 0.16 0.00 0.16
2 233 0.16 2 116 0.16 1 233 0.16 1 116 0.16 0 233 0.16 0 116 0.16 0 58 0 28 0 17 0 14
2 129 0.16 2 64 0.16
1 168 0.16 1 84
1 181 0.16 0.16
1 191 0.00 1 95 0.00
1 129 0.16 1 64 0.16
0 168 0.16 0 84 0 41 0 20 0 12 0 10
0 181 0.16 0.16
0 191 0.00 0 95 0.00 0.00 0.00
0 129 0.16 0.16 -1.36 0.00 1.73
-0.93 0 47 -0.93 0 23 0.00 3.57 0 14 0 11
-0.69 0 64 1.02 0.00 0 32 0 19
-1.70 0 15 0.00 0 12
-3.82 0 10
-2.34 0 15
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13. Serial Communication Interface
Table 13.4 Examples of Bit Rates and BRR Settings in Synchronous Mode
(MHz) Bit 2 Rate (bit/s) n 110 250 500 1k 2.5k 5k 10k 25k 50k 3 2 1 1 0 0 0 0 0 4 N 70 124 249 124 199 99 49 19 9 4 1 0* n 2 2 1 1 0 0 0 0 0 0 0 0 N 249 124 249 99 199 99 39 19 9 3 1 0* n 3 2 2 1 1 0 0 0 0 0 0 0 0 8 N 124 249 124 199 99 199 79 39 19 7 3 1 0* 10 n 1 1 0 0 0 0 0 0 0 N 249 124 249 99 49 24 9 4 0* 13 n 3 3 2 2 1 1 0 0 0 N 202 101 202 80 162 80 129 64 12 16 n 3 3 2 2 1 1 0 0 0 0 0 0 0 0 N 249 124 249 99 199 99 159 79 39 15 7 3 1 0* 18 n 3 3 2 1 1 0 0 0 0 0 0 N 140 69 112 224 112 179 89 44 17 8 4 20 n 3 3 2 1 1 0 0 0 0 0 0 N 155 77 124 249 124 199 99 49 19 9 4
100k 0 250k 0 500k 0 1M 2M 2.5M 4M
Legend: Blank: No setting available : Setting possible, but error occurs *: Continuous transmission/reception not possible Note: Settings with an error of 1% or less are recommended.
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The BRR setting is calculated as follows: Asynchronous mode:
N=
64 x 22n-1 x B
x 106 - 1
Synchronous mode:
N=
8x 22n-1 x B
x 106 - 1
Legend: B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) : System clock frequency (MHz) n: Baud rate generator clock source (n = 0, 1, 2, 3) (For the clock sources and values of n, see the following table.)
SMR Settings n 0 1 2 3 Clock Source /4 /16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1
The bit rate error in asynchronous mode is calculated as follows:
Error (%) =
x 106 (N + 1) x B x 64 x 22n-1
-1
x 100
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13. Serial Communication Interface
Table 13.5 shows the maximum bit rates in asynchronous mode for various system clock frequencies. Table 13.6 and 13.7 shows the maximum bit rates with external clock input. Table 13.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode)
Settings (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 20 Maximum Bit Rate (bit/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 625000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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13. Serial Communication Interface
Table 13.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)
(MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 20 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 5.0000 Maximum Bit Rate (bit/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 153600 156250 187500 192000 218750 230400 250000 268800 281250 312500
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13. Serial Communication Interface
Table 13.7 Maximum Bit Rates with External Clock Input (Synchronous Mode)
(MHz) 2 4 6 8 10 12 14 16 18 20 External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 Maximum Bit Rate (bit/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3
13.3
13.3.1
Operation
Overview
The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. A smart card interface is also supported as a serial communication function for an IC card interface. Selection of asynchronous or synchronous mode and the transmission format for the normal serial communication interface is made in SMR, as shown in table 13.8. The SCI clock source is selected by the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13.9. For details of the procedures for switching between LSB-first and MSB-first mode and inverting the data logic level, see section 14.2.1, Smart Card Mode Register (SCMR). For selection of the smart card interface format, see section 14.3.3, Data Format. Asynchronous Mode * Data length is selectable: 7 or 8 bits * Parity and multiprocessor bits are selectable, and so is the stop bit length (1 or 2 bits). These selections determine the communication format and character length. * In receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break state.
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13. Serial Communication Interface
* An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Synchronous Mode * The communication format has a fixed 8-bit data length. * In receiving, it is possible to detect overrun errors. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and can output a serial clock signal to external devices. When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used. Smart Card Interface * One frame consists of 8-bit data and a parity bit. * In transmitting, a guard time of at least two elementary time units (2 etu) is provided between the end of the parity bit and the start of the next frame. (An elementary time unit is the time required to transmit one bit.) * In receiving, if a parity error is detected, a low error signal level is output for 1 etu, beginning 10.5 etu after the start bit.. * In transmitting, if an error signal is received, the same data is automatically transmitted again after at least 2 etu. * Only asynchronous communication is supported. There is no synchronous communication function. For details of smart card interface operation, see section 14, Smart Card Interface.
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13. Serial Communication Interface
Table 13.8 SMR Settings and Serial Communication Formats
SMR Settings Bit 7 C/A 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP Mode 0 1 1 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 Synchronous mode 8-bit data Absent Asyn8-bit data chronous mode (multi7-bit data processor Present Absent Present 7-bit data Absent Asynchronous mode Data Length 8-bit data SCI Communication Format Multiprocessor Parity Bit Bit Absent Absent Stop Bit Length 1 bit 2 bits Present 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None
Table 13.9 SMR and SCR Settings and SCI Clock Source Selection
SMR Bit 7 C/A 0 SCR Setting Bit 1 Bit 0 CKE1 CKE0 Mode 0 0 1 1 0 1 1 0 0 1 1 0 1 Synchronous mode Internal Asynchronous mode SCI Transmit/Receive clock Clock Source SCK Pin Function Internal SCI does not use the SCK pin Outputs clock with frequency matching the bit rate External Inputs clock with frequency 16 times the bit rate Outputs the serial clock
External
Inputs the serial clock
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13. Serial Communication Interface
13.3.2
Operation in Asynchronous Mode
In asynchronous mode, each transmitted or received character begins with a start bit and ends with one or two stop bits. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full-duplex communication is possible. The transmitter and the receiver are both double-buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 13.2 shows the general format of asynchronous serial communication. In asynchronous serial communication the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and one or two stop bits (high), in that order. When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit.
Idle (mark) state
1 (LSB) 0 D0 D1 D2 D3 D4 D5 D6 (MSB) D7 0/1 1 1
1
Serial data
Start bit 1 bit
Transmit or receive data 7 or 8 bits One unit of data (character or frame)
Parity bit 1 bit, or none
Stop bit(s) 1 or 2 bits
Figure 13.2 Data Format in Asynchronous Communication (Example: 8-Bit Data with Parity and 2 Stop Bits) Communication Formats: Table 13.10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in SMR.
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13. Serial Communication Interface
Table 13.10 Serial Communication Formats (Asynchronous Mode)
SMR Settings CHR 0 PE 0 MP 0 STOP 0 Serial Communication Format and Frame Length
1 S
2
3
4
5
6
7
8
9
10
STOP
11
12
8-bit data
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P STOP
0
1
0
1
S
8-bit data
P STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P STOP
1
1
0
1
S
7-bit data
P STOP STOP
0
1
0
S
8-bit data
MPB STOP
0
1
1
S
8-bit data
MPB STOP STOP
1
1
0
S
7-bit data
MPB STOP
1
1
1
S
7-bit data
MPB STOP STOP
Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev.5.00 Sep. 12, 2007 Page 458 of 764 REJ09B0396-0500
13. Serial Communication Interface
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. For details of SCI clock source selection, see table 13.9. When an external clock is input at the SCK pin, it must have a frequency 16 times the desired bit rate. When the SCI is operated on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as shown in figure 13.3 so that the rising edge of the clock occurs at the center of each transmit data bit.
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 13.3 Phase Relationship between Output Clock and Serial Data (Asynchronous Mode) Transmitting and Receiving Data: * SCI Initialization (Asynchronous Mode): Before transmitting or receiving data, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and initializes TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags, or RDR, which retain their previous contents. When an external clock is used the clock should not be stopped during initialization or subsequent operation, since operation will be unreliable in this case. Figure 13.4 shows a sample flowchart for initializing the SCI.
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13. Serial Communication Interface
Start of initialization
Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (leaving TE and RE bits cleared to 0) Select communication format in SMR Set value in BRR Wait No 1-bit interval elapsed? Yes (4) Set TE or RE bit to 1 in SCR Set RIE, TIE, TEIE, and MPIE bits (4) (1) (1) Set the clock source in SCR. Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made in SCR. Select the communication format in SMR.
(2) (2) (3) (3)
Write the value corresponding to the bit rate in BRR. This step is not necessary when an external clock is used. Wait for at least the interval required to transmit or receive one bit, then set the TE or RE bit to 1 in SCR. Set the RIE, TIE, TEIE, and MPIE bits. Setting the TE or RE bit enables the SCI to use the TxD or RxD pin.
Note: In simultaneous transmitting and receiving, the TE and RE bits should be cleared to 0 or set to 1 simultaneously.
Figure 13.4 Sample Flowchart for SCI Initialization
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13. Serial Communication Interface
* Transmitting Serial Data (Asynchronous Mode): Figure 13.5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow.
Initialize Start transmitting (1) (1) SCI initialization: the transmit data output function of the TxD pin is selected automatically. After the TE bit is set to 1, one frame of 1s is output, then transmission is possible. (2) SCI status check and transmit data write: read SSR and check that the TDRE flag is set to 1, then write transmit data in TDR and clear the TDRE flag to 0. (3) To continue transmitting serial data: after checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is activated by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. (3) (4) To output a break signal at the end of serial transmission: set the DDR bit to 1 and clear the DR bit to 0 (DDR and DR are I/O port registers), then clear the TE bit to 0 in SCR.
Read TDRE flag in SSR No
(2)
TDRE = 1 Yes Write transmit data in TDR and clear TDRE flag to 0 in SSR
All data transmitted? Yes Read TEND flag in SSR
No
TEND = 1 Yes Output break signal? Yes Clear DR bit to 0 and set DDR bit to 1
No
No
(4)
Clear TE bit to 0 in SCR

Figure 13.5 Sample Flowchart for Transmitting Serial Data
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13. Serial Communication Interface
In transmitting serial data, the SCI operates as follows: * The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. * After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: Start bit: One 0 bit is output. Transmit data: 7 or 8 bits are output, LSB first. Parity bit or multiprocessor bit: One parity bit (even or odd parity),or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. Stop bit(s): One or two 1 bits (stop bits) are output. Mark state: Output of 1 bits continues until the start bit of the next transmit data. * The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmitend interrupt (TEI) is requested at this time Figure 13.6 shows an example of SCI transmit operation in asynchronous mode.
1
Start bit Data Parity Stop Start bit bit bit Data Parity Stop bit bit
1
0
D0
D1
D7
0/1
1
0
D0
D1
D7
0/1
1 Idle state (mark state)
TDRE TEND
1 frame TXI interrupt request TXI interrupt handler writes data in TDR and clears TDRE flag to 0 TXI interrupt request TEI interrupt request
Figure 13.6 Example of SCI Transmit Operation in Asynchronous Mode (8-Bit Data with Parity and One Stop Bit)
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13. Serial Communication Interface
* Receiving Serial Data (Asynchronous Mode): Figure 13.7 shows a sample flowchart for receiving serial data and indicates the procedure to follow.
Initialize Start receiving (2)(3) Read ORER, PER, and FER flags in SSR (2) (1) (1) SCI initialization: the receive data input function of the RxD pin is selected automatically. Receive error handling and break detection: if a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After executing the necessary error handling, clear the ORER, PER, and FER flags all to 0. Receiving cannot resume if any of these flags remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state.
PERFEROPER = 1
Yes (3)
No
Error handling (continued on next page)
Read RDRF flag in SSR No
(4)
(4)
RDRF = 1 Yes
SCI status check and receive data read: read SSR, check that the RDRF flag is set to 1, then read receive data from RDR and clear the RDRF flag to 0. Notification that the RDRF flag has changed from 0 to 1 can also be given by the RXI interrupt. To continue receiving serial data: check the RDRF flag, read RDR, and clear the RDRF flag to 0 before the stop bit of the current frame is received. When the DMAC is activated by a receive-data-full interrupt request (RXI) to read RDR, the RDRF flag is cleared automatically.
Read receive data from RDR, and clear RDRF flag to 0 in SSR
(5)
No
All data received? Yes Clear RE bit to 0 in SCR
(5)

Figure 13.7 Sample Flowchart for Receiving Serial Data (1)
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13. Serial Communication Interface
(3) Error handling
No
ORER = 1 Yes Overrun error handling
No
FER = 1 Yes Break? No Framing error handling Clear RE bit to 0 in SCR Yes
No
PER = 1 Yes Parity error handling
Clear ORER, PER, and FER flags to 0 in SSR

Figure 13.7 Sample Flowchart for Receiving Serial Data (2)
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13. Serial Communication Interface
In receiving, the SCI operates as follows: * The SCI monitors the communication line. When it detects a start bit (0 bit), the SCI synchronizes internally and starts receiving. * Receive data is stored in RSR in order from LSB to MSB. * The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks: Parity check: The number of 1s in the receive data must match the even or odd parity setting of in the O/E bit in SMR. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first is checked. Status check: The RDRF flag must be 0, indicating that the receive data can be transferred from RSR into RDR. If these all checks pass, the RDRF flag is set to 1 and the received data is stored in RDR. If one of the checks fails (receive error*), the SCI operates as shown in table 13.11. Note: * When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag is not set to 1. Be sure to clear the error flags to 0. * When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt (RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also set to 1, a receive-error interrupt (ERI) is requested. Table 13.11 Receive Error Conditions
Receive Error Abbreviation Condition Overrun error ORER Framing error FER Parity error PER Data Transfer
Receiving of next data ends while Receive data is not transferred RDRF flag is still set to 1 in SSR from RSR to RDR Stop bit is 0 Receive data is transferred from RSR to RDR
Parity of received data differs from Receive data is transferred from even/odd parity setting in SMR RSR to RDR
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13. Serial Communication Interface
Figure 13.8 shows an example of SCI receive operation in asynchronous mode.
1
Start bit Data Parity Stop bit bit Start bit Data Stop Parity Stop bit bit bit
1
0
D0
D1
D7
0/1
1
0
D0
D1
D7
0/1
1
Idle (mark) state
RDRF
FER
RXI request 1 frame RXI interrupt handler reads data in RDR and clears RDRF flag to 0 Framing error, ERI request
Figure 13.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) 13.3.3 Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by an ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor stars by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 13.9 shows an example of communication among different processors using a multiprocessor format. Communication Formats: Four formats are available. Parity bit settings are ignored when a multiprocessor format is selected. For details see table 13.10. Clock: See the description of asynchronous mode.
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13. Serial Communication Interface
Transmitting processor
Serial communication line
Receiving processor A (ID = 01)
Receiving processor B (ID = 02)
Receiving processor C (ID = 03)
Receiving processor D (ID = 04)
Serial data
H'01 (MPB = 1) ID-sending cycle: receiving processor address
H'AA (MPB = 0) Data-sending cycle: data sent to receiving processor specified by ID
Legend: MPB : Multiprocessor bit
Figure 13.9 Example of Communication among Processors using Multiprocessor Format (Sending Data H'AA to Receiving Processor A) Transmitting and Receiving Data: * Transmitting Multiprocessor Serial Data: Figure 13.10 shows a sample flowchart for transmitting multiprocessor serial data and indicates the procedure to follow.
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13. Serial Communication Interface
(1) (1) SCI initialization: the transmit data output function of the TxD pin is selected automatically. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR. Also set the MPBT flag to 0 or 1 in SSR. Finally, clear the TDRE flag to 0. To continue transmitting serial data: after checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is activated by a transmit-dataempty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. To output a break signal at the end of serial transmission: set the DDR bit to 1 and clear the DR bit to 0 (DDR and DR are I/O port registers), then clear the TE bit to 0 in SCR.
Initialize Start transmitting
(2) Read TDRE flag in SSR (2)
TDRE = 1 Yes Write transmit data in TDR and set MPBT bit in SSR Clear TDRE flag to 0
No
(3)
(4) No
All data transmitted? Yes
(3)
Read TEND flag in SSR No
TEND = 1 Yes Output break signal? Yes
No
(4)
Clear DR bit to 0 and set DDR to 1
Clear TE bit to 0 in SCR

Figure 13.10 Sample Flowchart for Transmitting Multiprocessor Serial Data
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13. Serial Communication Interface
In transmitting serial data, the SCI operates as follows: * The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. * After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: Start bit: One 0 bit is output. Transmit data: 7 or 8 bits are output, LSB first. Multiprocessor bit: One multiprocessor bit (MPBT value) is output. Stop bit(s): One or two 1 bits (stop bits) are output. Mark state: Output of 1 bits continues until the start bit of the next transmit data. * The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmitend interrupt (TEI) is requested at this time Figure 13.11 shows an example of SCI transmit operation using a multiprocessor format.
Multiprocessor Stop Start bit bit bit Multiprocessor Stop bit bit
1
Start bit
Data
Data
0 TDRE TEND
D0
D1
D7
0/1
1
0
D0
D1
D7
0/1
1
Idle (mark) state
TXI interrupt TXI interrupt handler writes data in TDR and request clears TDRE flag to 0 1 frame
TXI interrupt request TEI interrupt request
Figure 13.11 Example of SCI Transmit Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit)
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13. Serial Communication Interface
* Receiving Multiprocessor Serial Data: Figure 13.12 shows a sample flowchart for receiving multiprocessor serial data and indicates the procedure to follow.
Initialize Start receiving (2) Set MPIE bit to 1 in SCR Read ORER and FER flags in SSR (2) (3) (1) (1) SCI initialization: the receive data input function of the RxD pin is selected automatically. ID receive cycle: set the MPIE bit to 1 in SCR. SCI status check and ID check: read SSR, check that the RDRF flag is set to 1, then read data from RDR and compare it with the processor's own ID. If the ID does not match, set the MPIE bit to 1 again and clear the RDRF flag to 0. If the ID matches, clear the RDRF flag to 0. SCI status check and data receiving: read SSR, check that the RDRF flag is set to 1, then read data from RDR. Receive error handling and break detection: if a receive error occurs, read the ORER and FER flags in SSR to identify the error. After executing the necessary error handling, clear the ORER and FER flags both to 0. Receiving cannot resume while either the ORER or FER flag remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state.
FERORER = 1 No Read RDRF flag in SSR
Yes (4) (3) (5)
No
RDRF = 1 Yes Read RDRF flag in SSR
No
Own ID? Yes Read ORER and FER flags in SSR FERORER = 1 No Read RDRF flag in SSR No (4) Yes
RDRF = 1
Yes Read receive data from RDR No
Finished receiving? Yes Clear RE bit to 0 in SCR
(5) Error handling (continued on next page)

Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (1)
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13. Serial Communication Interface
(5) Error handling
No
ORER = 1 Yes Overrun error handling
No
FER = 1 Yes Break? No Clear RE bit to 0 in SCR Framing error handling Yes
Clear ORER, PER, and FER flags to 0 in SSR

Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (2)
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13. Serial Communication Interface
Figure 13.13 shows an example of SCI receive operation using a multiprocessor format.
1
Start bit
Data (ID1)
MPB bit
D7 1
Stop
Start bit
Data (data1)
MPB bit
D7 0
Stop
1
0
D0
D1
1
0
D0
D1
1
Idle (mark) state
MPIE RDRF RDR value
MPB detection MPIE = 0 RXI interrupt request (multiprocessor interrupt) RXI interrupt handler reads RDR data and clears RDRF flag to 0
ID1
Not own ID, so MPIE bit is set to 1 again
No RXI interrupt request, RDR not updated
a. Own ID does not match data
1
Start bit
Data (ID2)
MPB
D7 1
Stop bit
Start bit
Data (data1)
MPB
D7 0
Stop bit
1
0
D0
D1
1
0
D0
D1
1
Idle (mark) state
MPIE RDRF
RDR value
ID1 ID2 Data2
MPB detection MPIE = 0
RXI interrupt request (multiprocessor interrupt)
RXI interrupt handler reads RDR data and clears RDRF flag to 0
Own ID, so receiving MPIE bit is set to continues, with data 1 again received by RXI interrupt handler
b. Own ID matches data
Figure 13.13 Example of SCI Receive Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit)
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13. Serial Communication Interface
13.3.4
Synchronous Operation
In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so fullduplex communication is possible. The transmitter and the receiver are also double-buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 13.14 shows the general format in synchronous serial communication.
One unit (character or frame) of transfer data * Serial clock
LSB MSB
*
Serial data
Don't care
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don't care
Note: * High except in continuous transmitting or receiving
Figure 13.14 Data Format in Synchronous Communication In synchronous serial communication, each data bit is placed on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock. In each character, the serial data bits are transferred in order from LSB (first) to MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In synchronous mode the SCI receives data by synchronizing with the rise of the serial clock. Communication Format: The data length is fixed at 8 bits. No parity bit or multiprocessor bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected by means of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. See table 13.9 for details of SCI clock source selection. When the SCI operates on an internal clock, it outputs the clock source at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. If receiving in single-character units is required, an external clock should be selected.
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Transmitting and Receiving Data: * SCI Initialization (Synchronous Mode): Before transmitting or receiving data, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and initializes TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags, or RDR, which retain their previous contents. Figure 13.15 shows a sample flowchart for initializing the SCI.
Start of initialization (1) Set the clock source in SCR. Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits to 0. Select the communication format in SMR. Write the value corresponding to the bit rate in BRR. This step is not necessary when an external clock is used. Wait for at least the interval required to transmit or receive one bit, then set the TE or RE bit to 1 in SCR. Set the RIE, TIE, TEIE, and MPIE bits. Setting the TE or RE bit enables the SCI to use the TxD or RxD pin.
Clear TE and RE bits to 0 in SCR
(2) (3)
Set RIE, TIE, TEIE, MPIE, CKE1 and CKE0 bits in SCR (leaving TE and RE bits cleared to 0) Select communication format in SMR Set value in BRR Wait 1-bit interval elapsed? Yes Set TE or RE bit to 1 in SCR Set RIE, TIE, TEIE, and MPIE bits as necessary
(1) (4)
(2)
(3)
Yes
(4)
Note: In simultaneous transmitting and receiving, the TE and RE bits should be cleared to 0 or set to 1 simultaneously.
Figure 13.15 Sample Flowchart for SCI Initialization
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13. Serial Communication Interface
* Transmitting Serial Data (Synchronous Mode): Figure 13.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow.
Initialize Start transmitting (2) Read TDRE flag in SSR (2) (1) (1) SCI initialization: the transmit data output function of the TxD pin is selected automatically. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. To continue transmitting serial data: after checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is activated by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically.
TDRE = 1 Yes
No
(3)
Write transmit data in TDR and clear TDRE flag to 0 in SSR
All data transmitted? Yes Read TEND flag in SSR
No
(3)
TEND = 1 Yes Clear TE bit to 0 in SCR
No

Figure 13.16 Sample Flowchart for Serial Transmitting In transmitting serial data, the SCI operates as follows. * The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR.
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13. Serial Communication Interface
* After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin n order from LSB (bit 0) to MSB (bit 7). * The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the SCI loads data from TDR into TSR and begins serial transmission of the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB, holds the TxD pin in the MSB state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI) is requested at this time * After the end of serial transmission, the SCK pin is held in a constant state. Figure 13.17 shows an example of SCI transmit operation.
Transmit direction
Serial clock
Serial data TDRE TEND TXI interrupt request
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TXI interrupt handler TXI interrupt writes data in TDR request and clears TDRE flag to 0 1 frame
TEI interrupt request
Figure 13.17 Example of SCI Transmit Operation
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13. Serial Communication Interface
* Receiving Serial Data (Synchronous Mode): Figure 13.18 shows a sample flowchart for receiving serial data and indicates the procedure to follow. When switching from asynchronous to synchronous mode, make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and receiving will be disabled.
Initialize Start receiving (1) (1) SCI initialization: the receive data input function of the RxD pin is selected automatically.
Read ORER flag in SSR
(2)
ORER = 1 No
Yes (3) Error handling (continued on next page)
(2)(3) Receive error handling: if a receive error occurs, read the ORER flag in SSR, then after executing the necessary error handling, clear the ORER flag to 0. Neither transmitting nor receiving can resume while the ORER flag remains set to 1. (4) SCI status check and receive data read: read SSR, check that the RDRF flag is set to 1, then read receive data from RDR and clear the RDRF flag to 0. Notification that the RDRF flag has changed from 0 to 1 can also be given by the RXI interrupt. To continue receiving serial data: check the RDRF flag, read RDR, and clear the RDRF flag to 0 before the MSB (bit 7) of the current frame is received. When the DMAC is activated by a receive-data-full interrupt request (RXI) to read RDR, the RDRF flag is cleared automatically.
Read RDRF flag in SSR No
(4)
RDRF = 1 Yes Read receive data from RDR, and clear RDRF flag to 0 in SSR (5)
No
Finished receiving? Yes Clear RE bit to 0 in SCR
(5)

Figure 13.18 Sample Flowchart for Serial Receiving (1)
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13. Serial Communication Interface
(3) Error handling
Overrun error handling
Clear ORER flag to 0 in SSR

Figure 13.18 Sample Flowchart for Serial Receiving (2) In receiving, the SCI operates as follows: * The SCI synchronizes with the serial clock input or output and performs receive operation. * Receive data is stored in RSR in order from LSB to MSB. After receiving the data, the SCI checks that the RDRF flag is 0, so that receive data can be transferred from RSR to RDR. If this check passes, the RDRF flag is set to 1 and the received data is stored in RDR. If the checks fails (receive error), the SCI operates as shown in table 13.11. When a receive error has been identified in the error check, subsequent transmit and receive operations are disabled. * When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt (RXI) is requested. If the ORER flag is set to 1 and the RIE bit in SCR is also set to 1, a receive-error interrupt (ERI) is requested. Figure 13.19 shows an example of SCI receive operation.
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13. Serial Communication Interface
Serial clock
Serial data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF ORER RXI interrupt request RXI interrupt handler reads data in RDR and clears RDRF flag to 0 1 frame RXI interrupt request Overrun error, ERI interrupt request
Figure 13.19 Example of SCI Receive Operation
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* Transmitting and Receiving Data Simultaneously (Synchronous Mode): Figure 13.20 shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates the procedure to follow.
Initialize Start of transmitting and receiving (2) (2) (1) (1) SCI initialization: the transmit data output function of the TxD pin and the read data input function of the RxD pin are selected, enabling simultaneous transmitting and receiving. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. Notification that the TDRE flag has changed from 0 to 1 can also be given by the TXI interrupt. Receive error handling: if a receive error occurs, read the ORER flag in SSR, then after executing the necessary error handling, clear the ORER flag to 0. Neither transmitting nor receiving can resume while the ORER flag remains set to 1. SCI status check and receive data read: read SSR, check that the RDRF flag is 1, then read receive data from RDR and clear the RDRF flag to 0. Notification that the RDRF flag has changed from 0 to 1 can also be given by the RXI interrupt. To continue transmitting and receiving serial data: check the RDRF flag, read RDR, and clear the RDRF flag to 0 before the MSB (bit 7) of the current frame is received. Also check that the TDRE flag is set to 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0 before the MSB (bit 7) of the current frame is transmitted. When the DMAC is activated by a transmitdata-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. When the DMAC is activated by a receive-data-full interrupt request (RXI) to read RDR, the RDRF flag is cleared automatically.
Read TDRE flag in SSR
No
TDRE = 1 Yes (3)
Write transmit data in TDR and clear TDRE flag to 0 in SSR
(4) Read ORER flag in SSR Yes (3) No Error handling (4) (5)
ORER = 1
Read RDRF flag in SSR
No
RDRF = 1 Yes
Read receive data from RDR, and clear RDRF flag to 0 in SSR No
End of transmitting and receiving? Yes
(5)
Clear TE and RE bits to 0 in SCR
Note: When switching from transmitting or receiving to simultaneous transmitting and receiving, clear both the TE bit and the RE bit to 0, then set both bits to 1 simultaneously.
Figure 13.20 Sample Flowchart for Simultaneous Serial Transmitting and Receiving
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13. Serial Communication Interface
13.4
SCI Interrupts
The SCI has four interrupt request sources: transmit-end interrupt (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty interrupt (TXI). Table 13.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled or disabled by the TIE, RIE, and TEIE bits in SCR. Each interrupt request is sent separately to the interrupt controller. A TXI interrupt is requested when the TDRE flag is set to 1 in SSR. A TEI interrupt is requested when the TEND flag is set to 1 in SSR. A TXI interrupt request can activate the DMAC to transfer data. Data transfer by the DMAC automatically clears the TDRE flag to 0. A TEI interrupt request cannot activate the DMAC. An RXI interrupt is requested when the RDRF flag is set to 1 in SSR. An ERI interrupt is requested when the ORER, PER, or FER flag is set to 1 in SSR. An RXI interrupt can activate the DMAC to transfer data. Data transfer by the DMAC automatically clears the RDRF flag to 0. An ERI interrupt request cannot activate the DMAC. The DMAC can be activated by interrupts from SCI channel 0. Table 13.12 SCI Interrupt Sources
Interrupt Source ERI RXI TXI TEI Description Receive error (ORER, FER, or PER) Receive data register full (RDRF) Transmit data register empty (TDRE) Transmit end (TEND) Low Priority High
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13. Serial Communication Interface
13.5
13.5.1
Usage Notes
Notes on Use of SCI
Note the following points when using the SCI. TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of transmit data from TDR to TSR. The SCI sets the TDRE flag to 1 when it transfers data from TDR to TSR. Data can be written into TDR regardless of the state of the TDRE flag. If new data is written in TDR when the TDRE flag is 0, the old data stored in TDR will be lost because this data has not yet been transferred to TSR. Before writing transmit data in TDR, be sure to check that the TDRE flag is set to 1. Simultaneous Multiple Receive Errors: Table 13.13 shows the state of the SSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs the RSR contents are not transferred to RDR, so receive data is lost. Table 13.13 SSR Status Flags and Transfer of Receive Data
SSR Status Flags RDRF 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Transfer RSR RDR Not transferred Transferred Transferred Not transferred Not transferred Transferred Not transferred
Receive Errors Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.
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Sending a Break Signal: The input/output condition and level of the TxD pin are determined by DR and DDR bits. This feature can be used to send a break signal. After the serial transmitter is initialized, the DR value substitutes for the mark state until the TE bit is set to 1 (the TxD pin function is not selected until the TE bit is set to 1). The DDR and DR bits should therefore be set to 1 beforehand. To send a break signal during serial transmission, clear the DR bit to 0 , then clear the TE bit to 0. When the TE bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the TxD pin becomes an input/output outputting the value 0. Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that clearing the RE bit to 0 does not clear the receive error flags to 0. Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In asynchronous mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. See figure 13.21.
16 clocks 8 clocks
0 7 15 0 7 15 0
Internal base clock
Receive data (RxD)
Start bit
D0
D1
Synchronization sampling timing
Data sampling timing
Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode
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13. Serial Communication Interface
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M=
(0.5 -
1 2N
) - (L - 0.5) F -
D - 0.5 N
(1 + F)
x 100% . . . . . . . . (1)
M: N: D: L: F:
Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (L = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
D = 0.5, F = 0 M = (0.5 - = 46.875% 1 2 x 16 ) x 100%
. . . . . . . . (2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Use of DMAC: * When an external clock source is used for the serial clock, after the DMAC updates TDR, allow an inversion of at least five system clock () cycles before input of the serial clock to start transmitting. If the serial clock is input within four states of the TDR update, a malfunction may occur. (See figure 13.22) * To have the DMAC read RDR, be sure to select the corresponding SCI receive-data-full interrupt (RXI) as the activation source with bits DTS2 to DTS0 in DTCR.
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SCK
t
TDRE
D0
D1
D2
D3
D4
D5
D6
D7
Note: In operation with an external clock source, be sure that t >4 states.
Figure 13.22 Example of Synchronous Transmission Using DMAC Switching from SCK Pin Function to Port Pin Function: * Problem in Operation: When switching the SCK pin function to the output port function (highlevel output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. End of serial data transmission 2. TE bit = 0 3. C/A bit = 0 ... switchover to port output 4. Occurrence of low-level output (see figure 13.23)
Half-cycle low-level output SCK/port 1. End of transmission Data TE C/A CKE1 CKE0 Bit 6 Bit 7 2. TE = 0 4. Low-level output
3.C/A = 0
Figure 13.23 Operation when Switching from SCK Pin Function to Port Pin Function
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* Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown. 1. End of serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/A bit = 0 ... switchover to port output 5. CKE1 bit = 0
High-level output SCK/port 1. End of transmission Data TE C/A 3.CKE1 = 1 CKE1 CKE0 5.CKE1 = 0 Bit 6 Bit 7 2.TE = 0
4.C/A = 0
Figure 13.24 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output)
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14. Smart Card Interface
Section 14 Smart Card Interface
14.1 Overview
An IC card (smart card) interface conforming to the ISO/IEC 7816-3 (Identification Card) standard is supported as an extension of the serial communication interface (SCI) functions. Switchover between the normal serial communication interface and the smart card interface is controlled by a register setting. 14.1.1 Features
Features of the smart card interface supported by the H8/3067 Group are listed below. * Asynchronous communication Data length: 8 bits Parity bit generation and checking Transmission of error signal (parity error) in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported * Built-in baud rate generator allows any bit rate to be selected * Three interrupt sources There are three interrupt sources transmit-data-empty, receive-data-full, and transmit/receive error that can issue requests independently. The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA controller (DMAC) to execute data transfer.
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14.1.2
Block Diagram
Figure 14.1 shows a block diagram of the smart card interface.
Bus interface
Module data bus
Internal data bus
RDR
TDR
RxD
RSR
TSR
TxD Parity generation Parity check SCK Legend: SCMR: Smart card mode register RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register
SCMR SSR SCR SMR Transmission/ reception control
BRR Baud rate generator /4 /16 /64 Clock
External clock TXI RXI ERI
Figure 14.1 Block Diagram of Smart Card Interface 14.1.3 Pin Configuration
Table 14.1 shows the smart card interface pins. Table 14.1 Smart Card Interface Pins
Pin Name Serial clock pin Receive data pin Transmit data pin Abbreviation SCK RxD TxD I/O I/O Input Output Function Clock input/output Receive data input Transmit data output
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14.1.4
Register Configuration
The smart card interface has the internal registers listed in table 14.2. The BRR, TDR, and RDR registers have their normal serial communication interface functions, as described in section 13, Serial Communication Interface. Table 14.2 Smart Card Interface Registers
Channel 0 Address* H'FFFB0 H'FFFB1 H'FFFB2 H'FFFB3 H'FFFB4 H'FFFB5 H'FFFB6 1 H'FFFB8 H'FFFB9 H'FFFBA H'FFFBB H'FFFBC H'FFFBD H'FFFBE 2 H'FFFC0 H'FFFC1 H'FFFC2 H'FFFC3 H'FFFC4 H'FFFC5 H'FFFC6
1
Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register
Abbreviation SMR BRR SCR TDR SSR RDR SCMR SMR BRR SCR TDR SSR RDR SCMR SMR BRR SCR TDR SSR RDR SCMR
R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W
2 2 2
Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2
Notes: 1. Lower 20 bits of the address in advanced mode. 2. Only 0 can be written in bits 7 to 3, to clear the flags.
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14.2
Register Descriptions
This section describes the new or modified registers and bit functions in the smart card interface. 14.2.1 Smart Card Mode Register (SCMR)
SCMR is an 8-bit readable/writable register that selects smart card interface functions.
Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 SDIR 0 R/W 2 SINV 0 R/W 1 1 Reserved bit Smart card interface mode select Enables or disables the smart card interface function Smart card data invert Inverts data logic levels Smart card data transfer direction Selects the serial/parallel conversion format 0 SMIF 0 R/W
Reserved bits
SCMR is initialized to H'F2 by a reset and in standby mode. Bits 7 to 4Reserved: Read-only bits, always read as 1. Bit 3Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion 1 format.*
Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored LSB-first in RDR TDR contents are transmitted MSB-first Receive data is stored MSB-first in RDR (Initial value)
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Bit 2Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used in combination with the SDIR bit to communicate with inverse-convention 2 cards.* The SINV bit does not affect the logic level of the parity bit. For parity settings, see section 14.3.4, Register Settings.
Bit 2 SINV 0 1 Description Unmodified TDR contents are transmitted Receive data is stored unmodified in RDR Inverted TDR contents are transmitted Receive data is inverted before storage in RDR (Initial value)
Bit 1Reserved: Read-only bit, always read as 1. Bit 0Smart Card Interface Mode Select (SMIF): Enables the smart card interface function.
Bit 0 SMIF 0 1 Description Smart card interface function is disabled Smart card interface function is enabled (Initial value)
Notes: 1. The function for switching between LSB-first and MSB-first mode can also be used with the normal serial communication interface. Note that when the communication format data length is set to 7 bits and MSB-first mode is selected for the serial data to be transferred, bit 0 of TDR is not transmitted, and only bits 7 to 1 of the received data are valid. 2. The data logic level inversion function can also be used with the normal serial communication interface. Note that, when inverting the serial data to be transferred, parity transmission and parity checking is based on the number of high-level periods at the serial data I/O pin, and not on the register value.
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14.2.2
Serial Status Register (SSR)
The function of SSR bit 4 is modified in smart card interface mode. This change also causes a modification to the setting conditions for bit 2 (TEND).
Bit Initial value Read/Write 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W
Transmit end Status flag indicating end of transmission Error signal status (ERS) Status flag indicating that an error signal has been received Note: * Only 0 can be written, to clear the flag.
Bits 7 to 5: These bits operate as in normal serial communication. For details see section 13.2.7, Serial Status Register (SSR). Bit 4Error Signal Status (ERS): In smart card interface mode, this flag indicates the status of the error signal sent from the receiving device to the transmitting device. The smart card interface does not detection framing errors.
Bit 4 ERS 0 Description Indicates normal transmission, with no error signal returned [Clearing conditions] * * 1 The chip is reset, or enters standby mode or module stop mode Software reads ERS while it is set to 1, then writes 0. (Initial value)
Indicates that the receiving device sent an error signal reporting a parity error [Setting condition] A low error signal was sampled.
Note: Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous value.
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14. Smart Card Interface
Bits 3 to 0: These bits operate as in normal serial communication. For details see section 13.2.7, Serial Status Register (SSR). The setting conditions for transmit end (TEND, bit 2), however, are modified as follows.
Bit 2 TEND 0 Description Transmission is in progress [Clearing conditions] * * 1 Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag. The DMAC writes data in TDR. (Initial value)
End of transmission [Setting conditions] * * * The chip is reset or enters standby mode. The TE bit and FER/ERS bit are both cleared to 0 in SCR. TDRE is 1 and ERS is 0 at a time 2.5 etu after the last bit of a 1-byte serial character is transmitted (normal transmission).
Note: An etu (elementary time unit) is the time needed to transmit one bit.
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14.2.3
Serial Mode Register (SMR)
The function of SMR bit 7 is modified in smart card interface mode. This change also causes a modification to the function of bits 1 and 0 in the serial control register (SCR).
Bit Initial value Read/Write 7 GM 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
Bit 7GSM Mode (GM): With the normal smart card interface, this bit is cleared to 0. Setting this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the TEND flag that indicates completion of transmission, and the type of clock output used. The details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in the serial control register (SCR).
Bit 7 GM 0 Description Normal smart card interface mode operation * * 1 * * The TEND flag is set 12.5 etu after the beginning of the start bit. Clock output on/off control only. The TEND flag is set 11.0 etu after the beginning of the start bit. Clock output on/off and fixed-high/fixed-low control. (Initial value)
GSM mode smart card interface mode operation
Bits 6 to 0: These bits operate as in normal serial communication. For details see section 13.2.5, Serial Mode Register (SMR). 14.2.4 Serial Control Register (SCR)
The function of SCR bits 1 and 0 is modified in smart card interface mode.
Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W
Bits 7 to 2: These bits operate as in normal serial communication. For details see section 13.2.6, Serial Control Register (SCR).
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14. Smart Card Interface
Bits 1 and 0Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. In smart card interface mode, it is possible to specify a fixed high level or fixed low level for the clock output, in addition to the usual switching between enabling and disabling of the clock output.
Bit 7 GM 0 Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 1 0 1 Description Internal clock/SCK pin is I/O port Internal clock/SCK pin is clock output Internal clock/SCK pin is fixed at low output Internal clock/SCK pin is clock output Internal clock/SCK pin is fixed at high output Internal clock/SCK pin is clock output (Initial value)
14.3
14.3.1
Operation
Overview
The main features of the smart card interface are as follows. * One frame consists of 8-bit data plus a parity bit. * In transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of one bit) is provided between the end of the parity bit and the start of the next frame. * If a parity error is detected during reception, a low error signal level is output for a1 etu period 10.5 etu after the start bit. * If an error signal is detected during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. * Only asynchronous communication is supported; there is no synchronous communication function. 14.3.2 Pin Connections
Figure 14.2 shows a pin connection diagram for the smart card interface. In communication with a smart card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should both be connected to this line. The data transmission line should be pulled up to VCC with a resistor.
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When the smart card uses the clock generated on the smart card interface, the SCK pin output is input to the CLK pin of the smart card. If the smart card uses an internal clock, this connection is unnecessary. The reset signal should be output from one of this LSI's generic ports. In addition to these pin connections, power and ground connections will normally also be necessary.
VCC
TxD RxD SCK Clock line This chip Px (port) Reset line Card-processing device Data line
I/O
CLK RST Smart card
Figure 14.2 Smart Card Interface Connection Diagram Note: If a smart card is not connected, and both TE and RE are set to 1, closed transmission/ reception is possible, enabling self-diagnosis to be carried out. 14.3.3 Data Format
Figure 14.3 shows the smart card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting device to request retransmission of the data. In transmission, the error signal is sampled and the same data is retransmitted if the error signal is low.
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No parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Output from transmitting device
Parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Output from transmitting device Output from receiving device
Legend: Ds: D0 to D7: Dp: DE:
Start bit Data bits Parity bit Error signal
Figure 14.3 Smart Card Interface Data Format The operating sequence is as follows. 1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. 2. The transmitting device starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). 3. With the smart card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. 4. The receiving device carries out a parity check. If there is no parity error and the data is received normally, the receiving device waits for reception of the next data. If a parity error occurs, however, the receiving device outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving device places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. 5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data frame. If it receives an error signal, however, it returns to step 2 and transmits the same data again.
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14.3.4
Register Settings
Table 14.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described in this section. Table 14.3 Smart Card Interface Register Settings
Bit Register Address* SMR BRR SCR TDR SSR RDR SCMR H'FFFB0 H'FFFB1 H'FFFB2 H'FFFB3 H'FFFB4 H'FFFB5 H'FFFB6
1
Bit 7 GM BRR7 TIE TDR7 TDRE RDR7
Bit 6 0 BRR6 RIE TDR6 RDRF RDR6
Bit 5 1 BRR5 TE TDR5 ORER RDR5
Bit 4 O/E BRR4 RE TDR4 ERS RDR4
Bit 3 1 BRR3 0 TDR3 PER RDR3 SDIR
Bit 2 0 BRR2 0 TDR2 TEND RDR2 SINV
Bit 1 CKS1 BRR1 CKE1* TDR1 0 RDR1
2
Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF
Notes: Unused bit. 1. Lower 20 bits of the address in advanced mode. 2. When GM is cleared to 0 in SMR, the CKE1 bit must also be cleared to 0.
Serial Mode Register (SMR) Settings: Clear the GM bit to 0 when using the normal smart card interface mode, or set to 1 when using GSM mode. Clear the O/E bit to 0 if the smart card is of the direct convention type, or set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the built-in baud rate generator. See section 14.3.5, Clock. Bit Rate Register (BRR) Settings: BRR is used to set the bit rate. See section 14.3.5, Clock, for the method of calculating the value to be set. Serial Control Register (SCR) Settings: The TIE, RIE, TE, and RE bits have their normal serial communication functions. See section 13, Serial Communication Interface, for details. The CKE1 and CKE0 bits specify clock output. To disable clock output, clear these bits to 00; to enable clock output, set these bits to 01. Clock output is not performed when the GM bit is set to 1 in SMR. Clock output can also be fixed low or high. Smart Card Mode Register (SCMR) Settings: Clear both the SDIR bit and SINV bit cleared to 0 if the smart card is of the direct convention type, and set both to 1 if of the inverse convention type. To use the smart card interface, set the SMIF bit to 1.
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The register settings and examples of starting character waveforms are shown below for two smart cards, one following the direct convention and one the inverse convention. 1. Direct Convention (SDIR = SINV = O/E = 0)
(Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State
With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. In the example above, the first character data is H'3B. The parity bit is 1, following the even parity rule designated for smart cards. 2. Indirect Convention (SDIR = SINV = O/E = 1)
(Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State
With the indirect convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. In the example above, the first character data is H'3F. The parity bit is 0, corresponding to state Z, following the even parity rule designated for smart cards. In the H8/3067 Group, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR must be set to odd parity mode. This applies to both transmission and reception. 14.3.5 Clock
Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register (BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR). The equation for calculating the bit rate is shown below. Table 14.5 shows some sample bit rates. If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is output from the SCK pin.
B=
1488 x 22n-1 x (N + 1)
x 106
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where, N: BRR setting (0 N 255) B: Bit rate (bit/s) : Operating frequency (MHz) n: See table 14.4 Table 14.4 n-Values of CKS1 and CKS0 Settings
n 0 1 2 3 1 CKS1 0 CKS0 0 1 0 1
Note: If the gear function is used to divide the clock frequency, use the divided frequency to calculate the bit rate. The equation above applies directly to 1/1 frequency division.
Table 14.5 Bit Rates (bits/s) for Various BRR Settings (When n = 0)
(MHz) N 0 1 2 7.1424 9600.0 4800.0 3200.0 10.00 13440.9 6720.4 4480.3 10.7136 14400.0 7200.0 4800.0 13.00 17473.1 8736.6 5824.4 14.2848 19200.0 9600.0 6400.0 16.00 21505.4 10752.7 7168.5 18.00 24193.5 12096.8 8064.5 20.00 26881.7 13440.9 8960.6
Note: Bit rates are rounded off to one decimal place.
The following equation calculates the bit rate register (BRR) setting from the operating frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error.
N=
1488 x 22n-1 x B
x 106 - 1
Table 14.6 BRR Settings for Typical Bit Rates (bits/s) (When n = 0)
(MHz) 7.1424 bit/s 9600 N Error 0 0.00 10.00 N Error 1 30 10.7136 N Error 1 25 13.00 N Error 1 8.99 14.2848 N Error 1 0.00 16.00 N Error 1 12.01 18.00 N Error 2 15.99 20.00 N Error 2 6.66
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Table 14.7 Maximum Bit Rates for Various Frequencies (Smart Card Interface Mode)
(MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 Maximum Bit Rate (bits/s) 9600 13441 14400 17473 19200 21505 24194 26882 N 0 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 0
The bit rate error is given by the following equation:
Error (%) =
1488 x 22n-1 x B x (N + 1)
x 106 - 1
x 100
14.3.6
Transmitting and Receiving Data
Initialization: Before transmitting or receiving data, the smart card interface must be initialized as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits to 0 in the serial control register (SCR). 2. Clear error flags ERS, PER, and ORER to 0 in the serial status register (SSR). 3. Set the parity bit (O/E) and baud rate generator select bits (CKS1 and CKS0) in the serial mode register (SMR). Clear the C/A, CHR, and MP bits to 0, and set the STOP and PE bits to 1. 4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCMR). When the SMIF bit is set to 1, the TxD pin and RxD pin are both switched from port to SCI pin functions and go to the high-impedance state. 5. Set a value corresponding to the desired bit rate in the bit rate register (BRR). 6. Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE, and CKE1 bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. 7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis.
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Transmitting Serial Data: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 14.5 shows a sample transmission processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above. 2. Check that the ERS error flag is cleared to 0 in SSR. 3. Repeat steps 2 and 3 until it can be confirmed that the TEND flag is set to 1 in SSR. 4. Write the transmit data in TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. 5. To continue transmitting data, go back to step 2. 6. To end transmission, clear the TE bit to 0. The above processing may include interrupt handling DMA transfer. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (TXI) will be requested. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transmit/receive-error interrupt (ERI) will be requested. The timing of TEND flag setting depends on the GM bit in SMR (see figure 14.4). If the TXI interrupt activates the DMAC, the number of bytes designated in the DMAC can be transmitted automatically, including automatic retransmission. For details, see Interrupt Operations and Data Transfer by DMAC in this section.
Serial data
Ds
Dp
DE Guard time
(1) GM = 0 TEND
12.5 etu
(2) GM = 1 TEND
11.0 etu
Figure 14.4 Timing of TEND Flag Setting
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Start Initialization Start transmitting
No FER/ERS = 0? Yes Error handling No TEND = 1? Yes Write transmit data in TDR, and clear TDRE flag to 0 in SSR No
All data transmitted? Yes No FER/ERS = 0? Yes Error handling
No TEND = 1? Yes Clear TE bit to 0
End
Figure 14.5 Sample Transmission Processing Flowchart
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14. Smart Card Interface
TDR 1. Data write 2. Transfer from TDR to TSR 3. Serial data output Data 1 Data 1 Data 1 Data 1 Data remains in TDR Data 1 I/O signal output TSR (shift register)
In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps 2 and 3 above are repeated until the TEND flag is set. Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmission) of the retransmit data to be transmitted next has been completed.
Figure 14.6 Relation Between Transmit Operation and Internal Registers
I/O data
Ds
Da
Db
Dc
Dd
De
Df
Dg
Dh
Dp
DE Guard time
TXI (TEND interrupt)
12.5 etu
When GM = 0
11.0 etu
When GM = 1
Figure 14.7 Timing of TEND Flag Setting Receiving Serial Data: Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 14.8 shows a sample reception processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above. 2. Check that the ORER flag and PER flag are cleared to 0 in SSR. If either is set, perform the appropriate receive error handling, then clear both the ORER and the PER flag to 0. 3. Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1. 4. Read the receive data from RDR. 5. To continue receiving data, clear the RDRF flag to 0 and go back to step 2. 6. To end reception, clear the RE bit to 0.
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Start Initialization Start receiving
ORER = 0 and PER = 0? Yes
No
Error handling No RDRF = 1? Yes Read RDR and clear RDRF flag to 0 in SSR
No
All data received? Yes Clear RE bit to 0
Figure 14.8 Sample Reception Processing Flowchart The above procedure may include interrupt handling and DMA transfer. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (RXI) will be requested. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) will be requested. If the RXI interrupt activates the DMAC, the number of bytes designated in the DMAC will be transferred, skipping receive data in which an error occurred. For details, see Interrupt Operations and Data Transfer by DMAC in this section.
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If a parity error occurs during reception and the PER flag is set to 1, the received data is transferred to RDR, so the erroneous data can be read. Switching Modes: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE to 0 and setting TE to 1. The RDRF, PER, or ORER flag can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE to 0 and setting RE to 1. The TEND flag can be used to check that the transmit operation has been completed. Fixing Clock Output: When the GM bit is set to 1 in SMR, clock output can be fixed by means of the CKE1 and CKE0 bits in SCR. The minimum clock pulse width can be set to the specified width in this case. Figure 14.9 shows the timing for fixing clock output. In this example, GM = 1, CKE1 = 0, and the CKE0 bit is controlled.
Specified pulse width CKE1 value SCK Specified pulse width
SCR write (CKE0 = 0)
SCR write (CKE0 = 1)
Figure 14.9 Timing for Fixing Cock Output Interrupt Operations: The smart card interface has three interrupt sources: transmit-data-empty (TXI), transmit/receive-error (ERI), and receive-data-full (RXI). The transmit-end interrupt request (TEI) is not available in smart card mode. A TXI interrupt is requested when the TEND flag is set to 1 in SSR. An RXI interrupt is requested when the RDRF flag is set to 1 in SSR. An ERI interrupt is requested when the ORER, PER, or ERS flag is set to 1 in SSR. These relationships are shown in table 14.8.
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14. Smart Card Interface
Table 14.8 Smart Card Interface Mode Operating States and Interrupt Sources
Operating State Transmit Mode Normal operation Error Receive Mode Normal operation Error Flag TEND ERS RDRF PER, ORER Enable Bit TIE RIE RIE RIE Interrupt Source TXI ERI RXI ERI DMAC Activation Available Not available Available Not available
Data Transfer by DMAC: The DMAC can be used to transmit and receive data in smart card mode, as in normal SCI operations. In transmit mode, when the TEND flag is set to 1 in SSR, the TDRE flag is set simultaneously, generating a TXI interrupt. If the TXI request is designated beforehand as a DMAC activation source, the DMAC will be activated by the TXI request and will transfer the next transmit data. This data transfer by the DMAC automatically clears the TDRE and TEND flags to 0. In the event of an error, the SCI automatically retransmits the same data, keeping the TEND flag cleared to 0 so that the DMAC is not activated. The SCI and DMAC will therefore automatically transmit the designated number of bytes, including retransmission when an error occurs. When an error occurs, the ERS flag is not cleared automatically, so the RIE bit should be set to 1 to enable the error to generate an ERI request, and the ERI interrupt handler should clear ERS. When using the DMAC to transmit or receive, first set up and enable the DMAC, then make SCI settings. DMAC settings are described in section 7, DMA controller. In receive operations, an RXI interrupt is requested when the RDRF flag is set to 1 in SSR. If the RXI request is designated beforehand as a DMAC activation source, the DMAC will be activated by the RXI request and will transfer the received data. This data transfer by the DMAC automatically clears the RDRF flag to 0. When an error occurs, the RDRF flag is not set and an error flag is set instead. The DMAC is not activated. The ERI interrupt request is directed to the CPU. The ERI interrupt handler should clear the error flags. Examples of Operation in GSM Mode: When switching between smart card interface mode and software standby mode, use the following procedures to maintain the clock duty cycle. * Switching from smart card interface mode to software standby mode 1. Set the P94 data register (DR) and data direction register (DDR) to the values for the fixed output state in software standby mode.
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2. Write 0 in the TE and RE bits in the serial control register (SCR) to stop transmit/receive operations. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. 3. Write 0 in the CKE0 bit in SCR to stop the clock. 4. Wait for one serial clock cycle. During this period, the duty cycle is preserved and clock output is fixed at the specified level. 5. Write H'00 in the serial mode register (SMR) and smart card mode register (SCMR). 6. Make the transition to the software standby state. * Returning from software standby mode to smart card interface mode 1. Clear the software standby state. 2. Set the CKE1 bit in SCR to the value for the fixed output state at the start of software standby (the current P94 pin state). 3. Set smart card interface mode and output the clock. Clock signal generation is started with the normal duty cycle.
Software standby
Normal operation
Normal operation
123
4 56
1 2 3
Figure 14.10 Procedure for Stopping and Restarting the Clock Use the following procedure to secure the clock duty cycle after powering on. 1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the potential. 2. Fix at the output specified by the CKE1 bit in SCR. 3. Set SMR and SCMR, and switch to smart card interface mode operation. 4. Set the CKE0 bit to 1 in SCR to start clock output.
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14. Smart Card Interface
14.4
Usage Notes
The following points should be noted when using the SCI as a smart card interface. Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart card interface mode, the SCI operates on a base clock with a frequency of 372 times the transfer rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the 186th base clock pulse. The timing is shown in figure 14.11.
372 clocks 186 clocks 0 185 371 0 185 371 0
Internal base clock
Receive data (RxD)
Start bit
D0
D1
Synchronization sampling timing
Data sampling timing
Figure 14.11 Receive Data Sampling Timing in Smart Card Interface Mode The receive margin can therefore be expressed as follows. Receive margin in smart card interface mode:
M = (0.5 - 1 2N ) - (L - 0.5) F - D - 0.5 N (1 + F) x 100%
M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 372)
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D: L: F:
Clock duty cycle (D = 0 to 1.0) Frame length (L =10) Absolute deviation of clock frequency
From the above equation, if F = 0 and D = 0.5, the receive margin is as follows. When D = 0.5 and F = 0:
M = (0.5 - 1/2 x 372) x 100% = 49.866%
Retransmission: Retransmission is performed by the SCI in receive mode and transmit mode as described below. * Retransmission when SCI is in Receive Mode Figure 14.12 illustrates retransmission when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit is automatically set to 1. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The PER bit should be cleared to 0 in SSR before the next parity bit sampling timing. 2. The RDRF bit in SSR is not set for the frame in which the error has occurred. 3. If no error is found when the received parity bit is checked, the PER bit is not set to 1 in SSR. 4. If no error is found when the received parity bit is checked, the receive operation is assumed to have been completed normally, and the RDRF bit is automatically set to 1 in SSR. If the RIE bit in SCR is set to the enable state, an RXI interrupt is requested. If RXI is enabled as a DMA transfer activation source, the RDR contents can be read automatically. When the DMAC reads the RDR data, the RDRF flag is automatically cleared to 0. 5. When a normal frame is received, the data pin is held in the high-impedance state at the error signal transmission timing.
Frame n
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransmitted frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE)
Frame n+1
Ds D0 D1 D2 D3 D4
RDRF [2] PER [1] [3] [4]
Figure 14.12 Retransmission in SCI Receive Mode
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14. Smart Card Interface
* Retransmission when SCI is in Transmit Mode Figure 14.13 illustrates retransmission when the SCI is in transmit mode. 6. If an error signal is sent back from the receiving device after transmission of one frame is completed, the ERS bit is set to 1 in SSR. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The ERS bit should be cleared to 0 in SSR before the next parity bit sampling timing. 7. The TEND bit in SSR is not set for the frame for which the error signal was received. 8. If an error signal is not sent back from the receiving device, the ERS flag is not set in SSR. 9. If an error signal is not sent back from the receiving device, transmission of one frame, including retransmission, is assumed to have been completed, and the TEND bit is set to 1 in SSR. If the TIE bit in SCR is set to the enable state, a TXI interrupt is requested. If TXI is enabled as a DMA transfer activation source, the next data can be written in TDR automatically. When the DMAC writes data in TDR, the TDRE bit is automatically cleared to 0.
Frame n
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransmitted frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE)
Frame n+1
Ds D0 D1 D2 D3 D4
TDRE Transfer from TDR to TSR TEND [7] ERS [6] [8] [9] Transfer from TDR to TSR Transfer from TDR to TSR
Figure 14.13 Retransmission in SCI Transmit Mode Note on Block Transfer Mode Support: The smart card interface installed in the H8/3006 and H8/3007 support an IC card (smart card) interface with provision for ISO/IEC7816-3 T=0 (character transmission). Therefore, block transfer operations are not supported (error signal transmission, detection, and automatic data retransmission are not performed).
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15. A/D Converter
Section 15 A/D Converter
15.1 Overview
The H8/3006 and H8/3007 include a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. When the A/D converter is not used, it can be halted independently to conserve power. For details see section 19.6, Module Standby Function. The H8/3006 and H8/3007 support 70/134-state conversion as a high-speed conversion mode. Note that it differs in this respect from the H8/3048 Group, which supports 134/266-state conversion. 15.1.1 Features
A/D converter features are listed below. * 10-bit resolution * Eight input channels * Selectable analog conversion voltage range The analog voltage conversion range can be programmed by input of an analog reference voltage at the VREF pin. * High-speed conversion Conversion time: maximum 3.5 s per channel (with 20 MHz system clock) * Two conversion modes Single mode: A/D conversion of one channel Scan mode: continuous conversion on one to four channels * Four 16-bit data registers A/D conversion results are transferred for storage into data registers corresponding to the channels. * Sample-and-hold function * Three conversion start sources The A/D converter can be activated by software, an external trigger, or an 8-bit timer compare match. * A/D interrupt requested at end of conversion At the end of A/D conversion, an A/D end interrupt (ADI) can be requested. * DMA controller (DMAC) activation The DMAC can be activated at the end of A/D conversion.
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15. A/D Converter
15.1.2
Block Diagram
Figure 15.1 shows a block diagram of the A/D converter.
On-chip data bus
Module data bus
AVCC VREF AVSS 10-bit D/A
Successiveapproximations register
ADDRC
ADDRD
ADDRA
ADDRB
ADCSR
AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 ADTRG Compare match A0 ADTE 8-bit timer 8TCSR0 Legend: ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: Analog multiplexer
+ - Comparator Control circuit Sample-andhold circuit /8 /4
ADCR
ADI interrupt signal
A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D
Figure 15.1 A/D Converter Block Diagram
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Bus interface
15. A/D Converter
15.1.3
Pin Configuration
Table 15.1 summarizes the A/D converter's input pins. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power supply for the analog circuits in the A/D converter. VREF is the A/D conversion reference voltage. Table 15.1 A/D Converter Pins
Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Abbreviation I/O AVCC AVSS VREF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Input Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Group 1 analog inputs Function Analog power supply Analog ground and reference voltage Analog reference voltage Group 0 analog inputs
A/D external trigger input pin ADTRG
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15. A/D Converter
15.1.4
Register Configuration
Table 15.2 summarizes the A/D converter's registers. Table 15.2 A/D Converter Registers
Address* H'FFFE0 H'FFFE1 H'FFFE2 H'FFFE3 H'FFFE4 H'FFFE5 H'FFFE6 H'FFFE7 H'FFFE8 H'FFFE9
1
Name A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register
Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR
R/W R R R R R R R R R/(W)* R/W
2
Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'7E
Notes: 1. Lower 20 bits of the address in advanced mode. 2. Only 0 can be written in bit 7, to clear the flag.
15.2
15.2.1
Bit ADDRn
Register Descriptions
A/D Data Registers A to D (ADDRA to ADDRD)
15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Initial value Read/Write (n = A to D)
A/D conversion data 10-bit data giving an A/D conversion result
Reserved bits
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D
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15. A/D Converter
data register are reserved bits that are always read as 0. Table 15.3 indicates the pairings of analog input channels and A/D data registers. The CPU can always read the A/D data registers. The upper byte can be read directly, but the lower byte is read through a temporary register (TEMP). For details see section 15.3, CPU Interface. The A/D data registers are initialized to H'0000 by a reset and in standby mode. Table 15.3 Analog Input Channels and A/D Data Registers
Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD
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15. A/D Converter
15.2.2
Bit
A/D Control/Status Register (ADCSR)
7 ADF 0 R/(W) * 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W
Initial value Read/Write
Channel select 2 to 0 These bits select analog input channels Clock select Selects the A/D conversion time Scan mode Selects single mode or scan mode A/D start Starts or stops A/D conversion A/D interrupt enable Enables and disables A/D end interrupts A/D end flag Indicates end of A/D conversion Note: * Only 0 can be written, to clear the flag.
ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter. ADCSR is initialized to H'00 by a reset and in standby mode. Bit 7A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7 ADF 0 Description [Clearing conditions] * * 1 * * Read ADF when ADF =1, then write 0 in ADF. DMAC activated by ADI interrupt. Single mode: A/D conversion ends Scan mode: A/D conversion ends in all selected channels (Initial value)
[Setting conditions]
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15. A/D Converter
Bit 6A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion.
Bit 6 ADIE 0 1 Description A/D end interrupt request (ADI) is disabled A/D end interrupt request (ADI) is enabled (Initial value)
Bit 5A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin, or by an 8-bit timer compare match.
Bit 5 ADST 0 1 Description A/D conversion is stopped (Initial value)
Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends. Scan mode: A/D conversion starts and continues, cycling among the selected channels, until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode.
Bit 4Scan Mode (SCAN): Selects single mode or scan mode. For further information on operation in these modes, see section 15.4, Operation. Clear the ADST bit to 0 before switching the conversion mode.
Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value)
Bit 3Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before switching the conversion time.
Bit 3 CKS 0 1 Description Conversion time = 134 states (maximum) Conversion time = 70 states (maximum) (Initial value)
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15. A/D Converter
Bits 2 to 0Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection.
Group Selection CH2 0 CH1 0 Channel Selection CH0 0 1 1 0 1 1 0 0 1 1 0 1 Single Mode AN0 (Initial value) AN1 AN2 AN3 AN4 AN5 AN6 AN7 Description Scan Mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7
15.2.3
Bit
A/D Control Register (ADCR)
7 TRGE 0 R/W 6 1 5 1 4 1 3 1 Reserved bits Trigger enable Enables or disables starting of A/D conversion by an external trigger or 8-bit timer compare match 2 1 1 -- 1 -- 0 0 R/W
Initial value Read/Write
ADCR is an 8-bit readable/writable register that enables or disables starting of A/D conversion by external trigger input or an 8-bit timer compare match signal. ADCR is initialized to H'7E by a reset and in standby mode.
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15. A/D Converter
Bit 7Trigger Enable (TRGE): Enables or disables starting of A/D conversion by an external trigger or 8-bit timer compare match.
Bit 7 TRGE 0 1 Description Starting of A/D conversion by an external trigger or 8-bit timer compare match is disabled A/D conversion is started at the falling edge of the external trigger signal (ADTRG) or by an 8-bit timer compare match (Initial value)
External trigger pin and 8-bit timer selection are performed by the 8-bit timer. For details, see section 10, 8-Bit Timers. Bits 6 to 1Reserved: These bits cannot be modified and are always read as 1. Bit 0Reserved: This bit can be read or written, but should not be set to 1.
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15. A/D Converter
15.3
CPU Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows. When the upper byte is read, the upper-byte value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading an A/D data register, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 15.2 shows the data flow for access to an A/D data register.
Upper-byte read
CPU (H'AA)
Module data bus Bus interface
TEMP (H'40)
ADDRnH (H'AA)
ADDRnL (H'40)
Lower-byte read
CPU (H'40)
Module data bus Bus interface
TEMP (H'40)
ADDRnH (H'AA) Note: n = A to D
ADDRnL (H'40)
Figure 15.2 A/D Data Register Access Operation (Reading H'AA40)
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15. A/D Converter
15.4
Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 15.4.1 Single Mode (SCAN = 0)
Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when conversion ends. When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF. When the mode or analog input channel must be switched during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the mode or channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 15.3 shows a timing diagram for this example. 1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The routine reads ADCSR, then writes 0 in the ADF flag. 6. The routine reads and processes the conversion result (ADDRB). 7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated.
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Set *
ADIE A/D conversion starts Clear * Clear * Set * Set *
15. A/D Converter
ADST
ADF Idle
State of channel 0 (AN 0) Idle
A/D conversion (1)
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Idle
A/D conversion (2)
State of channel 1 (AN 1) Idle
Idle
State of channel 2 (AN 2) Idle
State of channel 3 (AN 3)
ADDRA Read conversion result A/D conversion result (1) Read conversion result A/D conversion result (2)
ADDRB
ADDRC
ADDRD
Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Note: * Vertical arrows ( ) indicate instructions executed by software.
15. A/D Converter
15.4.2
Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the mode or analog input channel selection must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are described next. Figure 15.4 shows a timing diagram for this example. 1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into ADDRA. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI interrupt is requested at this time. 5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0).
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Continuous A/D conversion Set *1 Clear*1
15. A/D Converter
ADST Clear*1 A/D conversion time Idle
A/D conversion (1)
ADF Idle A/D conversion (4) Idle
State of channel 0 (AN 0) Idle A/D conversion (2) Idle
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A/D conversion (5)*2 Idle Idle A/D conversion (3) Idle Idle Transfer A/D conversion result (1) A/D conversion result (4) A/D conversion result (2) A/D conversion result (3)
State of channel 1 (AN 1)
State of channel 2 (AN 2)
State of channel 3 (AN 3)
ADDRA
ADDRB
ADDRC
Figure 15.4 Example of A/D Converter Operation (Scan Mode, Channels 3 AN0 to AN2 Selected)
ADDRD
Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored.
15. A/D Converter
15.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D conversion timing. Table 15.4 indicates the A/D conversion time. As indicated in figure 15.5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 15.4. In scan mode, the values given in table 15.4 apply to the first conversion. In the second and subsequent conversions the conversion time is fixed at 128 states when CKS = 0 or 66 states when CKS = 1.
(1)
Address bus
(2)
Write signal Input sampling timing
ADF tD t SPL t CONV Legend: (1): ADCSR write cycle (2): ADCSR address tD : Synchronization delay t SPL : Input sampling time t CONV : A/D conversion time
Figure 15.5 A/D Conversion Timing
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15. A/D Converter
Table 15.4 A/D Conversion Time (Single Mode)
CKS = 0 Symbol Synchronization delay Input sampling time A/D conversion time tD tSPL tCONV Min 6 131 Typ 31 Max 9 134 Min 4 69 CKS = 1 Typ 15 Max 5 70
Note: Values in the table are numbers of states.
15.4.4
External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR and the 8-bit timer's ADTE bit is cleared to 0, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit had been set to 1 by software. Figure 15.6 shows the timing.
ADTRG
Internal trigger signal
ADST A/D conversion
Figure 15.6 External Trigger Input Timing
15.5
Interrupts
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. The ADI interrupt request can be designated as a DMAC activation source. In this case, an interrupt request is not sent to the CPU.
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15. A/D Converter
15.6
Usage Notes
When using the A/D converter, note the following points: 1. Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input pins should be in the range AVSS ANn VREF. 2. Relationships of AVCC and AVSS to VCC and VSS: AVCC, AVSS, VCC, and VSS should be related as follows: AVSS = VSS. AVCC and AVSS must not be left open, even if the A/D converter is not used. 3. VREF Programming Range: The reference voltage input at the VREF pin should be in the range VREF AVCC. 4. Note on Board Design: In board layout, separate the digital circuits from the analog circuits as much as possible. Particularly avoid layouts in which the signal lines of digital circuits cross or closely approach the signal lines of analog circuits. Induction and other effects may cause the analog circuits to operate incorrectly, or may adversely affect the accuracy of A/D conversion. The analog input signals (AN0 to AN7), analog reference voltage (VREF), and analog supply voltage (AVCC) must be separated from digital circuits by the analog ground (AVSS). The analog ground (AVSS) should be connected to a stable digital ground (VSS) at one point on the board. 5. Note on Noise: To prevent damage from surges and other abnormal voltages at the analog input pins (AN0 to AN7) and analog reference voltage pin (VREF), connect a protection circuit like the one in figure 15.7 between AVCC and AVSS. The bypass capacitors connected to AVCC and VREF and the filter capacitors connected to AN0 to AN7 must be connected to AVSS. If filter capacitors like the ones in figure 15.7 are connected, the voltage values input to the analog input pins (AN0 to AN7) will be smoothed, which may give rise to error. Error can also occur if A/D conversion is frequently performed in scan mode so that the current that charges and discharges the capacitor in the sample-and-hold circuit of the A/D converter becomes greater than that input to the analog input pins via input impedance Rin. The circuit constants should therefore be selected carefully.
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15. A/D Converter
AV CC
VREF Rin*2
*1 *1
100 AN0 to AN7 0.1 F
AV SS
Notes: 1. 10 F 0.01 F
2. Rin: input impedance
Figure 15.7 Example of Analog Input Protection Circuit Table 15.5 Analog Input Pin Ratings
Item Analog input capacitance Allowable signal-source impedance Note: * min max 20 10* Unit pF k
When conversion time 134 states, VCC = 4.0 V to 5.5 V and 13 MHz. For details see section 20, Electrical Characteristics.
10 k AN0 to AN7 To A/D converter 20 pF
Figure 15.8 Analog Input Pin Equivalent Circuit Note: Numeric values are approximate, except in table 15.5
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15. A/D Converter
6. A/D Conversion Accuracy Definitions: A/D conversion accuracy in the H8/3006 and H8/3007 are defined as follows: Resolution Digital output code length of A/D converter Offset error Deviation from ideal A/D conversion characteristic of analog input voltage required to raise digital output from minimum voltage value 0000000000 to 0000000001 (figure 15.10) Full-scale error Deviation from ideal A/D conversion characteristic of analog input voltage required to raise digital output from 1111111110 to 1111111111 (figure 15.10) Quantization error Intrinsic error of the A/D converter; 1/2 LSB (figure 15.9) Nonlinearity error Deviation from ideal A/D conversion characteristic in range from zero volts to full scale, exclusive of offset error, full-scale error, and quantization error. Absolute accuracy Deviation of digital value from analog input value, including offset error, full-scale error, quantization error, and nonlinearity error.
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15. A/D Converter
Digital output
111 110 101 100 011 010 001 000
Ideal A/D conversion characteristic
Quantization error
1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage
Figure 15.9 A/D Converter Accuracy Definitions (1)
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15. A/D Converter
Full-scale error
Digital output
Ideal A/D conversion characteristic
Nonlinearity error
Actual A/D conversion characteristic FS Offset error Analog input voltage
Figure 15.10 A/D Converter Accuracy Definitions (2) 7. Allowable Signal-Source Impedance: The analog inputs of the H8/3006 and H8/3007 are designed to assure accurate conversion of input signals with a signal-source impedance not exceeding 10 k. The reason for this rating is that it enables the input capacitor in the sampleand-hold circuit in the A/D converter to charge within the sampling time. If the sensor output impedance exceeds 10 k, charging may be inadequate and the accuracy of A/D conversion cannot be guaranteed. If a large external capacitor is provided in single mode, then the internal 10-k input resistance becomes the only significant load on the input. In this case the impedance of the signal source is not a problem. A large external capacitor, however, acts as a low-pass filter. This may make it impossible to track analog signals with high dv/dt (e.g. a variation of 5 mV/s) (figure 15.11). To convert high-speed analog signals or to use scan mode, insert a low-impedance buffer.
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15. A/D Converter
8. Effect on Absolute Accuracy: Attaching an external capacitor creates a coupling with ground, so if there is noise on the ground line, it may degrade absolute accuracy. The capacitor must be connected to an electrically stable ground, such as AVSS. If a filter circuit is used, be careful of interference with digital signals on the same board, and make sure the circuit does not act as an antenna.
H8/3006 and H8/3007 Sensor output impedance Sensor input Up to 10 k Cin = 15 pF Equivalent circuit of A/D converter 10 k
Low-pass filter C Up to 0.1F
20 pF
Figure 15.11 Analog Input Circuit (Example)
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16. D/A Converter
Section 16 D/A Converter
16.1 Overview
The H8/3006 and H8/3007 include a D/A converter with two channels. 16.1.1 Features
D/A converter features are listed below. * Eight-bit resolution * Two output channels * Conversion time: maximum 10 s (with 20-pF capacitive load) * Output voltage: 0 V to VREF * D/A outputs can be sustained in software standby mode
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16. D/A Converter
16.1.2
Block Diagram
Figure 16.1 shows a block diagram of the D/A converter.
Module data bus
VREF
DA 0 DA 1 AVSS
8-bit D/A
Legend: D/A control register DACR: DADR0: D/A data register 0 DADR1: D/A data register 1 DASTCR: D/A standby control register
Control circuit
Figure 16.1 D/A Converter Block Diagram 16.1.3 Pin Configuration
Table 16.1 summarizes the D/A converter's input and output pins. Table 16.1 D/A Converter Pins
Pin Name Analog power supply pin Analog ground pin Analog output pin 0 Analog output pin 1 Reference voltage input pin Abbreviation I/O AVCC AVSS DA0 DA1 VREF Input Input Output Output Input Function Analog power supply and reference voltage Analog ground and reference voltage Analog output, channel 0 Analog output, channel 1 Analog reference voltage
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DASTCR
AVCC
DADR0
DADR1
DACR
Bus interface
On-chip data bus
16. D/A Converter
16.1.4
Register Configuration
Table 16.2 summarizes the D/A converter's registers. Table 16.2 D/A Converter Registers
Address* H'FFF9C H'FFF9D H'FFF9E H'EE01A Note: * Name D/A data register 0 D/A data register 1 D/A control register D/A standby control register Abbreviation DADR0 DADR1 DACR DASTCR R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'1F H'FE
Lower 20 bits of the address in advanced mode.
16.2
16.2.1
Bit
Register Descriptions
D/A Data Registers 0 and 1 (DADR0/1)
7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Initial value Read/Write
The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the data to be converted. When analog output is enabled, the D/A data register values are constantly converted and output at the analog output pins. The D/A data registers are initialized to H'00 by a reset and in standby mode. When the DASTE bit is set to 1 in the D/A standby control register (DASTCR), the D/A registers are not initialized in software standby mode.
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16. D/A Converter
16.2.2
Bit
D/A Control Register (DACR)
7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 1 3 1 2 1 1 1 0 1
Initial value Read/Write
D/A enable Controls D/A conversion D/A output enable 0 Controls D/A conversion and analog output D/A output enable 1 Controls D/A conversion and analog output
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter. DACR is initialized to H'1F by a reset and in standby mode. When the DASTE bit is set to 1 in DASTCR, the DACR is not initialized in software standby mode. Bit 7D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output.
Bit 7 DAOE1 0 1 Description DA1 analog output is disabled Channel-1 D/A conversion and DA1 analog output are enabled
Bit 6D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output.
Bit 6 DAOE0 0 1 Description DA0 analog output is disabled Channel-0 D/A conversion and DA0 analog output are enabled
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16. D/A Converter
Bit 5D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1. When the DAE bit is cleared to 0, analog conversion is controlled independently in channels 0 and 1. When the DAE bit is set to 1, analog conversion is controlled together in channels 0 and 1. Output of the conversion results is always controlled independently by DAOE0 and DAOE1.
Bit 7 Bit 6 Bit 5 DAOE1 DAOE0 DAE 0 0 1 0 1 1 0 0 1 1 Description D/A conversion is disabled in channels 0 and 1 D/A conversion is enabled in channel 0 D/A conversion is disabled in channel 1 D/A conversion is enabled in channels 0 and 1 D/A conversion is disabled in channel 0 D/A conversion is enabled in channel 1 D/A conversion is enabled in channels 0 and 1 D/A conversion is enabled in channels 0 and 1
When the DAE bit is set to 1, even if bits DAOE0 and DAOE1 in DACR and the ADST bit in ADCSR are cleared to 0, the same current is drawn from the analog power supply as during A/D and D/A conversion. Bits 4 to 0Reserved: These bits cannot be modified and are always read as 1. 16.2.3 D/A Standby Control Register (DASTCR)
DASTCR is an 8-bit readable/writable register that enables or disables D/A output in software standby mode.
Bit Initial value Read/Write 7 1 6 1 5 1 4 1 Reserved bits D/A standby enable Enables or disables D/A output in software standby mode 3 1 2 1 1 1 0 DASTE 0 R/W
DASTCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 1Reserved: These bits cannot be modified and are always read as 1.
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16. D/A Converter
Bit 0D/A Standby Enable (DASTE): Enables or disables D/A output in software standby mode.
Bit 0 DASTE 0 1 Description D/A output is disabled in software standby mode D/A output is enabled in software standby mode (Initial value)
16.3
Operation
The D/A converter has two built-in D/A conversion circuits that can perform conversion independently. D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value is modified, conversion of the new data begins immediately. The conversion results are output when bits DAOE0 and DAOE1 are set to 1. An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 16.2. 1. Data to be converted is written in DADR0. 2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA0 becomes an output pin. The converted result is output after the conversion time. DADR contents The output value is x VREF 256 Output of this conversion result continues until the value in DADR0 is modified or the DAOE0 bit is cleared to 0. 3. If the DADR0 value is modified, conversion starts immediately, and the result is output after the conversion time. 4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin.
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16. D/A Converter
DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle
Address
DADR0 DAOE0 DA 0
Conversion data 1
Conversion data 2
High-impedance state t DCONV Legend: t DCONV : D/A conversion time
Conversion result 1 t DCONV
Conversion result 2
Figure 16.2 Example of D/A Converter Operation
16.4
D/A Output Control
In the H8/3006 and H8/3007, D/A converter output can be enabled or disabled in software standby mode. When the DASTE bit is set to 1 in DASTCR, D/A converter output is enabled in software standby mode. The D/A converter registers retain the values they held prior to the transition to software standby mode. When D/A output is enabled in software standby mode, the reference supply current is the same as during normal operation.
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16. D/A Converter
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17. RAM
Section 17 RAM
17.1 Overview
The H8/3007 has 4 kbytes of high-speed static RAM on-chip. The H8/3006 has 2 kbytes. The RAM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, making the RAM useful for rapid data transfer. The on-chip RAM of the H8/3007 is assigned to addresses H'FEF20 to H'FFF1F in modes 1 and 2, and to addresses H'FFEF20 to H'FFFF1F in modes 3 and 4. The on-chip RAM of the H8/3006 are assigned to addresses H'FF720 to H'FFF1F in modes 1 and 2, and to addresses H'FFF720 to H'FFFF1F in modes 3 and 4. The RAM enable bit (RAME) in the system control register (SYSCR) can enable or disable the on-chip RAM. 17.1.1 Block Diagram
Figure 17.1 shows a block diagram of the on-chip RAM.
On-chip data bus (upper 8 bits)
On-chip data bus (lower 8 bits)
Bus interface
SYSCR
H'FEF20* H'FEF22*
H'FEF21* H'FEF23*
On-chip RAM
H'FFF1E* Even addresses Legend: SYSCR: System control register
H'FFF1F* Odd addresses
Note: * This example is of the H8/3007 operating in mode 1 and 2. The lower 20 bits of the address are shown.
Figure 17.1 RAM Block Diagram
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17. RAM
17.1.2
Register Configuration
The on-chip RAM is controlled by SYSCR. Table 17.1 gives the address and initial value of SYSCR. Table 17.1 System Control Register
Address* H'EE012 Note: * Name System control register Abbreviation SYSCR R/W R/W Initial Value H'09
Lower 20 bits of the address in advanced mode.
17.2
Bit
System Control Register (SYSCR)
7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 SSOE 0 R/W 0 RAME 1 R/W
Initial value Read/Write
RAM enable bit Enables or disables on-chip RAM Software standby output port enable NMI edge select User bit enable Standby timer select 2 to 0 Software standby
One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3, System Control Register (SYSCR).
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17. RAM
Bit 0RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized at the rising edge of the input at the RES pin. It is not initialized in software standby mode.
Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value)
17.3
Operation
When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to addresses H'FEF20 to H'FFF1F in the H8/3007 in modes 1 and 2, and to addresses H'FFEF20 to H'FFFF1F in the H8/3007 in modes 3 and 4, are directed to the on-chip RAM. In the H8/3006, accesses to addresses H'FF720 to H'FFF1F in modes 1 and 2, to addresses H'FFF720 to H'FFFF1F in modes 3 and 4, are directed to the on-chip RAM. In modes 1 to 4, when the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written and read by word access. It can also be written and read by byte access. Byte data is accessed in two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed in two states using all 16 bits of the data bus.
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17. RAM
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18. Clock Pulse Generator
Section 18 Clock Pulse Generator
18.1 Overview
The H8/3006 and H8/3007 have a built-in clock pulse generator (CPG) that generates the system clock () and other internal clock signals (/2 to /4096). After duty adjustment, a frequency divider divides the clock frequency to generate the system clock (). The system clock is output at 1 the pin* and furnished as a master clock to prescalers that supply clock signals to the on-chip supporting modules. Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the 2 frequency divider by settings in a division control register (DIVCR)* . Power consumption in the chip is reduced in almost direct proportion to the frequency division ratio. Notes: 1. Usage of the pin differs depending on the chip operating mode and the PSTOP bit setting in the module standby control register (MSTCR). For details, see section 19.7, System Clock Output Disabling Function. 2. The division ratio of the frequency divider can be changed dynamically during operation. The clock output at the pin also changes when the division ratio is changed. The frequency output at the pin is shown below. = EXTAL x n where, EXTAL:Frequency of crystal resonator or external clock signal n: 18.1.1 Block Diagram Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8)
Figure 18.1 shows a block diagram of the clock pulse generator.
CPG XTAL Oscillator EXTAL
Duty adjustment circuit
Frequency divider
Prescalers
Division control register
Data bus
/2 to /4096
Figure 18.1 Block Diagram of Clock Pulse Generator
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18. Clock Pulse Generator
18.2
Oscillator Circuit
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock signal. 18.2.1 Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as in the example in figure 18.2. The damping resistance Rd should be selected according to table 18.1. An AT-cut parallelresonance crystal should be used.
C L1 EXTAL
XTAL Rd C L2 C L1 = C L2 = 10 pF to 22 pF
Figure 18.2 Connection of Crystal Resonator (Example) Table 18.1 Damping Resistance Value
Damping Resistance Value 2 Rd () 1k Frequency f (MHz) 2Note: A crystal resonator between 2 MHz and 20 MHz can be used. If the chip is to be operated at less than 2 MHz, the on-chip frequency divider should be used. (A crystal resonator of less than 2 MHz cannot be used.)
Crystal Resonator: Figure 18.3 shows an equivalent circuit of the crystal resonator. The crystal resonator should have the characteristics listed in table 18.2.
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18. Clock Pulse Generator
CL L XTAL Rs EXTAL
C0
AT-cut parallel-resonance type
Figure 18.3 Crystal Resonator Equivalent Circuit Table 18.2 Crystal Resonator Parameters
Frequency (MHz) Rs max () Co (pF) 2 500 4 120 8 80 10 70 12 60 7 pF max 16 50 18 40 20 40
Use a crystal resonator with a frequency equal to the system clock frequency (). Notes on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 18.4. When the board is designed, the crystal resonator and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins.
Avoid C L2 Signal A Signal B H8/3006 and H8/3007 XTAL
EXTAL C L1
Figure 18.4 Example of Incorrect Board Design
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18. Clock Pulse Generator
18.2.2
External Clock Input
Circuit Configuration: An external clock signal can be input as shown in the examples in figure 18.5. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. If the stray capacitance at the XTAL pin exceeds 10 pF, use configuration b instead and hold the clock high in standby mode.
EXTAL
External clock input
XTAL
Open
a. XTAL pin left open
EXTAL
External clock input
XTAL
b. Complementary clock input at XTAL pin
Figure 18.5 External Clock Input (Examples) External Clock: The external clock frequency should be equal to the system clock frequency when not divided by the on-chip frequency divider. Table 18.3 shows the clock timing, figure 18.6 shows the external clock input timing, and figure 18.7 shows the external clock output settling delay timing. When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the on-chip oscillator and duty adjustment circuit. When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external devices after the external clock settling time (tDEXT) has passed after the clock input. The system must remain reset with the reset signal low during tDEXT, while the clock output is unstable.
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18. Clock Pulse Generator
Table 18.3 Clock Timing
VCC = 2.7 V to 5.5 V Item Symbol Min 40 40 0.4 80 tCH tDEXT* 0.4 80 500 Max 10 10 0.6 0.6 VCC = 3.0 V to 5.5 V Min 30 30 0.4 80 0.4 80 500 Max 8 8 0.6 0.6 VCC = 5.0 V 10% Min 15 15 0.4 80 0.4 80 500 Max 5 5 0.6 0.6 Unit Test Conditions ns ns ns ns tcyc ns tcyc ns s 5 MHz Figure 20.3 < 5 MHz 5 MHz < 5 MHz Figure 18.7 Figure 18.6
External clock input tEXL low pulse width External clock input tEXH high pulse width External clock rise time External clock fall time Clock low pulse width Clock high pulse width External clock output settling delay time Note: * tEXr tEXf tCL
tDEXT includes a 10 tcyc of RES pulse width (tRESW).
tEXH
tEXL
VCC x 0.7
EXTAL VCC x 0.5
0.3 V
tEXr tEXf
Figure 18.6 External Clock Input Timing
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18. Clock Pulse Generator
VCC
STBY EXTAL
VIH
(internal or external) RES tDEXT* Note: * tDEXT includes a 10 tcyc RES pulse width (tRESW).
Figure 18.7 External Clock Output Settling Delay Timing
18.3
Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate .
18.4
Prescalers
The prescalers divide the system clock () to generate internal clocks (/2 to /4096).
18.5
Frequency Divider
The frequency divider divides the duty-adjusted clock signal to generate the system clock (). The frequency division ratio can be changed dynamically by modifying the value in DIVCR, as described below. Power consumption in the chip is reduced in almost direct proportion to the frequency division ratio. The system clock generated by the frequency divider can be output at the pin.
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18. Clock Pulse Generator
18.5.1
Register Configuration
Table 18.4 summarizes the frequency division register. Table 18.4 Frequency Division Register
Address* H'EE01B Note: * Name Division control register Abbreviation DIVCR R/W R/W Initial Value H'FC
Lower 20 bits of the address in advanced mode.
18.5.2
Division Control Register (DIVCR)
DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency divider.
Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 1 2 1 1 DIV1 0 R/W 0 DIV0 0 R/W
Reserved bits Divide bits 1 and 0 These bits select the frequency division ratio
DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 2Reserved: These bits cannot be modified and are always read as 1. Bits 1 and 0Divide (DIV1, DIV0): These bits select the frequency division ratio, as follows.
Bit 1 DIV1 0 Bit 0 DIV0 0 1 1 0 1 Frequency Division Ratio 1/1 1/2 1/4 1/8 (Initial value)
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18. Clock Pulse Generator
18.5.3
Usage Notes
The DIVCR setting changes the frequency, so note the following points. * Select a frequency division ratio that stays within the assured operation range specified for the clock cycle time tcyc in the AC electrical characteristics. Set min to the lower limit of the operating frequency range, and ensure that does not fall below this lower limit. * All on-chip module operations are based on . Note that the timing of timer operations, serial communication, and other time-dependent processing differs before and after any change in the division ratio. The waiting time for exit from software standby mode also changes when the division ratio is changed. For details, see section 19.4.3, Selection of Waiting Time for Exit from Software Standby Mode.
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19. Power-Down State
Section 19 Power-Down State
19.1 Overview
The H8/3006 and H8/3007 have a power-down state that greatly reduces power consumption by halting the CPU, and a module standby function that reduces power consumption by selectively halting on-chip modules. The power-down state includes the following three modes: * Sleep mode * Software standby mode * Hardware standby mode The module standby function can halt on-chip supporting modules independently of the powerdown state. The modules that can be halted are the 16-bit timer, 8-bit timer, SCI0, SCI1, SCI2, DMAC, DRAM interface, and A/D converter. Table 19.1 indicates the methods of entering and exiting the power-down modes and module standby mode, and gives the status of the CPU and on-chip supporting modules in each mode.
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State CPU Other SCI0 Active * RES * STBY Active Active Active Active Held output Held * Interrupt SCI1 SCI2 A/D Modules RAM output *4 Ports Conditions Registers DMAC Timer Active Active Active Active Interface Timer DRAM 8-Bit I/O Exiting 16-Bit clock
Mode/
Entering
Function Conditions
Clock CPU
Sleep
SLEEP instruc- Active Halted Held
mode
tion executed
while SSBY = 0
19. Power-Down State
in SYSCR Halted Halted Halted and reset reset reset reset reset and and and and output Halted Halted Halted Halted and reset and reset held*1 reset and and Halted Held Halted High Held * NMI * IRQ0 to IRQ2 * RES * STBY Halted and reset reset reset reset reset reset reset reset High impedance*2 * STBY * RES * Clear MSTCR bit to 0*5 and and and and and and and Halted Halted Halted Halted Halted Halted Halted Held*3 High impedance High * STBY impedance * RES
Software SLEEP instruc- Halted Halted Held
standby
tion executed
mode
while SSBY = 1
in SYSCR
Hardware Low input at mined reset Halted*2 Halted*2 Halted*2 Halted*2 Halted*2 Halted*2 Halted*2 Halted*2 Active and reset held*1 reset reset reset reset reset reset and and and and and and and and
Halted Halted Undeter- Halted
standby
STBY pin
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mode
Module
Corresponding Active Active
standby
bit set to 1 in
MSTCRH and
MSTCRL
Notes: 1. RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their previous states.
2. State in which the corresponding MSTCR bit was set to 1. For details see section 19.2.2, Module Standby Control Register H (MSTCRH) and section 19.2.3,
Module Standby Control Register L (MSTCRL).
Table 19.1 Power-Down State and Module Standby Function
3. The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware standby mode.
4. When P67 is used as the output pin.
5. When a MSTCR bit is set to 1, the registers of the corresponding on-chip supporting module are initialized. To restart the module, first clear the MSTCR bit to 0,
then set up the module registers again.
Legend:
SYSCR:
System control register
SSBY:
Software standby bit
MSTCRH: Module standby control register H
MSTCRL: Module standby control register L
19. Power-Down State
19.2
Register Configuration
The H8/3006 and H8/3007 have a system control register (SYSCR) that controls the power-down state, and module standby control registers H (MSTCRH) and L (MSTCRL) that control the module standby function. Table 19.2 summarizes these registers. Table 19.2 Control Register
Address* H'EE012 H'EE01C H'EE01D Note: * Name System control register Module standby control register H Module standby control register L Abbreviation SYSCR MSTCRH MSTCRL R/W R/W R/W R/W Initial Value H'09 H'78 H'00
Lower 20 bits of the address in advanced mode.
19.2.1
Bit
System Control Register (SYSCR)
7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 SSOE 0 R/W 0 RAME 1 R/W RAM enable Software standby output port enable NMI edge select User bit enable Standby timer select 2 to 0 These bits select the waiting time of the CPU and peripheral functions Software standby Enables transition to software standby mode
Initial value Read/Write
SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY), bits 6 to 4 (STS2 to STS0), and bit 1 (SSOE) control the power-down state. For information on the other SYSCR bits, see section 3.3, System Control Register (SYSCR).
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19. Power-Down State
Bit 7--Software Standby (SSBY): Enables transition to software standby mode. When software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. To clear this bit, write 0.
Bit 7 SSBY 0 1 Description SLEEP instruction causes transition to sleep mode SLEEP instruction causes transition to software standby mode (Initial value)
Bits 6 to 4--Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the clock to settle when software standby mode is exited by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to the clock frequency so that the waiting time will be at least 7 ms (oscillation settling time). See table 19.3. If an external clock is used, any setting is permitted.
Bit 6 STS2 0 Bit 5 STS1 0 Bit 4 STS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Waiting time = 8,192 states Waiting time = 16,384 states Waiting time = 32,768 states Waiting time = 65,536 states Waiting time = 131,072 states Waiting time = 262,144 states Waiting time = 1,024 states Illegal setting (Initial value)
Bit 1--Software Standby Output Port Enable (SSOE): Specifies whether the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR, UCAS, LCAS, and RFSH) are kept as outputs or fixed high, or placed in the high-impedance state in software standby mode.
Bit 1 SSOE 0 1 Description In software standby mode, the address bus and bus control signals are (Initial value) all high-impedance In software standby mode, the address bus retains its output state and bus control signals are fixed high
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19. Power-Down State
19.2.2
Module Standby Control Register H (MSTCRH)
MSTCRH is an 8-bit readable/writable register that controls output of the system clock (). It also controls the module standby function, which places individual on-chip supporting modules in the standby state. Module standby can be designated for the SCI0, SCI1, SCI2.
Bit Initial value Read/Write 7 PSTOP 0 R/W 6 1 5 1 4 1 3 1 2 0 R/W 1 0 R/W 0 0 R/W
MSTPH2 MSTPH1 MSTPH0
Reserved bit clock stop Enables or disables output of the system clock
Module standby H2 to 0 These bits select modules to be placed in standby
MSTCRH is initialized to H'78 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7-- Clock Stop (PSTOP): Enables or disables output of the system clock ().
Bit 1 PSTOP 0 1 Description System clock output is enabled System clock output is disabled (Initial value)
Bits 6 to 3--Reserved: These bits cannot be modified and are always read as 1. Bit 2--Module Standby H2 (MSTPH2): Selects whether to place the SCI2 in standby.
Bit 2 MSTPH2 0 1 Description SCI2 operates normally SCI2 is in standby state (Initial value)
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19. Power-Down State
Bit 1--Module Standby H1 (MSTPH1): Selects whether to place the SCI1 in standby.
Bit 1 MSTPH1 0 1 Description SCI1 operates normally SCI1 is in standby state (Initial value)
Bit 0--Module Standby H0 (MSTPH0): Selects whether to place the SCI0 in standby.
Bit 0 MSTPH0 0 1 Description SCI0 operates normally SCI0 is in standby state (Initial value)
19.2.3
Module Standby Control Register L (MSTCRL)
MSTCRL is an 8-bit readable/writable register that controls the module standby function, which places individual on-chip supporting modules in the standby state. Module standby can be designated for the DMAC, 16-bit timer, DRAM interface, 8-bit timer, and A/D converter modules.
Bit Initial value Read/Write 7 MSTPL7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 MSTPL0 0 R/W
MSTPL5 MSTPL4 MSTPL3 MSTPL2
Module standby L7, L5 to L2, L0 These bits select modules to be placed in standby Reserved bits
MSTCRL is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode.
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19. Power-Down State
Bit 7--Module Standby L7 (MSTPL7): Selects whether to place the DMAC in standby.
Bit 7 MSTPL7 0 1 Description DMAC operates normally DMAC is in standby state (Initial value)
Bit 6--Reserved: This bit can be written and read. Bit 5--Module Standby L5 (MSTPL5): Selects whether to place the DRAM interface in standby.
Bit 5 MSTPL5 0 1 Description DRAM interface operates normally DRAM interface is in standby state (Initial value)
Bit 4--Module Standby L4 (MSTPL4): Selects whether to place the 16-bit timer in standby.
Bit 4 MSTPL4 0 1 Description 16-bit timer operates normally 16-bit timer is in standby state (Initial value)
Bit 3--Module Standby L3 (MSTPL3): Selects whether to place 8-bit timer channels 0 and 1 in standby.
Bit 3 MSTPL3 0 1 Description 8-bit timer channels 0 and 1 operate normally 8-bit timer channels 0 and 1 are in standby state (Initial value)
Bit 2--Module Standby L2 (MSTPL2): Selects whether to place 8-bit timer channels 2 and 3 in standby.
Bit 2 MSTPL2 0 1 Description 8-bit timer channels 2 and 3 operate normally 8-bit timer channels 2 and 3 are in standby state Rev.5.00 Sep. 12, 2007 Page 561 of 764 REJ09B0396-0500 (Initial value)
19. Power-Down State
Bit 1--Reserved: This bit can be written and read. Bit 0--Module Standby L0 (MSTPL0): Selects whether to place the A/D converter in standby.
Bit 0 MSTPL0 0 1 Description A/D converter operates normally A/D converter is in standby state (Initial value)
19.3
19.3.1
Sleep Mode
Transition to Sleep Mode
When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal registers are retained. The DMA controller (DMAC), DRAM interface, and on-chip supporting modules do not halt in sleep mode. Modules which have been placed in standby by the module standby function, however, remain halted. 19.3.2 Exit from Sleep Mode
Sleep mode is exited by an interrupt, or by input at the RES or STBY pin. Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by an interrupt other than NMI if the interrupt is masked by interrupt priority settings and the settings of the I and UI bits in CCR, IPR. Exit by RES Input: Low input at the RES pin exits from sleep mode to the reset state. Exit by STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby mode.
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19. Power-Down State
19.4
19.4.1
Software Standby Mode
Transition to Software Standby Mode
To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in SYSCR. In software standby mode, current dissipation is reduced to an extremely low level because the CPU, clock, and on-chip supporting modules all halt. The DMAC and on-chip supporting modules are reset and halted. As long as the specified voltage is supplied, however, CPU register contents and on-chip RAM data are retained. The settings of the I/O ports and DRAM interface* are also held. When the WDT is used as a watchdog timer (WT/IT = 1), the TME bit must be cleared to 0 before setting SSBY. Also, when setting TME to 1, SSBY should be cleared to 0. Clear the BRLE bit in BRCR (inhibiting bus release) before making a transition to software standby mode. Note: * RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their previous states. 19.4.2 Exit from Software Standby Mode
Software standby mode can be exited by input of an external interrupt at the NMI, IRQ0, IRQ1, or IRQ2 pin, or by input at the RES or STBY pin. Exit by Interrupt: When an NMI, IRQ0, IRQ1, or IRQ2 interrupt request signal is received, the clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0 in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and interrupt exception handling begins. Software standby mode is not exited if the interrupt enable bits of interrupts IRQ0, IRQ1, and IRQ2 are cleared to 0, or if these interrupts are masked in the CPU. Exit by RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are supplied immediately to the entire chip. The RES signal must be held low long enough for the clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling. Exit by STBY Input: Low input at the STBY pin causes a transition to hardware standby mode.
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19. Power-Down State
19.4.3
Selection of Waiting Time for Exit from Software Standby Mode
Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows. Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to stabilize) is at least 7 ms. Table 19.3 indicates the waiting times that are selected by STS2 to STS0, DIV1, and DIV0 settings at various system clock frequencies. External Clock: Any values may be set. Table 19.3 Clock Frequency and Waiting Time for Clock to Settle
DIV1 DIV0 STS2 STS1 STS0 Waiting Time 0 0 0 0 0 8192 states 0 0 1 16384 states 0 1 0 32768 states 0 1 1 65536 states 1 0 0 131072 states 1 0 1 262144 states 1 1 0 1024 states 1 1 1 0 1 0 0 0 8192 states 0 0 1 16384 states 0 1 0 32768 states 0 1 1 65536 states 1 0 0 131072 states 1 0 1 262144 states 1 1 0 1024 states 1 1 1 1 0 0 0 0 8192 states 0 0 1 16384 states 0 1 0 32768 states 0 1 1 65536 states 1 0 0 131072 states 1 0 1 262144 states 1 1 0 1024 states 1 1 1 1 1 0 0 0 8192 states 0 0 1 16384 states 0 1 0 32768 states 0 1 1 65536 states 1 0 0 131072 states 1 0 1 262144 states 1 1 0 1024 states 1 1 1 Note: * Recommended setting 20 MHz 0.4 0.8 1.6 3.3 6.6 13.1* 0.05 0.8 1.6 3.3 6.6 13.1* 26.2 0.10 1.6 3.3 6.6 13.1* 26.2 52.4 0.20 3.3 6.6 13.1* 26.2 52.4 104.9 0.41 18 MHz 0.46 0.91 1.8 3.6 7.3* 14.6 0.057 0.91 1.8 3.6 7.3* 14.6 29.1 0.11 1.8 3.6 7.3* 14.6 29.1 58.3 0.23 3.6 7.3* 14.6 29.1 58.3 116.5 0.46 16 MHz 0.51 1.0 2.0 4.1 8.2* 16.4 0.064 1.02 2.0 4.1 8.2* 16.4 32.8 0.13 2.0 4.1 8.2* 16.4 32.8 65.5 0.26 4.1 8.2* 16.4 32.8 65.5 131.1 0.51 12 MHz 0.65 1.3 2.7 5.5 10.9* 21.8 0.085 1.4 2.7 5.5 10.9* 21.8 43.7 0.17 2.7 5.5 10.9* 21.8 43.7 87.4 0.34 5.5 10.9* 21.8 43.7 87.4 174.8 0.68 10 MHz 8 MHz 0.8 1.0 1.6 2.0 3.3 4.1 6.6 8.2* 13.1* 16.4 26.2 32.8 0.10 0.13 Illegal setting 1.6 2.0 3.3 4.1 6.6 8.2* 13.1* 16.4 26.2 32.8 52.4 65.5 0.20 0.26 Illegal setting 3.3 4.1 6.6 8.2* 13.1* 16.4 26.2 32.8 52.4 65.5 104.9 131.1 0.41 0.51 Illegal setting 6.6 8.2* 13.1* 16.4 26.2 32.8 52.4 65.5 104.9 131.1 209.7 262.1 0.82 1.0 Illegal setting 6 MHz 1.3 2.7 5.5 10.9* 21.8 43.7 0.17 2.7 5.5 10.9* 21.8 43.7 87.4 0.34 5.5 10.9* 21.8 43.7 87.4 174.8 0.68 10.9* 21.8 43.7 87.4 174.8 349.5 1.4 4 MHz 2.0 4.1 8.2* 16.4 32.8 65.5 0.26 4.1 8.2* 16.4 32.8 65.5 131.1 0.51 8.2* 16.4 32.8 65.5 131.1 262.1 1.02 16.4* 32.8 65.5 131.1 262.1 524.3 2.0 2 MHz 4.1 8.2* 16.4 32.8 65.5 131.1 0.51 8.2* 16.4 32.8 65.5 131.1 262.1 1.0 16.4* 32.8 65.5 131.1 262.1 524.3 2.0 32.8* 65.5 131.1 262.1 524.3 1048.6 4.1 1 MHz Unit 8.2* ms 16.4 32.8 65.5 131.1 262.1 1.0 16.4* ms 32.8 65.5 131.1 262.1 524.3 2.0 32.8* ms 65.5 131.1 262.1 524.3 1048.6 4.1 65.5 ms 131.1 262.1 524.3 1048.6 2097.1 8.2*
Rev.5.00 Sep. 12, 2007 Page 564 of 764 REJ09B0396-0500
19. Power-Down State
19.4.4
Sample Application of Software Standby Mode
Figure 19.1 shows an example in which software standby mode is entered at the fall of NMI and exited at the rise of NMI. With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an NMI interrupt occurs. Next the NMIEG bit is set to 1 (selecting the rising edge) and the SSBY bit is set to 1; then the SLEEP instruction is executed to enter software standby mode. Software standby mode is exited at the next rising edge of the NMI signal.
Clock oscillator NMI NMIEG SSBY
NMI interrupt handler NMIEG = 1 SSBY = 1
Software standby mode (powerdown state)
Oscillator settling time (tosc2)
NMI exception handling
SLEEP instruction
Figure 19.1 NMI Timing for Software Standby Mode (Example) 19.4.5 Note
The I/O ports retain their existing states in software standby mode. If a port is in the high output state, its output current is not reduced.
Rev.5.00 Sep. 12, 2007 Page 565 of 764 REJ09B0396-0500
19. Power-Down State
19.5
19.5.1
Hardware Standby Mode
Transition to Hardware Standby Mode
Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting all functions of the CPU, DMAC, DRAM interface, and on-chip supporting modules. All modules are reset except the on-chip RAM. As long as the specified voltage is supplied, on-chip RAM data is retained. I/O ports are placed in the high-impedance state. Clear the RAME bit to 0 in SYSCR before STBY goes low to retain on-chip RAM data. The inputs at the mode pins (MD2 to MD0) should not be changed during hardware standby mode. 19.5.2 Exit from Hardware Standby Mode
Hardware standby mode is exited by inputs at the STBY and RES pins. While RES is low, when STBY goes high, the clock oscillator starts running. RES should be held low long enough for the clock oscillator to settle. When RES goes high, reset exception handling begins, followed by a transition to the program execution state. 19.5.3 Timing for Hardware Standby Mode
Figure 19.2 shows the timing relationships for hardware standby mode. To enter hardware standby mode, first drive RES low, then drive STBY low. To exit hardware standby mode, first drive STBY high, wait for the clock to settle, then bring RES from low to high.
Clock oscillator RES
STBY
Oscillator settling time Reset exception handling
Figure 19.2 Hardware Standby Mode Timing
Rev.5.00 Sep. 12, 2007 Page 566 of 764 REJ09B0396-0500
19. Power-Down State
19.6
19.6.1
Module Standby Function
Module Standby Timing
The module standby function can halt several of the on-chip supporting modules (SCI2, SCI1, SCI0, the DMAC, 16-bit timer, 8-bit timer, DRAM interface, and A/D converter) independently in the power-down state. This standby function is controlled by bits MSTPH2 to MSTPH0 in MSTCRH and bits MSTPL7 to MSTPL0 in MSTCRL. When one of these bits is set to 1, the corresponding on-chip supporting module is placed in standby and halts at the beginning of the next bus cycle after the MSTCR write cycle. 19.6.2 Read/Write in Module Standby
When an on-chip supporting module is in module standby, read/write access to its registers is disabled. Read access always results in H'FF data. Write access is ignored. 19.6.3 Usage Notes
When using the module standby function, note the following points. DMAC: When setting a bit in MSTCR to 1 to place the DMAC or DRAM interface in module standby, make sure that the DMAC or DRAM interface is not currently requesting the bus right. If the corresponding bit in MSTCR is set to 1 when a bus request is present, operation of the bus arbiter becomes ambiguous and a malfunction may occur. DRAM Interface: When the module standby function is used on the DRAM interface, set the MSTCR bit to 1 while DRAM space is deselected. Cancellation of Interrupt Handling: Before setting a module standby bit, first disable interrupts by that module. When an on-chip supporting module is placed in standby by the module standby function, its registers are initialized, including registers with interrupt request flags. Pin States: Pins used by an on-chip supporting module lose their module functions when the module is placed in module standby. What happens after that depends on the particular pin. For details, see section 8, I/O Ports. Pins that change from the input to the output state require special care. For example, if SCI1 is placed in module standby, the receive data pin loses its receive data function and becomes a port pin. If its port DDR bit is set to 1, the pin becomes a data output pin, and its output may collide with external SCI transmit data. Data collision should be prevented by clearing the port DDR bit to 0 or taking other appropriate action. Register Resetting: When an on-chip supporting module is halted by the module standby function, all its registers are initialized. To restart the module, after its MSTCR bit is cleared to 0, its registers must be set up again. It is not possible to write to the registers while the MSTCR bit is set to 1.
Rev.5.00 Sep. 12, 2007 Page 567 of 764 REJ09B0396-0500
19. Power-Down State
MSTCR Access from DMAC Disabled: To prevent malfunctions, MSTCR can only be accessed from the CPU. It can be read by the DMAC, but it cannot be written by the DMAC.
19.7
System Clock Output Disabling Function
Output of the system clock () can be controlled by the PSTOP bit in MSTCRH. When the PSTOP bit is set to 1, output of the system clock halts and the pin is placed in the highimpedance state. Figure 19.3 shows the timing of the stopping and starting of system clock output. When the PSTOP bit is cleared to 0, output of the system clock is enabled. Table 19.4 indicates the state of the pin in various operating states.
MSTCRH write cycle (PSTOP = 1) T1 pin High impedance T2 T3 MSTCRH write cycle (PSTOP = 0) T1 T2 T3
Figure 19.3 Starting and Stopping of System Clock Output Table 19.4 Pin State in Various Operating States
Operating State Hardware standby Software standby Sleep mode Normal operation PSTOP = 0 High impedance Always high System clock output System clock output PSTOP = 1 High impedance High impedance High impedance High impedance
Rev.5.00 Sep. 12, 2007 Page 568 of 764 REJ09B0396-0500
20. Electrical Characteristics
Section 20 Electrical Characteristics
20.1 Absolute Maximum Ratings
Table 20.1 lists the absolute maximum ratings. Table 20.1 Absolute Maximum Ratings
Item Power supply voltage Input voltage (except for port 7) Input voltage (port 7) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Symbol VCC Vin Vin VREF AVCC VAN Topr Tstg Value -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 Storage temperature -55 to +125 Unit V V V V V V C C C
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
Rev.5.00 Sep. 12, 2007 Page 569 of 764 REJ09B0396-0500
20. Electrical Characteristics
20.2
20.2.1
Electrical Characteristics
DC Characteristics
Tables 20.2, 20.3 and 20.4 list the DC characteristics. Table 20.4 lists the permissible output currents. Table 20.2 DC Characteristics (1) Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 V to AVCC* , 1 VSS = AVSS = 0 V* , Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
1
Item Schmitt trigger input voltages Input high voltage Port A, P82 to P80 RES, STBY, NMI, MD2 to MD0 EXTAL Port 7 Ports 4, 6, P83, P84, P95 to P90, port B, D15 to D8 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, ports 4, 6, 7, P83, P84, P95 to P90, port B, D15 to D8 Output high voltage Output low voltage
Symbol VT VT
- + + -
Min 1.0 0.4 VCC -0.7
Typ
Max VCC x 0.7 VCC +0.3
Unit Test Conditions V V V V
VT - VT VIH
VCC x 0.7 2.0 2.0
VCC +0.3 AVCC +0.3 VCC +0.3
V V V
VIL
-0.3 -0.3

0.5 0.8
V V
All output pins VOH (except RESO) All output pins VOL (except RESO) A19 to A0 RESO
VCC -0.5 3.5

0.4 1.0 0.4
V V V V V
IOH = -200 A IOH = -1 mA IOL = 1.6 mA IOL = 10 mA IOL = 2.6 mA
Rev.5.00 Sep. 12, 2007 Page 570 of 764 REJ09B0396-0500
20. Electrical Characteristics Item Input leakage STBY, NMI, current RES, MD2 to MD0 Port 7 Three-state leakage current Ports 4, 6, 8 to B, A19 to A0, D15 to D8 RESO Input pull-up MOS current Input capacitance Port 4 NMI All input pins except NMI Normal operation Sleep mode Module standby mode Standby mode ICC*
3
Symbol |Iin|
Min
Typ
Max 1.0
Unit Test Conditions A Vin = 0.5 V to VCC -0.5 V Vin = 0.5 V to AVCC -0.5 V Vin = 0.5 V to VCC -0.5 V
|ITSI|

1.0 1.0
A A
-Ip Cin 50
45 (5.0 V) 35 (5.0 V) 18 (5.0 V) 0.01 0.6 0.6
10.0 300 50 15 100 73 51 5.0 20.0 1.5 1.5
A A pF pF mA mA mA A A mA mA
Vin = 0 V Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C f = 20 MHz f = 20 MHz f = 20 MHz Ta 50C 50C Ta
Current 2 dissipation*
Analog power During A/D supply current conversion During A/D and D/A conversion Idle Reference current During A/D conversion During A/D and D/A conversion Idle RAM standby voltage
AICC
AICC
0.01 0.5 2.0
5.0 0.8 3.0
A mA mA
DASTE = 0
VRAM 2.0
0.01
5.0
A V
DASTE = 0
Notes: 1. Do not open the pin connections of the AVCC, VREF and AVSS pins while the A/D converter is not in use. Rev.5.00 Sep. 12, 2007 Page 571 of 764 REJ09B0396-0500
20. Electrical Characteristics Connect the AVCC and VREF pins to the VCC and connect the AVSS pin to the VSS, respectively. 2. Given current consumption values are when all the output pins are made to unloaded state and, furthermore, when the on-chip pull-up MOS is turned off under conditions that VIH min = VCC - 0.5 V and VIL max = 0.5 V. Also, the aforesaid current consumption values are when VIH min = VCC x 0.9 and VIL max = 0.3 V under the condition of VRAM VCC < 4.5 V. 3. ICC max. (under normal operations) = 1.0 (mA) + 0.90 (mA/(MHz x V)) x VCC x f ICC max. (when using the sleeve) = 1.0 (mA) + 0.65 (mA/(MHz x V)) x VCC x f ICC max. (when the sleeve + module are standing by) = 1.0 (mA) + 0.45 (mA/(MHz x V)) x VCC x f Also, the typ. values for current dissipation are reference values.
Rev.5.00 Sep. 12, 2007 Page 572 of 764 REJ09B0396-0500
20. Electrical Characteristics
Table 20.3 DC Characteristics (2) Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 V to AVCC*1, 1 VSS = AVSS = 0 V* , Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Schmitt trigger input voltages Input high voltage Port A, P82 to P80 Symbol VT VT
- + + -
Min VCC x 0.2 VCC x 0.07 VCC x 0.9
Typ
Max VCC x 0.7 VCC +0.3
Unit Test Conditions V V V V
VT - VT RES, STBY, NMI, MD2 to MD0 EXTAL Port 7 Ports 4, 6, P83, P84, P95 to P90, port B, D15 to D8 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, Ports 4, 6, 7, D15 to D8 P83, P84, P95 to P90, port B Output high voltage Output low voltage All output pins VOH (except RESO) All output pins VOL (except RESO) A19 to A0 VIL VIH
VCC x 0.7 VCC x 0.7 VCC x 0.7

VCC +0.3 AVCC +0.3 VCC +0.3
V V V
-0.3 -0.3

VCC x 0.1 VCC x 0.2
V V VCC < 4.0 V
0.8 VCC -0.5 VCC -1.0 0.4 1.0
V V V V V
VCC = 4.0 to 5.5 V IOH = -200 A IOH = -1 mA IOL = 1.6 mA IOL = 5 mA (VCC < 4.0 V) IOL = 10 mA (VCC = 4.0 to 5.5 V)
RESO
0.4
V
IOL = 1.6 mA
Rev.5.00 Sep. 12, 2007 Page 573 of 764 REJ09B0396-0500
20. Electrical Characteristics Item Input leakage STBY, NMI, current RES, MD2 to MD0 Port 7 Three-state leakage current Ports 4, 6, 8 to B, A19 to A0, D15 to D8 RESO Input pull-up MOS current Input capacitance Port 4 NMI All input pins except NMI Normal operation Sleep mode Module standby mode Standby mode ICC*
3
Symbol |Iin|
Min
Typ
Max 1.0
Unit Test Conditions A Vin = 0.5 V to VCC -0.5 V Vin = 0.5 V to AVCC -0.5 V Vin = 0.5 V to VCC -0.5 V
|ITSI|

1.0 1.0
A A
-Ip Cin 10 AICC VRAM 2.0
15 (3.0 V) 9 (3.0 V) 6 (3.0 V) 0.01 0.2 0.6 0.2 0.6 0.01 0.3 0.5 1.2 2.0 0.01
10.0 300 50 15 51 37 26 5.0 20.0 0.5 0.5 5.0 0.5 2.0 5.0
A A pF pF mA mA mA A A mA mA mA mA A mA mA mA mA A V
Vin = 0 V Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C f = 10 MHz f = 10 MHz f = 10 MHz Ta 50C 50C Ta AVCC = 3.0 V AVCC = 5.0 V AVCC = 3.0 V AVCC = 5.0 V DASTE = 0 VREF = 3.0 V VREF = 5.0 V VREF = 3.0 V VREF = 5.0 V DASTE = 0
Current 2 dissipation*
Analog power During A/D supply current conversion During A/D and D/A conversion Idle Reference current During A/D conversion During A/D and D/A conversion Idle RAM standby voltage
AICC
Notes: 1. Do not open the pin connections of the AVCC, VREF and AVSS pins while the A/D converter is not in use. Rev.5.00 Sep. 12, 2007 Page 574 of 764 REJ09B0396-0500
20. Electrical Characteristics Connect the AVCC and VREF pins to the VCC and connect the AVSS pin to the VSS, respectively. 2. Given current consumption values are when all the output pins are made to unloaded state and, furthermore, when the on-chip pull-up MOS is turned off under conditions that VIH min = VCC - 0.5 V and VIL max = 0.5 V. Also, the aforesaid current consumption values are when VIH min = VCC x 0.9 and VIL max = 0.3 V under the condition of VRAM VCC < 2.7 V. 3. ICC max. (under normal operations) = 1.0 (mA) + 0.90 (mA/(MHz x V)) x VCC x f ICC max. (when using the sleeve) = 1.0 (mA) + 0.65 (mA/(MHz x V)) x VCC x f ICC max. (when the sleeve + module are standing by) = 1.0 (mA) + 0.45 (mA/(MHz x V)) x VCC x f Also, the typ. values for current dissipation are reference values.
Rev.5.00 Sep. 12, 2007 Page 575 of 764 REJ09B0396-0500
20. Electrical Characteristics
Table 20.4 DC Characteristics (3) Conditions: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 V to AVCC* , 1 VSS = AVSS = 0 V* , Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Schmitt trigger input voltages Input high voltage Port A, P82 to P80 Symbol VT VT
- + + -
1
Min VCC x 0.2 VCC x 0.9
Typ
Max VCC x 0.7 VCC +0.3
Unit Test Conditions V V V V
VT - VT RES, STBY, NMI, MD2 to MD0 EXTAL Port 7 Ports 4, 6, P83, P84, P95 to P90, Port B, D15 to D8 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, Ports 4, 6, 7 P83, P84, P95 to P90, Port B, D15 to D8 Output high voltage Output low voltage All output pins VOH (except RESO) All output pins VOL (except RESO) A19 to A0 VIL VIH
VCC x 0.07
VCC x 0.7 VCC x 0.7 VCC x 0.7

VCC +0.3 AVCC +0.3 VCC +0.3
V V V
-0.3 -0.3

VCC x 0.1 VCC x 0.2 0.8
V V V VCC < 4.0 V VCC = 4.0 to 5.5 V IOH = -200 A IOH = -1 mA IOL = 1.6 mA IOL = 5 mA (VCC < 4.0 V) IOL = 10 mA (VCC = 4.0 to 5.5 V)
VCC -0.5 VCC -1.0

0.4 1.0
V V V V
RESO
0.4
V
IOL = 1.6 mA
Rev.5.00 Sep. 12, 2007 Page 576 of 764 REJ09B0396-0500
20. Electrical Characteristics Item Input leakage STBY, NMI, current RES, MD2 to MD0 Port 7 Three-state leakage current Ports 4, 6, 8 to |ITSI| B, A19 to A0, D15 to D8 RESO Input pull-up MOS current Input capacitance Port 4 NMI All input pins except NMI Normal operation Sleep mode Module standby mode Standby mode ICC*
3
Symbol |Iin|
Min
Typ
Max 1.0
Unit Test Conditions A Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to AVCC - 0.5 V Vin = 0.5 V to VCC - 0.5 V Vin = 0 V Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C f = 13 MHz f = 13 MHz f = 13 MHz Ta 50C 50C Ta AVCC = 3.0 V AVCC = 5.0 V AVCC = 3.0 V AVCC = 5.0 V DASTE = 0 VREF = 3.0 V VREF = 5.0 V VREF = 3.0 V VREF = 5.0 V DASTE = 0

1.0 1.0
A A
-Ip Cin 10 AICC VRAM 2.0
20 (3.5 V) 15 (3.5 V) 9 (3.5 V) 0.01 0.2 0.6 0.2 0.6 0.01 0.3 0.5 1.2 2.0 0.01
10.0 300 50 15 66 48 34 5.0 20.0 0.5 0.5 5.0 0.5 2.0 5.0
A A pF pF mA mA mA A A mA mA mA mA A mA mA mA mA A V
Current 2 dissipation*
Analog power During A/D supply current conversion During A/D and D/A conversion Idle Reference current During A/D conversion During A/D and D/A conversion Idle RAM standby voltage
AICC
Notes: 1. Do not open the pin connections of the AVCC, VREF and AVSS pins while the A/D converter is not in use. Rev.5.00 Sep. 12, 2007 Page 577 of 764 REJ09B0396-0500
20. Electrical Characteristics Connect the AVCC and VREF pins to the VCC and connect the AVSS pin to the VSS, respectively. 2. Given current consumption values are when all the output pins are made to unloaded state and, furthermore, when the on-chip pull-up MOS is turned off under conditions that VIH min = VCC - 0.5 V and VIL max = 0.5 V. Also, the aforesaid current consumption values are when VIH min = VCC x 0.9 and VIL max = 0.3 V under the condition of VRAM VCC < 3.0 V. 3. ICC max. (under normal operations) = 1.0 (mA) + 0.90 (mA/(MHz x V)) x VCC x f ICC max. (when using the sleeve) = 1.0 (mA) + 0.65 (mA/(MHz x V)) x VCC x f ICC max. (when the sleeve + module are standing by) = 1.0 (mA) + 0.45 (mA/(MHz x V)) x VCC x f Also, the typ. values for current dissipation are reference values.
Rev.5.00 Sep. 12, 2007 Page 578 of 764 REJ09B0396-0500
20. Electrical Characteristics
Table 20.5 Permissible Output Currents Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Permissible output low current (per pin) Permissible output low current (total) A19 to A0 Other output pins Total of 20 pins in A19 to A0 Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins |-IOH| |-IOH| IOL Symbol IOL Min Typ Max 10 2.0 80 120 2.0 40 Unit mA mA mA mA mA mA
Notes: 1. To protect chip reliability, do not exceed the output current values in table 20.5. 2. When driving a darlington pair, always insert a current-limiting resistor in the output line, as shown in figures 20.1.
H8/3006 and H8/3007
2 k Port
Darlington pair
Figure 20.1 Darlington Pair Drive Circuit (Example)
Rev.5.00 Sep. 12, 2007 Page 579 of 764 REJ09B0396-0500
20. Electrical Characteristics
20.2.2
AC Characteristics
Clock timing parameters are listed in table 20.6, control signal timing parameters in table 20.7, and bus timing parameters in table 20.8. Timing parameters of the on-chip supporting modules are listed in table 20.9. Table 20.6 Clock Timing Condition: Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V, = 1 to 10 MHz Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V, = 1 to 13 MHz Condition C: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, = 1 to 20 MHz
Condition A Item Clock cycle time Clock pulse low width Clock pulse high width Clock rise time Clock fall time Clock oscillator settling time at reset Clock oscillator settling time in software standby Symbol tcyc tCL tCH tCr tCf tOSC1 Min 100 30 30 20 Max 1000 20 20 Condition B Min 76.9 20 20 20 Max 1000 15 15 Condition C Min 50 15 15 20 Max 1000 10 10 Test Unit Conditions ns ns ns ns ns ms Figure 20.4 Figure 20.3
tOSC2
7
7
7
ms
Figure 19.1
Rev.5.00 Sep. 12, 2007 Page 580 of 764 REJ09B0396-0500
20. Electrical Characteristics
Table 20.7 Control Signal Timing Condition: Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V, = 1 to 10 MHz Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V, = 1 to 13 MHz Condition C: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, = 1 to 20 MHz
Condition A Item RES setup time RES pulse width Mode programming setup time RESO output delay time RESO output pulse width NMI, IRQ hold time NMI, IRQ pulse width (in recovery from software standby mode) Symbol tRESS tRESW tMDS tRESD tRESOW Min 200 10 200 132 200 10 200 Max 100 Condition B Min 200 10 200 132 200 10 200 Max 100 Condition C Min 150 10 200 132 150 10 200 Max 50 Unit ns tcyc ns ns tcyc ns ns ns Figure 20.7 Figure 20.6 Test Conditions Figure 20.5
NMI, IRQ setup time tNMIS tNMIH tNMIW
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20. Electrical Characteristics
Table 20.8 Bus Timing Condition: Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V, = 1 to 10 MHz Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V, = 1 to 13 MHz Condition C: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, = 1 to 20 MHz
Condition A Item Address delay time Address hold time Read strobe delay time Address strobe delay time Write strobe delay time Symbol Min tAD tAH tRSD tASD tWSD 0.5 tcyc - 45 1.0 tcyc - 50 1.5 tcyc - 50 0.5 tcyc - 45 1.0 tcyc - 45 50 0 Max 50 60 60 60 60 60 Condition B Min 0.5 tcyc - 35 1.0 tcyc - 40 1.5 tcyc - 40 0.5 tcyc - 35 1.0 tcyc - 35 40 0 Max 40 50 50 50 50 50 Condition C Min 0.5 tcyc - 20 1.0 tcyc - 25 1.5 tcyc - 25 0.5 tcyc - 20 1.0 tcyc - 20 25 0 Max 25 25 25 25 25 35 Test Unit Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 20.8, figure 20.9, figure 20.11, figure 20.12
Strobe delay time tSD Write strobe pulse width 1 Write strobe pulse width 2 Address setup time 1 Address setup time 2 tWSW1 tWSW2 tAS1 tAS2
Read data setup tRDS time Read data hold time Write data delay time tRDH tWDD
Rev.5.00 Sep. 12, 2007 Page 582 of 764 REJ09B0396-0500
20. Electrical Characteristics Condition A Item Write data setup time 1 Write data setup time 2 Write data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Symbol Min tWDS1 tWDS2 tWDH tACC1 tACC2 tACC3 tACC4 1.0 tcyc - 50 2.0 tcyc - 50 0.5 tcyc - 30 1.0 tcyc - 40 0.5 tcyc - 40 40 5 40 1.5 tcyc - 50 0.5 tcyc - 30 0.5 tcyc - 30 Max 2.0 tcyc - 100 3.0 tcyc - 100 1.5 tcyc - 100 2.5 tcyc - 100 60 60 60 60 60 Condition B Min 1.0 tcyc - 40 2.0 tcyc - 40 0.5 tcyc - 25 1.0 tcyc - 30 0.5 tcyc - 30 40 5 40 1.5 tcyc - 40 0.5 tcyc - 25 0.5 tcyc - 25 Max 2.0 tcyc - 80 3.0 tcyc - 80 1.5 tcyc - 80 2.5 tcyc - 80 50 50 50 50 50 Condition C Min 1.0 tcyc - 30 2.0 tcyc - 30 0.5 tcyc - 15 1.0 tcyc - 20 0.5 tcyc - 20 25 5 25 1.5 tcyc - 25 0.5 tcyc - 15 0.5 tcyc - 15 Max Test Unit Conditions ns ns ns Figure 20.8, figure 20.9, figure 20.11, figure 20.12
2.0 tcyc ns - 45 3.0 tcyc ns - 45 1.5 tcyc ns - 45 2.5 tcyc ns - 45 30 30 30 25 30 ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 20.14 to figure 20.16 Figure 20.13 Figure 20.10
Precharge time 1 tPCH1 Precharge time 2 tPCH2 Wait setup time Wait hold time Bus request setup time tWTS tWTH tBRQS
Bus acknowledge tBACD1 delay time 1 Bus acknowledge tBACD2 delay time 2 Bus-floating time tBZD RAS precharge time CAS precharge time tRP tCP
Low address hold tRAH time RAS delay time 1 tRAD1 RAS delay time 2 tRAD2
Rev.5.00 Sep. 12, 2007 Page 583 of 764 REJ09B0396-0500
20. Electrical Characteristics Condition A Item Symbol Min 1.5 tcyc - 50 1.0 tcyc - 50 1.0 tcyc - 50 0.5 tcyc - 45 0.5 tcyc - 40 0.5 tcyc - 45 0.5 tcyc - 30 0.5 tcyc - 30 0.5 tcyc - 30 0.5 tcyc - 30 1.5 tcyc - 30 Max 60 60 60 2.5 tcyc - 80 2.0 tcyc - 100 1.5 tcyc - 100 CAS delay time 1 tCASD1 CAS delay time 2 tCASD2 WE delay time tWCD Condition B Min 1.5 tcyc - 40 1.0 tcyc - 40 1.0 tcyc - 40 0.5 tcyc - 35 0.5 tcyc - 28 0.5 tcyc - 35 0.5 tcyc - 25 0.5 tcyc - 25 0.5 tcyc - 25 0.5 tcyc - 25 1.5 tcyc - 25 Max 50 50 50 2.5 tcyc - 70 2.0 tcyc - 80 1.5 tcyc - 80 Condition C Min 1.5 tcyc - 20 1.0 tcyc - 20 1.0 tcyc - 20 0.5 tcyc - 20 0.5 tcyc - 15 0.5 tcyc - 20 0.5 tcyc - 15 0.5 tcyc - 20 0.5 tcyc - 15 0.5 tcyc - 15 1.5 tcyc - 15 Max 25 25 25 Test Unit Conditions ns ns ns ns ns ns Figure 20.14 to figure 20.16
CAS pulse width tCAS1 1 CAS pulse width tCAS2 2 CAS pulse width tCAS3 3 RAS access time tRAC Address access time tAA
2.5 tcyc ns - 40 2.0 tcyc ns - 50 1.5 tcyc ns - 50 ns ns ns ns ns ns ns ns
CAS access time tCAC WE setup time WE hold time Write data setup time WE write data hold time tWCS tWCH tWDS tWDH
CAS setup time 1 tCSR1 CAS setup time 2 tCSR2 CAS hold time tCHR
RAS pulse width tRAS
Rev.5.00 Sep. 12, 2007 Page 584 of 764 REJ09B0396-0500
20. Electrical Characteristics
Table 20.9 Timing of On-Chip Supporting Modules Condition: Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V, = 1 to 10 MHz Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V, = 1 to 13 MHz Condition C: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, = 1 to 20 MHz
Condition A Item Ports and TPC Symbol Output data delay tPWD time Input data setup time Input data hold time 16-bit Timer output timer delay time tPRS tPRH tTOCD Min 50 50 50 50 1.5 2.5 50 50 1.5 2.5 Max 100 100 100 Condition B Min 50 50 50 50 1.5 2.5 50 50 1.5 2.5 Max 100 100 100 Condition C Min 50 50 50 50 1.5 2.5 50 50 1.5 2.5 Max 50 50 50 Unit ns ns ns ns ns ns tcyc tcyc ns ns ns tcyc tcyc Figure 20.19 Figure 20.18 Figure 20.19 Figure 20.18
Test Conditions Figure 20.17
Timer input setup tTICS time Timer clock input tTCKS setup time Timer clock pulse width 8-bit timer Single edge Both edges tTCKWH tTCKWL tTOCD tTICS tTCKS tTCKWH tTCKWL
Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges
Rev.5.00 Sep. 12, 2007 Page 585 of 764 REJ09B0396-0500
20. Electrical Characteristics Condition A Item SCI Input clock cycle Symbol AsyntScyc chronous Synchronous tSCKr tSCKf tSCKW tTXD tRXS Min 4 6 1.5 1.5 0.4 100 Max 0.6 100 Condition B Min 4 6 1.5 1.5 0.4 100 Max 0.6 100 Condition C Min 4 6 1.5 1.5 0.4 100 Max 0.6 100 Unit tcyc tcyc tcyc tcyc tScyc ns ns Figure 20.21
Test Conditions Figure 20.20
Input clock rise time Input clock fall time Input clock pulse width Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) Clock input Clock output
tRXH
100 0
100 100
100 0 40 10
100 100
100 0 25 10
50 50
ns ns ns ns ns ns Figure 20.24 Figure 20.22, figure 20.23
DMAC TEND delay time 1 TEND delay time 2 DREQ setup time DREQ hold time
tTED1 tTED2 tDRQS tDRQH
40 10
Rev.5.00 Sep. 12, 2007 Page 586 of 764 REJ09B0396-0500
20. Electrical Characteristics
RL H8/3006 and H8/3007 output pin C RH
C = 90 pF: Ports 4, 6, 8, A19 to A0, D15 to D8 C = 30 pF: Ports 9, A, B, RESO R L = 2.4 k R H = 12 k Input/output timing measurement levels * Low: 0.8 V * High: 2.0 V
Figure 20.2 Output Load Circuit
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20. Electrical Characteristics
20.2.3
A/D Conversion Characteristics
Table 20.10 lists the A/D conversion characteristics. Table 20.10 A/D Conversion Characteristics Condition: Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V, fmax = 10 MHz Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V, fmax = 13 MHz Condition C: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, fmax = 20 MHz
Condition A Item Conversion time: 134 states Resolution Conversion time (single mode) Min Typ Max 10 10 10 134 20 10 5 7.5 7.5 7.5 0.5 8.0 Condition B Min Typ Max 10 10 10 134 20 10 5 7.5 7.5 7.5 0.5 8.0 Condition C Min Typ Max 10 10 10 134 20 10 5 3.5 3.5 3.5 0.5 4.0 Unit bits tcyc pF k k k k LSB LSB LSB LSB LSB
Analog input capacitance Permissible 13 MHz signal > 13 MHz source impedance 4.0 V AVCC 5.5 V 2.7 V AVCC < 4.0 V Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy
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20. Electrical Characteristics Condition A Item Conversion time: 70 states Resolution Conversion time (single mode) Min Typ Max 10 10 10 70 20 5 3 Condition B Min Typ Max 10 10 10 70 20 5 3 Condition C Min Typ Max 10 10 10 70 20 5 3 7.5 7.5 7.5 0.5 8.0 Unit bits tcyc pF k k k k LSB LSB LSB LSB LSB
Analog input capacitance Permissible 13 MHz signal > 13 MHz source impedance 4.0 V AVCC 5.5 V 2.7 V AVCC < 4.0 V Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy
15.5 15.5 15.5 0.5 16
15.5 15.5 15.5 0.5 16
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20. Electrical Characteristics
20.2.4
D/A Conversion Characteristics
Table 20.11 lists the D/A conversion characteristics. Table 20.11 D/A Conversion Characteristics Condition: Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V, fmax = 10 MHz Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V, fmax = 13 MHz Condition C: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, fmax = 20 MHz
Condition A Item Resolution Conversion time (centering time) Absolute accuracy Min Typ Max 8 8 8 10 Condition B Min Typ Max 8 8 8 10 Condition C Min Typ Max 8 8 8 10 Test Unit Conditions Bits s 20 pF capacitive load

2.0 3.0 2.0

2.0 3.0 2.0

1.5 2.0 1.5
LSB 2 M resistive load LSB 4 M resistive load
Rev.5.00 Sep. 12, 2007 Page 590 of 764 REJ09B0396-0500
20. Electrical Characteristics
20.3
Operational Timing
This section shows timing diagrams. 20.3.1 Clock Timing
Clock timing is shown as follows: * System clock timing Figure 20.3 shows the system clock timing. * Oscillator settling timing Figure 20.4 shows the oscillator settling timing.
tcyc tCH tCf
tCL
tCr
Figure 20.3 System Clock Timing
VCC
STBY tOSC1 RES tOSC1
Figure 20.4 Oscillator Settling Timing
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20. Electrical Characteristics
20.3.2
Control Signal Timing
Control signal timing is shown as follows: * Reset input timing Figure 20.5 shows the reset input timing. * Reset output timing Figure 20.6 shows the reset output timing. * Interrupt input timing Figure 20.7 shows the interrupt input timing for NMI and IRQ5 to IRQ0.
tRESS RES tMDS MD2 to MD0 tRESW tRESS
Figure 20.5 Reset Input Timing
tRESD RESO tRESOW tRESD
Figure 20.6 Reset Output Timing
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20. Electrical Characteristics
tNMIS NMI tNMIS IRQ E tNMIS IRQ L IRQ E : Edge-sensitive IRQ i IRQ L : Level-sensitive IRQ i (i = 0 to 5) tNMIW NMI IRQ j (j = 0 to 5) tNMIH tNMIH
Figure 20.7 Interrupt Input Timing 20.3.3 Bus Timing
Bus timing is shown as follows: * Basic bus cycle: two-state access Figure 20.8 shows the timing of the external two-state access cycle. * Basic bus cycle: three-state access Figure 20.9 shows the timing of the external three-state access cycle. * Basic bus cycle: three-state access with one wait state Figure 20.10 shows the timing of the external three-state access cycle with one wait state inserted. * Burst ROM access timing: burst cycle two-state Figure 20.11 shows the timing of the burst cycle two-state access. * Burst ROM access timing: burst cycle three-state Figure 20.12 shows the timing of the burst cycle three-state access. * Bus-release mode timing Figure 20.13 shows the bus-release mode timing.
Rev.5.00 Sep. 12, 2007 Page 593 of 764 REJ09B0396-0500
20. Electrical Characteristics
T1 tcyc tCH tAD A23 to A0, CSn tCL
T2
tCf
tcyc
tCr
tPCH1 tASD AS tAS1 tASD RD (read) tAS1 tACC1 D15 to D0 (read) tPCH1 tASD HWR, LWR (write) tAS1 tWSW1 tWDS1 tSD tAH tRDS tACC3 tRSD tPCH2 tACC3 tSD tAH
tRDH*
tWDD D15 to D0 (write)
tWDH
Note: * Specification from the earliest negation timing of A23 to A0, CSn, and RD.
Figure 20.8 Basic Bus Cycle: Two-State Access
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20. Electrical Characteristics
T1 A23 to A0, CSn tACC4 AS tACC4 RD (read) tACC2 D15 to D0 (read) tWSD HWR, LWR (write) tAS2 tWDD D15 to D0 (write) tWDS2 tWSW2 tRDS T2 T3
Figure 20.9 Basic Bus Cycle: Three-State Access
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20. Electrical Characteristics
T1 A23 to A0, CSn AS RD (read) D15 to D0 (read) T2 TW T3
HWR, LWR (write) D15 to D0 (write) tWTS WAIT tWTH tWTS tWTH
Figure 20.10 Basic Bus Cycle: Three-State Access with One Wait State
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20. Electrical Characteristics
T1 tAD A23 to A3, CSn
T2
T3
T1
T2
tAD
A2 to A0 tASD AS tACC4 tSD tAH tASD tSD tAH
tAS1 tASD tACC4
tAS1 tRSD
RD
tAS1 tACC2 tRDS tACC1 tRDS
tRDH*
D15 to D0
Note: * Specification from the earliest negation timing of A23 to A0, CSn, and RD.
Figure 20.11 Burst ROM Access Timing: Two-State Access
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20. Electrical Characteristics
T1 tAD A23 to A3, CSn tAD T2 T3 T1 T2 T3
A2 to A0 tASD AS tACC4 tSD tAH tASD tSD tAH
tAS1 tASD tACC4
tAS1 tRSD
RD
tAS1 tACC2 tRDS tACC2 tRDS
tRDH*
D15 to D0
Note: * Specification from the earliest negation timing of A23 to A0, CSn, and RD.
Figure 20.12 Burst ROM Access Timing: Three-State Access
tBRQS BREQ tBACD2 tBACD1 BACK tBZD tBRQS
A23 to A0, AS, RD, HWR, LWR
tBZD
Figure 20.13 Bus-Release Mode Timing
Rev.5.00 Sep. 12, 2007 Page 598 of 764 REJ09B0396-0500
20. Electrical Characteristics
20.3.4
DRAM Interface Bus Timing
DRAM interface bus timing is shown as follows: * DRAM bus timing: read and write access Figure 20.14 shows the timing of the read and write access. * DRAM bus timing: CAS before RAS refresh Figure 20.15 shows the timing of the CAS before RAS refresh. * DRAM bus timing: self-refresh Figure 20.16 shows the timing of the self-refresh.
Rev.5.00 Sep. 12, 2007 Page 599 of 764 REJ09B0396-0500
20. Electrical Characteristics
Tp
Tr
TC1
TC2
tAD A23 to A0
tAD
tAD
tAS1 tRP CS5 to CS2 (RAS5 to RAS2) tRAD1
tRAH
tRAD2
tASD UCAS, LCAS (read) tCAS1
tCASD2
tCP
RD (WE) (read)
(High) tRAC tRDS tRDH* tAA tCAC tCASD1 tCASD2 tCAS2 tCP tASD tWCD
D15 to D0 (read)
UCAS, LCAS (write)
RD (WE) (write) tWCS tWDD D15 to D0 (write) tWDS tWCH tWDH
RFSH
(High)
Note: * Specification from the earliest negation timing of RAS and CAS.
Figure 20.14 DRAM Bus Timing (Read/Write)
Rev.5.00 Sep. 12, 2007 Page 600 of 764 REJ09B0396-0500
20. Electrical Characteristics
TRp
TR1
TR2
tRAD1 tRP CS5 to CS2 (RAS5 to RAS2) tRAS tCASD1 tCSR1 UCAS, LCAS tCAS3 tCASD2 tCHR
tRAD2
RD (WE) (High)
tRAD1 tCSR1 tCHR tRAS
tRAD2
RFSH
Figure 20.15 DRAM Bus Timing (CAS before RAS Refresh)
Rev.5.00 Sep. 12, 2007 Page 601 of 764 REJ09B0396-0500
20. Electrical Characteristics
tCSR2 CS5 to CS2 (RAS5 to RAS2)
UCAS, LCAS
RD (WE) (High) tCSR2 RFSH
Figure 20.16 DRAM Bus Timing (Self-Refresh) 20.3.5 TPC and I/O Port Timing
Figure 20.17 shows the TPC and I/O port input/output timing.
T1 tPRS Port 4, 6 to B (read) tPWD Port 4, 6, 8 to B (write) tPRH T2 T3
Figure 20.17 TPC and I/O Port Input/Output Timing
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20. Electrical Characteristics
20.3.6
Timer Input/Output Timing
The timings of 16-bit and 8-bit timer are shown as follows: * Timer input/output timing Figure 20.18 shows the timer input/output timing. * Timer external clock input timing Figure 20.19 shows the timer external clock input timing.
tTOCD Output compare*1 tTICS Input capture*2 Notes: 1. TIOCA 0 to TIOCA 2, TIOCB 0 to TIOCB 2 , TMO0, TMO2, TMIO1,TMIO3 2. TIOCA 0 to TIOCA 2, TIOCB 0 to TIOCB 2 , TMIO1, TMIO3
Figure 20.18 Timer Input/Output Timing
tTCKS tTCKS TCLKA to TCLKD
tTCKWL
tTCKWH
Figure 20.19 Timer External Clock Input Timing
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20. Electrical Characteristics
20.3.7
SCI Input/Output Timing
SCI timing is shown as follows: * SCI input clock timing Figure 20.20 shows the SCI input clock timing. * SCI input/output timing (synchronous mode) Figure 20.21 shows the SCI input/output timing in synchronous mode.
tSCKW SCK0 to SCK2 tScyc tSCKr tSCKf
Figure 20.20 SCI Input Clock Timing
tScyc SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) RxD0 to RxD2 (receive data)
tRXS
tRXH
Figure 20.21 SCI Input/Output Timing in Synchronous Mode
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20. Electrical Characteristics
20.3.8
DMAC Timing
DMAC timing is shown as follows. * DMAC TEND output timing for 2 state access Figure 20.22 shows the DMAC TEND output timing for 2 state access. * DMAC TEND output timing for 3 state access Figure 20.23 shows the DMAC TEND output timing for 3 state access. * DMAC DREQ input timing Figure 20.24 shows DMAC DREQ input timing.
T1 tTED1 TEND tTED2 T2
Figure 20.22 DMAC TEND Output Timing for 2 State Access
T1 tTED1 TEND tTED2 T2 T3
Figure 20.23 DMAC TEND Output Timing for 3 State Access
tDRQS DREQ tDRQH
Figure 20.24 DMAC DREQ Input Timing
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20. Electrical Characteristics
Rev.5.00 Sep. 12, 2007 Page 606 of 764 REJ09B0396-0500
Appendix A Instruction Set
Appendix A Instruction Set
A.1 Instruction List
Operand Notation
Symbol Rd Rs Rn ERd ERs ERn (EAd) (EAs) PC SP CCR N Z V C disp + - x / ( ), < > Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) Destination operand Source operand Program counter Stack pointer Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Displacement Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the operand on the right Logical AND of the operands on both sides Logical OR of the operands on both sides Exclusive logical OR of the operands on both sides NOT (logical complement) Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7). Rev.5.00 Sep. 12, 2007 Page 607 of 764 REJ09B0396-0500
Appendix A Instruction Set
Condition Code Notation
Symbol Description Changed according to execution result * 0 1 Undetermined (no guaranteed value) Cleared to 0 Set to 1 Not affected by execution of the instruction Varies depending on conditions, described in notes
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Appendix A Instruction Set
Table A.1
Instruction Set
1. Data transfer instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
No. of States*1
@(d, ERn)
@aa
Condition Code
Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd
Operation #xx:8 Rd8
I
HN
Z
V
C
B B B
2 2 2 4

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 2 4 6
Rs8 Rd8 @ERs Rd8 @(d:16, ERs) Rd8 @(d:24, ERs) Rd8 2 @ERs Rd8 ERs32+1 ERs32 2 4 6 2 4 @aa:8 Rd8 @aa:16 Rd8 @aa:24 Rd8 Rs8 @ERd Rs8 @(d:16, ERd) Rs8 @(d:24, ERd) 2 ERd32-1 ERd32 Rs8 @ERd 2 4 6 Rs8 @aa:8 Rs8 @aa:16 Rs8 @aa:24 #xx:16 Rd16
MOV.B @(d:16, ERs), B Rd MOV.B @(d:24, ERs), B Rd MOV.B @ERs+, Rd B
8
10
6
MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @ERd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd
B B B B B
4 6 8 4 6
B
8
10
B
6
MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd
B B B W4 W W 2 2 4
4 6 8 4 2 4 6
Rs16 Rd16 @ERs Rd16 @(d:16, ERs) Rd16 @(d:24, ERs) Rd16 2 @ERs Rd16 ERs32+2 @ERd32 4 @aa:16 Rd16
MOV.W @(d:16, ERs), W Rd MOV.W @(d:24, ERs), W Rd MOV.W @ERs+, Rd W
8
10
6
MOV.W @aa:16, Rd
W
6
Rev.5.00 Sep. 12, 2007 Page 609 of 764 REJ09B0396-0500
Advanced
@(d, PC)
Normal
@@aa
@ERn
#xx
Rn
Appendix A Instruction Set
Addressing Mode and Instruction Length (bytes) No. of States*1
@-ERn/@ERn+
Operand Size
@(d, ERn)
#xx
Rn
@aa
Condition Code
Mnemonic MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16, ERd) MOV.W Rs, @(d:24, ERd) MOV.W Rs, @-ERd
Operation @aa:24 Rd16 Rs16 @ERd
I
HN
Z
V
C
W W W 2 4
6

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8 4 6
Rs16 @(d:16, ERd) Rs16 @(d:24, ERd) 2 ERd32-2 ERd32 Rs16 @ERd 4 6 Rs16 @aa:16 Rs16 @aa:24 #xx:32 Rd32
W
8
10
W
6
MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, Rd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd
W W L L L L 6 2 4 6
6 8 6 2 8 10
ERs32 ERd32 @ERs ERd32
@(d:16, ERs) ERd32 @(d:24, ERs) ERd32 4 @ERs ERd32 ERs32+4 ERs32 6 8 @aa:16 ERd32 @aa:24 ERd32 ERs32 @ERd -- --
L
10
14
L
10
MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs, @ERd MOV.L ERs, @(d:16, ERd) MOV.L ERs, @(d:24, ERd) MOV.L ERs, @-ERd
L L L L 4 6
10 12 8 10
ERs32 @(d:16, ERd) ERs32 @(d:24, ERd) 4 ERd32-4 ERd32 ERs32 @ERd 6 8 ERs32 @aa:16 ERs32 @aa:24 2 @SP Rn16 SP+2 SP 4 @SP ERn32 SP+4 SP
L
10
14
L
10
MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 POP.W Rn W
L L W
10 12 6
POP.L ERn L
L
10
Rev.5.00 Sep. 12, 2007 Page 610 of 764 REJ09B0396-0500
Advanced
@(d, PC)
Normal
@ERn
@@aa
Appendix A Instruction Set
Addressing Mode and Instruction Length (bytes) No. of States*1
@-ERn/@ERn+
Operand Size
@(d, ERn)
@aa
Condition Code
Mnemonic PUSH.W Rn
Operation
I
HN
Z
V
C
W
2 SP-2 SP Rn16 @SP 4 SP-4 SP ERn32 @SP 4 Cannot be used in the H8/3006 and H8/3007 Cannot be used in the H8/3006 and H8/3007

0 0
6
PUSH.L ERn
L
10
MOVFPE @aa:16, Rd MOVTPE Rs, @aa:16
B
Cannot be used in the H8/3006 and H8/3007 Cannot be used in the H8/3006 and H8/3007
B
4
2. Arithmetic instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
@-ERn/@ERn+
Operand Size
@(d, ERn)
@aa
Condition Code
Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd
Operation Rd8+#xx:8 Rd8
I
HN
Z
V
C
B B
2 2
2 2 4 2 6
Rd8+Rs8 Rd8 Rd16+#xx:16 Rd16
W4 W L 6 2
(1) (1) (2) (2) (3) (3)
Rd16+Rs16 Rd16 ERd32+#xx:32 ERd32
ADD.L ERs, ERd
L
2
ERd32+ERs32 ERd32 Rd8+#xx:8 +C Rd8
2
ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS.L #1, ERd ADDS.L #2, ERd ADDS.L #4, ERd INC.B Rd INC.W #1, Rd INC.W #2, Rd
B B L L L B W W
2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2
Rd8+Rs8 +C Rd8 ERd32+1 ERd32 ERd32+2 ERd32 ERd32+4 ERd32 Rd8+1 Rd8 Rd16+1 Rd16 Rd16+2 Rd16

Rev.5.00 Sep. 12, 2007 Page 611 of 764 REJ09B0396-0500
Advanced
@(d, PC)
Normal
@@aa
@ERn
#xx
Rn
Advanced
@(d, PC)
Normal
@@aa
@ERn
#xx
Rn
Appendix A Instruction Set
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
No. of States*1
@(d, ERn)
#xx
Rn
@aa
Condition Code
Mnemonic INC.L #1, ERd INC.L #2, ERd DAA Rd
Operation ERd32+1 ERd32 ERd32+2 ERd32 Rd8 decimal adjust Rd8 Rd8-Rs8 Rd8 Rd16-#xx:16 Rd16
I
HN
Z
V
C
L L B
2 2 2
* (1) (1) (2) (2) (3) (3)
2 2 2
*
SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd
B W4 W L 6
2
2 4 2 6
2
Rd16-Rs16 Rd16 ERd32-#xx:32 ERd32
SUB.L ERs, ERd
L
2
ERd32-ERs32 ERd32 Rd8-#xx:8-C Rd8
2
SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS.L #1, ERd SUBS.L #2, ERd SUBS.L #4, ERd DEC.B Rd DEC.W #1, Rd DEC.W #2, Rd DEC.L #1, ERd DEC.L #2, ERd DAS.Rd
B B L L L B W W L L B
2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2
Rd8-Rs8-C Rd8 ERd32-1 ERd32 ERd32-2 ERd32 ERd32-4 ERd32 Rd8-1 Rd8 Rd16-1 Rd16 Rd16-2 Rd16 ERd32-1 ERd32 ERd32-2 ERd32 Rd8 decimal adjust Rd8
* *
MULXU. B Rs, Rd
B
2
Rd8 x Rs8 Rd16 (unsigned multiplication) Rd16 x Rs16 ERd32 (unsigned multiplication) Rd8 x Rs8 Rd16 (signed multiplication) Rd16 x Rs16 ERd32 (signed multiplication) Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (unsigned division)
14
MULXU. W Rs, ERd
W
2
22
MULXS. B Rs, Rd
B
4
16
MULXS. W Rs, ERd
W
4
24
DIVXU. B Rs, Rd
B
2
(6) (7)
14
Rev.5.00 Sep. 12, 2007 Page 612 of 764 REJ09B0396-0500
Advanced
@(d, PC)
Normal
@ERn
@@aa
Appendix A Instruction Set
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
No. of States*1
@(d, ERn)
@(d, PC)
@@aa
@aa
Condition Code
Mnemonic DIVXU. W Rs, ERd
Operation
I
HN
Z
V
C
W
2
ERd32 / Rs16 ERd32 (6) (7) (Ed: remainder, Rd: quotient) (unsigned division) Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (signed division) (8) (7)
22
DIVXS. B Rs, Rd
B
4
16
DIVXS. W Rs, ERd
W
4
ERd32 / Rs16 ERd32 (8) (7) (Ed: remainder, Rd: quotient) (signed division) Rd8-#xx:8 (1) (1) (2) (2) 0 0 0 0 0 0
24
CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd NEG.B Rd NEG.W Rd NEG.L ERd EXTU.W Rd
B B
2 2
2 2 4 2 6 2 2 2 2 2
Rd8-Rs8 Rd16-#xx:16
W4 W L L B W L W 6 2 2 2 2 2 2
Rd16-Rs16 ERd32-#xx:32 ERd32-ERs32 0-Rd8 Rd8 0-Rd16 Rd16 0-ERd32 ERd32 0 ( of Rd16) 0 ( of ERd32)
EXTU.L ERd
L
2
2
EXTS.W Rd
W
2
( of Rd16) ( of Rd16) ( of ERd32) ( of ERd32)
2
EXTS.L ERd
L
2
2
Rev.5.00 Sep. 12, 2007 Page 613 of 764 REJ09B0396-0500
Advanced
Normal
@ERn
#xx
Rn
Appendix A Instruction Set
3. Logic instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
@-ERn/@ERn+
Operand Size
@(d, ERn)
@aa
Condition Code
Mnemonic AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd NOT.B Rd NOT.W Rd NOT.L ERd
Operation Rd8#xx:8 Rd8
I
HN
Z
V
C
B B
2 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2
Rd8Rs8 Rd8 Rd16#xx:16 Rd16
W4 W L L B B W4 W L L B B W4 W L L B W L 6 4 2 2 2 2 2 2 6 4 2 2 2 6 4 2
Rd16Rs16 Rd16
ERd32#xx:32 ERd32 ERd32ERs32 ERd32 Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16
ERd32#xx:32 ERd32 ERd32ERs32 ERd32 Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16
ERd32#xx:32 ERd32 ERd32ERs32 ERd32 Rd8 Rd8 Rd16 Rd16 Rd32 Rd32
Rev.5.00 Sep. 12, 2007 Page 614 of 764 REJ09B0396-0500
Advanced
@(d, PC)
Normal
@@aa
@ERn
#xx
Rn
Appendix A Instruction Set
4. Shift instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
@-ERn/@ERn+
Operand Size
@(d, ERn)
@aa
Condition Code
Mnemonic SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR.B Rd SHLR.W Rd SHLR.L ERd ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR.B Rd ROTR.W Rd ROTR.L ERd
Operation
I
HN
Z
V
C
B W L B W L B W L B W L B W L B W L B W L B W L
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
C MSB LSB
0

C MSB LSB

C MSB LSB
0

0 MSB LSB
C

C MSB LSB

C MSB LSB

C MSB LSB

C MSB LSB

Rev.5.00 Sep. 12, 2007 Page 615 of 764 REJ09B0396-0500
Advanced
@(d, PC)
Normal
@@aa
@ERn
#xx
Rn
Appendix A Instruction Set
5. Bit manipulation instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
@-ERn/@ERn+
Operand Size
@(d, ERn)
@aa
Condition Code
Mnemonic BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BNOT #xx:3, Rd
Operation (#xx:3 of Rd8) 1
I
HN
Z
V
C
B B B B B B B B B B B B B
2 4 4 2 4 4 2 4 4 2 4 4 2

2 8 8 2 8 8 2 8 8 2 8 8 2
(#xx:3 of @ERd) 1 (#xx:3 of @aa:8) 1 (Rn8 of Rd8) 1 (Rn8 of @ERd) 1 (Rn8 of @aa:8) 1 (#xx:3 of Rd8) 0 (#xx:3 of @ERd) 0 (#xx:3 of @aa:8) 0 (Rn8 of Rd8) 0 (Rn8 of @ERd) 0 (Rn8 of @aa:8) 0 (#xx:3 of Rd8) (#xx:3 of Rd8)
BNOT #xx:3, @ERd
B
4
(#xx:3 of @ERd) (#xx:3 of @ERd) 4 (#xx:3 of @aa:8) (#xx:3 of @aa:8) (Rn8 of Rd8) (Rn8 of Rd8)
8
BNOT #xx:3, @aa:8
B
8
BNOT Rn, Rd
B
2
2
BNOT Rn, @ERd
B
4
(Rn8 of @ERd) (Rn8 of @ERd) 4 (Rn8 of @aa:8) (Rn8 of @aa:8) (#xx:3 of Rd8) Z
8
BNOT Rn, @aa:8
B
8
BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BLD #xx:3, Rd
B B B B B B B
2 4 4 2 4 4 2
2 6 6 2 6 6 2
(#xx:3 of @ERd) Z (#xx:3 of @aa:8) Z (Rn8 of @Rd8) Z (Rn8 of @ERd) Z (Rn8 of @aa:8) Z (#xx:3 of Rd8) C
Rev.5.00 Sep. 12, 2007 Page 616 of 764 REJ09B0396-0500
Advanced
@(d, PC)
Normal
@@aa
@ERn
#xx
Rn
Appendix A Instruction Set
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
No. of States*1
@(d, ERn)
@aa
Condition Code
Mnemonic BLD #xx:3, @ERd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 BIAND #xx:3, Rd
Operation (#xx:3 of @ERd) C
I
HN
Z
V
C
B B B B B B B B B B B B B B B 2 2 2 2 2
4 4

6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6
(#xx:3 of @aa:8) C (#xx:3 of Rd8) C
4 4
(#xx:3 of @ERd) C (#xx:3 of @aa:8) C C (#xx:3 of Rd8)
4 4
C (#xx:3 of @ERd24) C (#xx:3 of @aa:8) C (#xx:3 of Rd8)
4 4
C (#xx:3 of @ERd24) C (#xx:3 of @aa:8) C(#xx:3 of Rd8) C
4 4
C(#xx:3 of @ERd24) C C(#xx:3 of @aa:8) C C(#xx:3 of Rd8) C
BIAND #xx:3, @ERd B BIAND #xx:3, @aa:8 B BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BIOR #xx:3, Rd BIOR #xx:3, @ERd BIOR #xx:3, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 BIXOR #xx:3, Rd B B B B B B B B B B 2 2 2 2
4 4
C(#xx:3 of @ERd24) C C(#xx:3 of @aa:8) C C(#xx:3 of Rd8) C
4 4
C(#xx:3 of @ERd24) C C(#xx:3 of @aa:8) C C(#xx:3 of Rd8) C
4 4
C(#xx:3 of @ERd24) C C(#xx:3 of @aa:8) C C(#xx:3 of Rd8) C
4 4
C(#xx:3 of @ERd24) C C(#xx:3 of @aa:8) C C(#xx:3 of Rd8) C
BIXOR #xx:3, @ERd B BIXOR #xx:3, @aa:8 B
4 4
C(#xx:3 of @ERd24) C C(#xx:3 of @aa:8) C
Rev.5.00 Sep. 12, 2007 Page 617 of 764 REJ09B0396-0500
Advanced
@(d, PC)
Normal
@@aa
@ERn
#xx
Rn
Appendix A Instruction Set
6. Branching instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
@-ERn/@ERn+
Operand Size
@(d, ERn)
Mnemonic BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8)
Branch Operation Condition If condition Always is true then PC PC+d else Never next; CZ=0
#xx
Rn
@aa
Condition Code I HN Z V C

2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4

4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6
CZ=1

C=0

BCC d:16 (BHS d:16) BCS d:8 (BLO d:8)
C=1

BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16
Z=0

Z=1

V=0

V=1

N=0

N=1

NV = 0

NV = 1

Z (NV) =0

Rev.5.00 Sep. 12, 2007 Page 618 of 764 REJ09B0396-0500
Advanced
@(d, PC)
Normal
@ERn
@@aa
Appendix A Instruction Set
Addressing Mode and Instruction Length (bytes) No. of States*1
@-ERn/@ERn+
Operand Size
@(d, ERn)
Mnemonic BLE d:8 BLE d:16
Branch Operation Condition
@aa
Condition Code I HN Z V C

2 4
If condition Z (NV) = 0 is true then Z (NV) = 1 PC PC+d else next; PC ERn 8 6
4 6
JMP @ERn JMP @aa:24 JMP @@aa:8 BSR d:8

2 4 2 2
4 6 10 8
PC aa:24 PC @aa:8 PC @-SP PC PC+d:8 PC @-SP PC PC+d:16 PC @-SP PC @ERn
BSR d:16
4
8
10
JSR @ERn
2
6
JSR @aa:24
4
PC @-SP PC @aa:24 2 PC @-SP PC @aa:8 2 PC @SP+
8
10
JSR @@aa:8
8
12
RTS
8
10
Rev.5.00 Sep. 12, 2007 Page 619 of 764 REJ09B0396-0500
Advanced
8
@(d, PC)
Normal
@@aa
@ERn
#xx
Rn
Appendix A Instruction Set
7. System control instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
@-ERn/@ERn+
Operand Size
@(d, ERn)
#xx
Rn
@aa
Condition Code
Mnemonic TRAPA #x:2
Operation
I
HN
Z
V
C
2 PC @-SP CCR @-SP PC CCR @SP+ PC @SP+
1 14 16
RTE
B B W W 2 2 4 6
10
SLEEP
Transition to powerdown state #xx:8 CCR Rs8 CCR @ERs CCR @(d:16, ERs) CCR @(d:24, ERs) CCR 4 @ERs CCR ERs32+2 ERs32 6 8 2 4 6 @aa:16 CCR @aa:24 CCR CCR Rd8 CCR @ERd CCR @(d:16, ERd) CCR @(d:24, ERd) 4 ERd32-2 ERd32 CCR @ERd 6 8 2 2 2 CCR @aa:16 CCR @aa:24 CCR#xx:8 CCR CCR#xx:8 CCR CCR#xx:8 CCR 2 PC PC+2
2
LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR
2 2 6 8
W
10
12
W
8
LDC @aa:16, CCR LDC @aa:24, CCR STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16, ERd) STC CCR, @(d:24, ERd) STC CCR, @-ERd
W W B W W
8 10 2 6 8
W
10
12
W
8
STC CCR, @aa:16 STC CCR, @aa:24 ANDC #xx:8, CCR ORC #xx:8, CCR XORC #xx:8, CCR NOP
W W B B B
8 10 2 2 2 2
Rev.5.00 Sep. 12, 2007 Page 620 of 764 REJ09B0396-0500
Advanced
@(d, PC)
Normal
@ERn
@@aa
Appendix A Instruction Set
8. Block transfer instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
@-ERn/@ERn+
Operand Size
@(d, ERn)
@aa
Condition Code
Mnemonic EEPMOV. B
Operation
I
HN
Z
V
C
4 if R4L 0 8+ repeat @R5 @R6 4n*2 R5+1 R5 R6+1 R6 R4L-1 R4L until R4L=0 else next; 4 if R4 0 repeat @R5 @R6 R5+1 R5 R6+1 R6 R4-1 R4 until R4=0 else next; 8+ 4n*2
EEPMOV. W
Notes: 1. The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. For other cases see appendix A.3, Number of States Required for Execution. Normal mode is not available in the H8/3006 and H8/3007. 2. n is the value set in register R4L or R4. (1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) Retains its previous value when the result is zero; otherwise cleared to 0. (4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) The number of states required for execution of an instruction that transfers data in synchronization with the E clock is variable. (6) Set to 1 when the divisor is negative; otherwise cleared to 0. (7) Set to 1 when the divisor is zero; otherwise cleared to 0. (8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Rev.5.00 Sep. 12, 2007 Page 621 of 764 REJ09B0396-0500
Advanced
@(d, PC)
Normal
@@aa
@ERn
#xx
Rn
A.2
Table A.2
Instruction code: Instruction when most significant bit of BH is 1.
4 ORC ADD SUB Table A.2 Table A.2 (2) (2) CMP OR.B XOR.B AND.B Table A.2 (2) XORC ANDC LDC Table A.2 Table A.2 (2) (2) MOV ADDX SUBX 5 6 7 8 9 A B C D E F Table A.2 (2) Table A.2 (2)
1st byte 2nd byte AH AL BH BL Instruction when most significant bit of BH is 0.
2 STC LDC 3
AL
AH
0
1
Appendix A Instruction Set
0
NOP
Table A.2 (2)
1
Table A.2 Table A.2 Table A.2 Table A.2 (2) (2) (2) (2)
2 MOV.B
Operation Code Maps
Operation Code Map (1)
Rev.5.00 Sep. 12, 2007 Page 622 of 764 REJ09B0396-0500
BHI BVS JMP MOV MOV BIOR ADD ADDX CMP SUBX OR XOR AND MOV BIXOR BIAND BILD Table A.2 Table A.2 EEPMOV (2) (2) Table A.2 (3) DIVXU BST OR BTST BOR BXOR BAND BIST BLD XOR AND RTS BSR RTE TRAPA Table A.2 (2) BLS BCC BCS BNE BNQ BVC BPL BMI BGE BSR BLT BGT JSR BLE
3
4
BRA
BRN
5
MULXU
DIVXU
MULXU
6
BSET
BNOT
BCLR
7
8
9
A
B
C
D
E
F
Table A.2
Instruction code:
1st byte 2nd byte AH AL BH BL
2 LDC/STC SLEEP ADD INC ADDS MOV SHLL SHAL SHAR ROTL ROTR EXTU EXTU NEG SHLR ROTXL ROTXR NOT SHAL SHAR ROTL ROTR NEG SUB DEC DEC SUBS CMP BHI BLS SUB SUB OR OR CMP CMP BCC BCS XOR XOR BNE AND AND BEQ BVC BVS BPL BMI BGE BLT BGT BLE DEC DEC EXTS EXTS INC INC INC Table A.2 Table A.2 (3) (3) 3 4 5 6 7 8 9 A B C D E F Table A.2 (3)
BH AH AL
0
1
01
MOV
0A
INC
0B
ADDS
Operation Code Map (2)
0F
DAA
10
SHLL
11
SHLR
12
ROTXL
13
ROTXR
17
NOT
1A
DEC
1B
SUBS
1F
DAS
58
BRA
BRN
79
MOV
ADD
Appendix A Instruction Set
Rev.5.00 Sep. 12, 2007 Page 623 of 764 REJ09B0396-0500
7A
MOV
ADD
Table A.2
Instruction code: Instruction when most significant bit of DH is 1.
1st byte 2nd byte 3rd byte 4th byte AH AL BH BL CH CL DH DL Instruction when most significant bit of DH is 0.
CL 2 3 4 5 6 7 8 9 A B C D E F
AH ALBH BLCH LDC STC STC MULXS DIVXS OR BTST BOR BTST BIOR BCLR BIST BCLR BTST BOR BTST BIOR BCLR BIST BCLR BIXOR BIAND BILD BST BXOR BAND BLD BIXOR BIAND BILD BST BXOR BAND BLD XOR AND LDC LDC STC
0
1
Appendix A Instruction Set
01406
LDC STC
01C05
MULXS
Operation Code Map (3)
Rev.5.00 Sep. 12, 2007 Page 624 of 764 REJ09B0396-0500
01D05
DIVIXS
01F06
7Cr06 * 1
7Cr07 * 1
7Dr06 * 1
BSET
BNOT
7Dr07 * 1
BSET
BNOT
7Eaa6 * 2
7Eaa7 * 2
7Faa6 * 2
BSET
BNOT
7Faa7 * 2
BSET
BNOT
Notes: 1. r is the register designation field. 2. aa is the absolute address field.
Appendix A Instruction Set
A.3
Number of States Required for Execution
The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table A.4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.3 indicates the number of states required per cycle according to the bus size. The number of states required for execution of an instruction can be calculated from these two tables as follows: Number of states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN Examples of Calculation of Number of States Required for Execution Examples: Advanced mode, stack located in external address space, on-chip supporting modules accessed with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. BSET #0, @FFFFC7:8 From table A.4, I = L = 2 and J = K = M = N = 0 From table A.3, SI = 4 and SL = 3 Number of states = 2 x 4 + 2 x 3 = 14 JSR @@30 From table A.4, I = J = K = 2 and L = M = N = 0 From table A.3, SI = SJ = SK = 4 Number of states = 2 x 4 + 2 x 4 + 2 x 4 = 24
Rev.5.00 Sep. 12, 2007 Page 625 of 764 REJ09B0396-0500
Appendix A Instruction Set
Table A.3
Number of States per Cycle
Access Conditions On-Chip Supporting Module External Device 8-Bit Bus 2-State Access 4 3-State Access 6 + 2m 16-Bit Bus 2-State Access 2 3-State Access 3+m
Cycle Instruction fetch SI SK SL SM
On-Chip 8-Bit Memory Bus 2 6
16-Bit Bus 3
Branch address read SJ Stack operation Byte data access Word data access Internal operation 3 6 2 4 3+m 6 + 2m
SN 1
Legend: m: Number of wait states inserted into external device access
Rev.5.00 Sep. 12, 2007 Page 626 of 764 REJ09B0396-0500
Appendix A Instruction Set
Table A.4
Number of Cycles per Instruction
Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1
Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS #1/2/4, ERd ADDX #xx:8, Rd ADDX Rs, Rd AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @ BAND #xx:3, @aa:8 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8
ADDS ADDX AND
ANDC BAND
Bcc
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Appendix A Instruction Set
Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 2 2 1 1 1 1 1 1 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Instruction Mnemonic Bcc BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BIAND #xx:3, BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 BIOR #xx:8, Rd BIOR #xx:8, @ BIOR #xx:8, @aa:8 BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BIXOR #xx:3, Rd BIXOR #xx:3, @ BIXOR #xx:3, @aa:8 BLD #xx:3, Rd BLD #xx:3, @ERd BLD #xx:3, @aa:8
BCLR
BIAND
BILD
BIOR
BIST
BIXOR
BLD
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Appendix A Instruction Set
Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 1 2 2 2 1 1 1 1 1 1 2 2 2 2 2 2 1 1 2 2 2 2
Instruction Mnemonic BNOT BNOT #xx:3, BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BSR d:8 Normal*1
BOR
BSET
BSR
Advanced 2 BSR d:16 Normal*1 2
Advanced 2 BST BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd DAA Rd DAS Rd 1 2 2 1 2 2 1 2 2 1 2 2 1 1 2 1 3 1 1 1
BTST
BXOR
CMP
DAA DAS
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Appendix A Instruction Set
Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 1 1 2 2 1 1 2 2 1 1 1 1 1 1 2 2
1
Instruction Mnemonic DEC DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU.B Rs, Rd DIVXU.W Rs, ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1/2, Rd INC.L #1/2, ERd JMP @ERn JMP @aa:24
DIVXS DIVXU EEPMOV EXTS EXTU INC
12 20 12 20 2n + 2*2 2n + 2*2
JMP
2 1 2 1 2 1 2 1 2 1 2 2 2 2 2
JMP @@aa:8 Normal* 2 Advanced 2 JSR JSR @ERn Normal*1 2 Advanced 2 JSR @aa:24 Normal* 2 Advanced 2 JSR @@aa:8 Normal* 2 Advanced 2 LDC 1 LDC #xx:8, CCR 1 LDC Rs, CCR 2 LDC @ERs, CCR LDC @(d:16, ERs), CCR 3 LDC @(d:24, ERs), CCR 5 2 LDC @ERs+, CCR 3 LDC @aa:16, CCR 4 LDC @aa:24, CCR
1 1
1 1 1 1 1 1
2
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Appendix A Instruction Set
Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N
Instruction Mnemonic MOV
MOV.B #xx:8, Rd 1 MOV.B Rs, Rd 1 MOV.B @ERs, Rd 1 MOV.B @(d:16, ERs), Rd 2 MOV.B @(d:24, ERs), Rd 4 MOV.B @ERs+, Rd 1 MOV.B @aa:8, Rd 1 MOV.B @aa:16, Rd 2 MOV.B @aa:24, Rd 3 MOV.B Rs, @ERd 1 MOV.B Rs, @(d:16, ERd) 2 MOV.B Rs, @(d:24, ERd) 4 MOV.B Rs, @-ERd 1 MOV.B Rs, @aa:8 1 MOV.B Rs, @aa:16 2 MOV.B Rs, @aa:24 3 MOV.W #xx:16, Rd 2 MOV.W Rs, Rd 1 MOV.W @ERs, Rd 1 MOV.W @(d:16, ERs), Rd 2 MOV.W @(d:24, ERs), Rd 4 MOV.W @ERs+, Rd 1 MOV.W @aa:16, Rd 2 MOV.W @aa:24, Rd 3 MOV.W Rs, @ERd 1 MOV.W Rs, @(d:16, ERd) 2 MOV.W Rs, @(d:24, ERd) 4 MOV.W Rs, @-ERd 1 MOV.W Rs, @aa:16 2 MOV.W Rs, @aa:24 3 MOV.L #xx:32, ERd 3 MOV.L ERs, ERd 1 MOV.L @ERs, ERd 2 MOV.L @(d:16, ERs), ERd 3 MOV.L @(d:24, ERs), ERd 5 MOV.L @ERs+, ERd 2 MOV.L @aa:16, ERd 3 MOV.L @aa:24, ERd 4 MOV.L ERs, @ERd 2 MOV.L ERs, @(d:16, ERd) 3 MOV.L ERs, @(d:24, ERd) 5 MOV.L ERs, @-ERd 2 MOV.L ERs, @aa:16 3 MOV.L ERs, @aa:24 4
1 1 1 1 1 1 1 1 1 1 1 1 1 1
2
2
1 1 1 1 1 1 1 1 1 1 1 1
2
2
2 2 2 2 2 2 2 2 2 2 2 2
2
2
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Appendix A Instruction Set
Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 1 12 20 12 20
Instruction Mnemonic MOVFPE MOVTPE MULXS MULXU NEG
MOVFPE @aa:16, Rd*12 MOVTPE Rs, @aa:16* 2 MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU.B Rs, Rd MULXU.W Rs, ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd ORC #xx:8, CCR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR.B Rd ROTR.W Rd ROTR.L ERd ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd RTE 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 2 2
1
NOP NOT
OR
ORC POP PUSH ROTL
1 2 1 2
2 2 2 2
ROTR
ROTXL
ROTXR
RTE
2
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Appendix A Instruction Set
Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N Normal*1 2 Advanced 2 SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR.B Rd SHLR.W Rd SHLR.L ERd SLEEP 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2
Instruction Mnemonic RTS RTS
SHAR
SHLL
SHLR
SLEEP STC
1 STC CCR, Rd 2 STC CCR, @ERd STC CCR, @(d:16, ERd) 3 STC CCR, @(d:24, ERd) 5 2 STC CCR, @-ERd 3 STC CCR, @aa:16 4 STC CCR, @aa:24 SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd SUBS #1/2/4, ERd SUBX #xx:8, Rd SUBX Rs, Rd 1 2 1 3 1 1 1 1 1 2 2 2
2
SUB
SUBS SUBX TRAPA XOR
TRAPA #x:2 Normal*1 2 Advanced 2 XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd XORC #xx:8, CCR 1 1 2 1 3 2 1
4 4
XORC
Notes: 1. Not available in the H8/3006 and H8/3007. 2. n is the value set in register R4L or R4. The source and destination are accessed n + 1 times each.
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Appendix B Internal I/O Registers
Appendix B Internal I/O Registers
B.1
Address (Low) H'EE000 H'EE001 H'EE002 H'EE003 H'EE004 H'EE005 H'EE006 H'EE007 H'EE008 H'EE009 H'EE00A H'EE00B H'EE00C H'EE00D H'EE00E H'EE00F H'EE010 H'EE011 H'EE012 H'EE013 H'EE014 H'EE015 H'EE016 H'EE017 H'EE018 H'EE019 H'EE01A H'EE01B H'EE01C H'EE01D H'EE01E P4DDR 8 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR 8 8 8 8 P41DDR P40DDR Port 4
Addresses
Data Register Bus Width Bit 7 Name Register Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module name
Reserved area (access prohibited)
Reserved area (access prohibited) P6DDR P8DDR P9DDR PADDR PBDDR MDCR SYSCR BRCR ISCR IER ISR IPRA IPRB 8 8 8 8 8 8 8 8 8 P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P81DDR P91DDR PA1DDR PB1DDR MDS1 SSOE IRQ1SC IRQ1E IRQ1F IPRA1 IPRB1 DIV1 P60DDR P80DDR P90DDR PA0DDR PB0DDR MDS0 RAME BRLE IRQ0SC IRQ0E IRQ0F IPRA0 DASTE DIV0 D/A converter System control System control Bus controller Interrupt controller Port 8 Port 9 Port A Port B Port 6
P84DDR P83DDR P82DDR
P95DDR P94DDR P93DDR P92DDR
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR SSBY A23E IPRA7 IPRB7 PSTOP STS2 A22E IPRA6 IPRB6 STS1 A21E STS0 A20E UE MDS2 NMIEG
IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ5E IRQ5F IPRA5 IPRB5 IRQ4E IRQ4F IPRA4 IRQ3E IRQ3F IPRA3 IPRB3 IRQ2E IRQ2F IPRA2 IPRB2
DASTCR 8 DIVCR 8
MSTCRH 8 MSTCRL 8
MSTPH2 MSTPH1 MSTPH0 MSTPL0
MSTPL7
MSTPL5 MSTPL4 MSTPL3 MSTPL2
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Appendix B Internal I/O Registers
Data Register Bus Name Width Bit 7 CSCR ABWCR ASTCR WCRH WCRL BCR DRCRA DRCRB 8 8 8 8 8 8 8 8 CS7E ABW7 AST7 W71 W31 ICIS1 DRAS2 MXC1 CMF
Address (Low) H'EE01F H'EE020 H'EE021 H'EE022 H'EE023 H'EE024 H'EE025 H'EE026 H'EE027 H'EE028 H'EE029 H'EE02A H'EE02B H'EE02C H'EE02D H'EE02E H'EE02F H'EE030 H'EE031 H'EE032 H'EE033 H'EE034 H'EE035 H'EE036 H'EE037 H'EE038 H'EE039 H'EE03A H'EE03B H'EE03C H'EE03D H'EE03E H'EE03F
Register Name Bit 6 CS6E ABW6 AST6 W70 W30 ICIS0 DRAS1 MXC0 CMIE Bit 5 CS5E ABW5 AST5 W61 W21 Bit 4 CS4E ABW4 AST4 W60 W20 Bit 3 ABW3 AST3 W51 W11 Bit 2 ABW2 AST2 W50 W10 Bit 1 ABW1 AST1 W41 W01 RDEA SRFMD RCW Bit 0 ABW0 AST0 W40 W00 WAITE RFSHE RLW
Module name Bus controller
BROME BRSTS1 BRSTS0 DRAS0 CSEL CKS2 BE RDM TPC
RCYCE CKS1 CKS0
DRAM interface
RTMCSR 8 RTCNT RTCOR 8 8
Reserved area (access prohibited)

Reserved area (access prohibited) P4PCR 8 P41PCR P40PCR Port 4
P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR
Reserved area (access prohibited)
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Appendix B Internal I/O Registers
Data Bus Width Bit 7 8 8 8 8
Address (Low) H'FFF20 H'FFF21 H'FFF22 H'FFF23 H'FFF24 H'FFF25 H'FFF26 H'FFF27
Register Name MAR0AR MAR0AE MAR0AH MAR0AL
Register Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module name DMAC channel 0A
ETCR0AH 8 ETCR0AL 8 IOAR0A DTCR0A 8 8 DTE DTE DTSZ DTSZ DTID SAID RPE SAIDE DTIE DTIE DTS2 DTS1 DTS0 Short address mode
DTS2A DTS1A DTS0A Full address mode DMAC channel 0B
H'FFF28 H'FFF29 H'FFF2A H'FFF2B H'FFF2C H'FFF2D H'FFF2E H'FFF2F
MAR0BR MAR0BE MAR0BH MAR0BL
8 8 8 8
ETCR0BH 8 ETCR0BL 8 IOAR0B DTCR0B 8 8 DTE DTME DTSZ DTID DAID RPE DAIDE DTIE TMS DTS2 DTS1 DTS0 Short address mode
DTS2B DTS1B DTS0B Full address mode DMAC channel 1A
H'FFF30 H'FFF31 H'FFF32 H'FFF33 H'FFF34 H'FFF35 H'FFF36 H'FFF37
MAR1AR MAR1AE MAR1AH MAR1AL
8 8 8 8
ETCR1AH 8 ETCR1AL 8 IOAR1A DTCR1A 8 8 DTE DTE DTSZ DTSZ DTID SAID RPE SAIDE DTIE DTIE DTS2 DTS1 DTS0 Short address mode
DTS2A DTS1A DTS0A Full address mode DMAC channel 1B
H'FFF38 H'FFF39 H'FFF3A H'FFF3B H'FFF3C H'FFF3D H'FFF3E H'FFF3F
MAR1BR MAR1BE MAR1BH MAR1BL
8 8 8 8
ETCR1BH 8 ETCR1BL 8 IOAR1B DTCR1B 8 8 DTE DTME DTSZ DTID DAID RPE DAIDE DTIE TMS DTS2 DTS1 DTS0 Short address mode
DTS2B DTS1B DTS0B Full address mode
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Appendix B Internal I/O Registers
Data Register Bus Name Width Bit 7
Address (Low) H'FFF40 H'FFF41 H'FFF42 H'FFF43 H'FFF44 H'FFF45 H'FFF46 H'FFF47 H'FFF48 H'FFF49 H'FFF4A H'FFF4B H'FFF4C H'FFF4D H'FFF4E H'FFF4F H'FFF50 H'FFF51 H'FFF52 H'FFF53 H'FFF54 H'FFF55 H'FFF56 H'FFF57 H'FFF58 H'FFF59 H'FFF5A H'FFF5B H'FFF5C H'FFF5D H'FFF5E H'FFF5F
Register Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Module name
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Appendix B Internal I/O Registers
Data Bus Width Bit 7 8 8 8 8 8 8 8
Address Register (Low) Name H'FFF60 TSTR H'FFF61 TSNC H'FFF62 TMDR H'FFF63 TOLR H'FFF64 TISRA H'FFF65 TISRB H'FFF66 TISRC H'FFF67 H'FFF68 16TCR0 H'FFF69 TIOR0
Register Name Bit 6 MDF IMIEA2 IMIEB2 OVIE2 Bit 5 FDIR TOB2 IMIEA1 IMIEB1 OVIE1 Bit 4 TOA2 IMIEA0 IMIEB0 OVIE0 Bit 3 TOB1 Bit 2 STR2 SYNC2 PWM2 TOA1 IMFA2 IMFB2 OVF2 Bit 1 STR1 SYNC1 PWM1 TOB0 IMFA1 IMFB1 OVF1 Bit 0 STR0 SYNC0 PWM0 TOA0 IMFA0 IMFB0 OVF0
Module name 16-bit timer, (all channels)
8 8

CCLR1 IOB2
CCLR0 IOB1
CKEG1 IOB0
CKEG0
TPSC2 IOA2
TPSC1 IOA1
TPSC0 IOA0
16-bit timer channel 0
H'FFF6A 16TCNT0H 16 H'FFF6B 16TCNT0L H'FFF6C GRA0H H'FFF6D GRA0L H'FFF6E GRB0H H'FFF6F GRB0L H'FFF70 16TCR1 H'FFF71 TIOR1 8 8 CCLR1 IOB2 CCLR0 IOB1 CKEG1 IOB0 CKEG0 TPSC2 IOA2 TPSC1 IOA1 TPSC0 IOA0 16-bit timer channel 1 16 16
H'FFF72 16TCNT1H 16 H'FFF73 16TCNT1L H'FFF74 GRA1H H'FFF75 GRA1L H'FFF76 GRB1H H'FFF77 GRB1L H'FFF78 16TCR2 H'FFF79 TIOR2 8 8 CCLR1 IOB2 CCLR0 IOB1 CKEG1 IOB0 CKEG0 TPSC2 IOA2 TPSC1 IOA1 TPSC0 IOA0 16-bit timer channel 2 16 16
H'FFF7A 16TCNT2H 16 H'FFF7B 16TCNT2L H'FFF7C GRA2H H'FFF7D GRA2L H'FFF7E GRB2H H'FFF7F GRB2L 16 16
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Appendix B Internal I/O Registers
Data Bus Width Bit 7 8 8 8 8 8 8 8 8 8 8
1
Address Register (Low) Name H'FFF80 H'FFF81 H'FFF82 H'FFF83 H'FFF84 H'FFF85 H'FFF86 H'FFF87 H'FFF88 H'FFF89 8TCR0 8TCR1 8TCSR0 8TCSR1 TCORA0 TCORA1 TCORB0 TCORB1 8TCNT0 8TCNT1
Register Name Bit 6 CMIEA CMIEA CMFA CMFA Bit 5 OVIE OVIE OVF OVF Bit 4 CCLR1 CCLR1 ADTE ICE Bit 3 CCLR0 CCLR0 OIS3 OIS3 Bit 2 CKS2 CKS2 OIS2 OIS2 Bit 1 CKS1 CKS1 OS1 OS1 Bit 0 CKS0 CKS0 OS0 OS0
Module name 8-bit timer channels 0 and 1
CMIEB CMIEB CMFB CMFB
H'FFF8A H'FFF8B H'FFF8C TCSR* H'FFF8D TCNT* H'FFF8E H'FFF8F RSTCSR 1 * H'FFF90 H'FFF91 H'FFF92 H'FFF93 H'FFF94 H'FFF95 H'FFF96 H'FFF97 H'FFF98 H'FFF99 8TCR2 8TCR3 8TCSR2 8TCSR3 TCORA2 TCORA3 TCORB2 TCORB3 8TCNT2 8TCNT3 8 8 8 8 8 8 8 8 8 8 8 8 8
WT/IT RSTOE CMIEA CMIEA CMFA CMFA
TME OVIE OVIE OVF OVF
CCLR1 CCLR1 ICE
CCLR0 CCLR0 OIS3 OIS3
CKS2 CKS2 CKS2 OIS2 OIS2
CKS1 CKS1 CKS1 OS1 OS1
CKS0 CKS0 CKS0 OS0 OS0 8-bit timer channels 2 and 3 WDT
OVF WRST CMIEB CMIEB CMFB CMFB
1
H'FFF9A H'FFF9B H'FFF9C DADR0 H'FFF9D DADR1 H'FFF9E DACR H'FFF9F 8 8 8 8

D/A converter
DAOE1
DAOE0
DAE

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Appendix B Internal I/O Registers
Data Address Register Bus (Low) Name Width Bit 7 H'FFFA0 TPMR H'FFFA1 TPCR H'FFFA2 NDERB H'FFFA3 NDERA H'FFFA4 NDRB*
2
Register Name Bit 6 Bit 5 Bit 4 Bit 3 G3NOV Bit 2 G2NOV Bit 1 G1NOV Bit 0 G0NOV
Module name TPC
8 8 8 8 8
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER2 NDER2 MP NDER1 NDER1 NDER1 CKS1 NDER8 NDER0 NDER8 NDER0 NDER8 NDER0 CKS0 SCI channel 0
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER15 NDER14 NDER13 NDER12
H'FFFA5 NDRA*
2
8
NDER7 NDER7
NDER6 NDER6 CHR
NDER5 NDER5 PE
NDER4 NDER4 O/E
NDER3 NDER3 STOP
H'FFFA6 NDRB*
2
8
NDER11 NDER10 NDER9
H'FFFA7 NDRA* H'FFFA8 H'FFFA9 H'FFFAA H'FFFAB H'FFFAC H'FFFAD H'FFFAE H'FFFAF H'FFFB0 SMR H'FFFB1 BRR H'FFFB2 SCR H'FFFB3 TDR H'FFFB4 SSR H'FFFB5 RDR H'FFFB6 SCMR
2
8
8 8 8 8 8 8 8
C/A
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDRE
RDRF
ORER
FER/ERS PER
TEND
MPB
MPBT
SDIR
SINV
SMIF
H'FFFB7 Reserved area (access prohibited) H'FFFB8 SMR H'FFFB9 BRR H'FFFBA SCR H'FFFBB TDR H'FFFBC SSR H'FFFBD RDR H'FFFBE SCMR 8 8 8 8 8 8 8 SDIR SINV SMIF TDRE RDRF ORER FER/ERS PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 C/A CHR PE O/E STOP MP CKS1 CKS0 SCI channel 1
H'FFFBF Reserved area (access prohibited)
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Appendix B Internal I/O Registers
Data Register Bus Name Width Bit 7 SMR BRR SCR TDR SSR RDR SCMR 8 8 8 8 8 8 8 SDIR SINV SMIF TDRE RDRF ORER FER/ERS PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 C/A
Address (Low) H'FFFC0 H'FFFC1 H'FFFC2 H'FFFC3 H'FFFC4 H'FFFC5 H'FFFC6 H'FFFC7 H'FFFC8 H'FFFC9 H'FFFCA H'FFFCB H'FFFCC H'FFFCD H'FFFCE H'FFFCF H'FFFD0 H'FFFD1 H'FFFD2 H'FFFD3 H'FFFD4 H'FFFD5 H'FFFD6 H'FFFD7 H'FFFD8 H'FFFD9 H'FFFDA H'FFFDB H'FFFDC H'FFFDD H'FFFDE H'FFFDF
Register Name Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0
Module name SCI channel 2
Reserved area (access prohibited)
Reserved area (access prohibited)
P4DR
8
P47
P46
P45
P44
P43
P42
P41
P40
Port 4
Reserved area (access prohibited) P6DR P7DR P8DR P9DR PADR PBDR 8 8 8 8 8 8 P67 P77 PA7 PB7 P66 P76 PA6 PB6 P65 P75 P95 PA5 PB5 P64 P74 P84 P94 PA4 PB4 P63 P73 P83 P93 PA3 PB3 P62 P72 P82 P92 PA2 PB2 P61 P71 P81 P91 PA1 PB1 P60 P70 P80 P90 PA0 PB0 Port 6 Port 7 Port 8 Port 9 Port A Port B
Rev.5.00 Sep. 12, 2007 Page 641 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
Data Register Bus Name Width Bit 7 ADDRAH 8 ADDRAL 8 ADDRBH 8 ADDRBL 8 ADDRCH 8 ADDRCL 8 ADDRDH 8 ADDRDL 8 ADCSR ADCR 8 8 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGE
Address (Low) H'FFFE0 H'FFFE1 H'FFFE2 H'FFFE3 H'FFFE4 H'FFFE5 H'FFFE6 H'FFFE7 H'FFFE8 H'FFFE9
Register Name Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE Bit 5 AD7 AD7 AD7 AD7 ADST Bit 4 AD6 AD6 AD6 AD6 SCAN Bit 3 AD5 AD5 AD5 AD5 CKS Bit 2 AD4 AD4 AD4 AD4 CH2 Bit 1 AD3 AD3 AD3 AD3 CH1 Bit 0 AD2 AD2 AD2 AD2 CH0
Module name A/D converter
Legend: WDT: Watchdog timer TPC: Programmable timing pattern controller SCI: Serial communication interface Notes: 1. For write access to TCSR, TCNT, and RSTCSR, see section 12.2.4, Notes on Register Access. 2. The address depends on the output trigger setting.
Rev.5.00 Sep. 12, 2007 Page 642 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
B.2
Functions
Register abbreviation Register name TIER--Timer Interrupt Enable Register H' 90 Address to which register is mapped Name of on-chip supporting module FRT Bit numbers Bit 7 ICIAE
Initial value
6 ICIBE 0 R/W
5 ICICE 0 R/W
4
3
2
1 OVIE 1 R/W
0 1 Names of the bits. Dashes () indicate reserved bits.
Initial bit values R/W:
OCIDE OCIAE OCIBE 0 R/W 0 R/W 1 R/W
0 R/W
Possible types of access R W Read only Write only
Timer overflow interrupt enable 0 1
Interrupt requested by OVF flag is disabled Interrupt requested by OVF flag is enabled
R/W Read and write
Output compare interrupt B enable 0 1
Interrupt requested by OCFB flag is disabled Interrupt requested by OCFB flag is enabled
Full name of bit
Output compare interrupt A enable 0 1
Interrupt requested by OCFA flag is disabled Interrupt requested by OCFA flag is enabled
Descriptions of bit settings
Input capture interrupt D enable 0 1
Interrupt requested by ICFD flag is disabled Interrupt requested by ICFD flag is enabled
Rev.5.00 Sep. 12, 2007 Page 643 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
P4DDRPort 4 Data Direction Register
Bit 7 6 5 4
H'EE003
3 2 1 0
Port 4
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 4 input/output select 0 1 Generic input Generic output
P6DDRPort 6 Data Direction Register
Bit 7 Initial value Read/Write 1 6 5 4
H'EE005
3 2 1 0
Port 6
P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 6 input/output select 0 1 Generic input Generic output
Rev.5.00 Sep. 12, 2007 Page 644 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
P8DDRPort 8 Data Direction Register
Bit 7 Modes 1 to 4 Initial value Read/Write 1 6 1 5 1
H'EE007
4 3 2 1 0
Port 8
P84DDR P83DDR P82DDR P81DDR P80DDR 1 W 0 W 0 W 0 W 0 W
Port 8 input/output select 0 1 Port 8 input/output select 0 1 Generic input CS output Generic input Generic output
P9DDRPort 9 Data Direction Register
Bit 7 Initial value Read/Write 1 6 1 5 4
H'EE008
3 2 1 0
Port 9
P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR 0 W 0 W 0 W 0 W 0 W 0 W
Port 9 input/output select 0 1 Generic input Generic output
Rev.5.00 Sep. 12, 2007 Page 645 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
PADDRPort A Data Direction Register
Bit 7 6 5
H'EE009
4 3 2 1
Port A
0
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial value Read/Write Initial value Read/Write 1 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Modes 3, 4 Modes 1, 2
Port A input/output select 0 1 Generic input pin Generic output pin
PBDDRPort B Data Direction Register
Bit 7 6 5 4
H'EE00A
3 2 1 0
Port B
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port B input/output select 0 1 Generic input Generic output
Rev.5.00 Sep. 12, 2007 Page 646 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
MDCRMode Control Register
Bit 7 Initial value Read/Write 1 6 1 5 0 4 0
H'EE011
3 0 2 MDS2 * R 1 MDS1 * R 0
System control
MDS0 * R
Mode select 2 to 0 Bit 2 MD2 Bit 1 MD1 0 0 1 Bit 0 MD0 0 1 0 1 0 1 1 0 1 0 1 Note: * Determined by the state of the mode pins (MD2 to MD0). Mode 1 Mode 2 Mode 3 Mode 4 Operating Mode
Rev.5.00 Sep. 12, 2007 Page 647 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
SYSCRSystem Control Register
Bit 7 SSBY Initial value Read/Write 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W
H'EE012
2 NMIEG 0 R/W 1 SSOE 0 R/W 0 RAME 1 R/W
System control
RAM enable 0 1 On-chip RAM is disabled On-chip RAM is enabled
Software standby output port enable In software standby mode, all address bus and bus control signals are highimpedance In software standby mode, address bus retains output state and bus control signals are fixed high
0
1
NMI edge select An interrupt is requested at the falling edge of NMI 0 An interrupt is requested at the rising edge of NMI 1 User bit enable CCR bit 6 (UI) is used as an interrupt mask bit 0 CCR bit 6 (UI) is used as a user bit 1 Standby timer select 2 to 0 Bit 6 STS2 0 1 0 1 1 Bit 5 STS1 0 Bit 4 STS0 0 1 0 1 0 1 0 1 Standby Timer Waiting Time = 8,192 states Waiting Time = 16,384 states Waiting Time = 32,768 states Waiting Time = 65,536 states Waiting Time = 131,072 states Waiting Time = 26,2144 states Waiting Time = 1,024 states Illegal setting
Software standby SLEEP instruction causes transition to sleep mode 0 SLEEP instruction causes transition to software standby mode 1
Rev.5.00 Sep. 12, 2007 Page 648 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
BRCRBus Release Control Register
Bit 7 A23E Modes Initial value 1, 2 Read/Write Modes Initial value 3, 4 Read/Write 1 1 R/W 6 A22E 1 1 R/W 5 A21E 1 1 R/W
H'EE013
4 A20E 1 0 3 1 1 2 1 1 1 1 1
Bus controller
0 BRLE 0 R/W 0 R/W
Address 23 to 20 enable 0 1 Address output Other input/output
Bus release enable 0 The bus cannot be released to an external device The bus can be released to an external device
1
ISCRIRQ Sense Control Register
Bit 7 Initial value Read/Write 0 R/W 6 0 R/W 5 4
H'EE014
3 2 1
Interrupt Controller
0
IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
IRQ5 to IRQ0 sense control 0 1 Interrupts are requested when IRQ5 toIRQ0 are low Interrupts are requested by falling-edge input at IRQ5 to IRQ0
Rev.5.00 Sep. 12, 2007 Page 649 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
IERIRQ Enable Register
Bit 7 Initial value Read/Write 0 R/W 6 0 R/W 5 IRQ5E 0 R/W 4
H'EE015
3 IRQ3E 0 R/W 2 IRQ2E 0 R/W
Interrupt Controller
1 IRQ1E 0 R/W 0 IRQ0E 0 R/W
IRQ4E 0 R/W
IRQ5 to IRQ0 enable 0 1 IRQ5 to IRQ0 interrupts are disabled IRQ5 to IRQ0 interrupts are enabled
ISRIRQ Status Register
Bit 7 Initial value Read/Write 0 6 0 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)*
H'EE016
3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1
Interrupt Controller
0 IRQ0F 0 R/(W)*
IRQ1F 0 R/(W)*
IRQ5 to IRQ0 flags Bits 5 to 0 IRQ5F to IRQ0F Setting and Clearing Conditions [Clearing conditions] * Read IRQnF when IRQnF = 1, then write 0 in IRQnF. 0 * IRQnSC = 0, IRQn input is high, and interrupt exception handling is being carried out. * IRQnSC = 1 and IRQn interrupt exception handling is being carried out. [Setting conditions] 1 * IRQnSC = 0 and IRQn input is low. * IRQnSC = 1 and IRQn input changes from high to low. Note: n = 5 to 0 Note: * Only 0 can be written, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 650 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
IPRAInterrupt Priority Register A
Bit 7 IPRA7 Initial value Read/Write 0 R/W 6 IPRA6 0 R/W 5 IPRA5 0 R/W
H'EE018
4 IPRA4 0 R/W 3 IPRA3 0 R/W 2 IPRA2 0 R/W
Interrupt Controller
1 IPRA1 0 R/W 0 IPRA0 0 R/W
Priority level A7 to A0 0 1 Priority level 0 (low priority) Priority level 1 (high priority)
* Interrupt sources controlled by each bit Bit IPRA Bit 7 IPRA7 IRQ0 Interrupt source Bit 6 IPRA6 IRQ1 Bit 5 IPRA5 IRQ2, IRQ3 Bit 4 IPRA4 IRQ4, IRQ5 Bit 3 IPRA3 WDT, DRAM Bit 2 IPRA2 16-bit timer Bit 1 IPRA1 16-bit timer Bit 0 IPRA0 16-bit timer
interface, channel 0 channel 1 channel 2 A/D converter
IPRBInterrupt Priority Register B
Bit 7 IPRB7 Initial value Read/Write 0 R/W 6 IPRB6 0 R/W 5 IPRB5 0 R/W 4 0 R/W
H'EE019
3 IPRB3 0 R/W 2 IPRB2 0 R/W 1 IPRB1 0 R/W
Interrupt Controller
0 0 R/W
Priority level B7 to B5, B3 to B1 0 1 Priority level 0 (low priority) Priority level 1 (high priority)
* Interrupt sources controlled by each bit Bit IPRB Bit 7 IPRB7 Bit 6 IPRB6 Bit 5 IPRB5 DMAC Bit 4 Bit 3 IPRB3 SCI Bit 2 IPRB2 SCI Bit 1 IPRB1 SCI Bit 0
8-bit timer 8-bit timer Interrupt channels channels source 0 and 1 2 and 3
channel 0 channel 1 channel 2
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Appendix B Internal I/O Registers
DASTCRD/A Standby Control Register
Bit 7 Initial value Read/Write 1 6 1 5 1 4 1
H'EE01A
3 1 2 1 1 1 0
D/A converter
DASTE 0 R/W
D/A standby enable 0 1 D/A output is disabled in software standby mode D/A output is enabled in software standby mode (Initial value)
DIVCRDivision Control Register
Bit 7 Initial value Read/Write 1 6 1 5 1 4 1
H'EE01B
3 1 2 1 1 DIV1 0 R/W 0
System control
DIV0 0 R/W
Divide 1 and 0 Bit 1 DIV1 0 Bit 0 DIV0 0 1 1 0 1 1/1 1/2 1/4 1/8 (Initial value) Frequency Division Ratio
Rev.5.00 Sep. 12, 2007 Page 652 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
MSTCRHModule Standby Control Register H
Bit 7 PSTOP Initial value Read/Write 0 R/W 6 1 5 1 4 1 3 1
H'EE01C
2 1 0
System control
MSTPH2 MSTPH1 MSTPH0 0 R/W 0 R/W 0 R/W
Module standby H2 to H0 Selection bits for placing modules in standby state. Reserved bits clock stop Enables or disables clock output.
MSTCRLModule Standby Control Register L
Bit 7 MSTPL7 Initial value Read/Write 0 R/W 6 0 R/W 5 4
H'EE01D
3 2 1 0 R/W
System control
0 MSTPL0 0 R/W
MSTPL5 MSTPL4 MSTPL3 MSTPL2 0 R/W 0 R/W 0 R/W 0 R/W
Module standby L7, L5 to L2, L0 Selection bits for placing modules in standby state. Reserved bits
Rev.5.00 Sep. 12, 2007 Page 653 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
CSCRChip Select Control Register
Bit 7 CS7E Initial value Read/Write 0 R/W 6 CS6E 0 R/W 5 CS5E 0 R/W 4
H'EE01F
3 1 2 1 1 1
Bus controller
0 1
CS4E 0 R/W
Chip select 7 to 4 enable Bit n CSnE 0 1 Output of chip select signal CSn is disabled (Initial value) Output of chip select signal CSn is enabled Description
Note: n = 7 to 4
ABWCRBus Width Control Register
Bit 7 ABW7 Modes 1, 3 Modes 2, 4 Initial value Initial value Read/Write 1 0 R/W 6 ABW6 1 0 R/W 5 ABW5 1 0 R/W
H'EE020
4 ABW4 1 0 R/W 3 ABW3 1 0 R/W 2 ABW2 1 0 R/W
Bus controller
1 ABW1 1 0 R/W 0 ABW0 1 0 R/W
Area 7 to 0 bus width control Bits 7 to 0 ABW7 to ABW0 0 1 Areas 7 to 0 are 16-bit access areas Areas 7 to 0 are 8-bit access areas Bus Width of Access Area
Rev.5.00 Sep. 12, 2007 Page 654 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
ASTCRAccess State Control Register
Bit 7 AST7 Initial value Read/Write 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4
H'EE021
3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W
Bus controller
0 AST0 1 R/W
AST4 1 R/W
Area 7 to 0 access state control Bits 7 to 0 AST7 to AST0 0 1 Areas 7 to 0 are two-state access areas Areas 7 to 0 are three-state access areas Number of States in Access Area
Rev.5.00 Sep. 12, 2007 Page 655 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
WCRHWait Control Register H
Bit
7 W71 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3
H'EE022
2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W
Bus controller
W51 1 R/W
Initial value Read/Write
1 R/W
Area 4 wait control 1 and 0 0 No program wait is inserted 0 1 1 program wait state is inserted
1
0 1
2 program wait states are inserted 3 program wait states are inserted
Area 5 wait control 1 and 0 0 No program wait is inserted 0 1 1 program wait state is inserted
1
0 1
2 program wait states are inserted 3 program wait states are inserted
Area 6 wait control 1 and 0 0 No program wait is inserted 0 1 1 program wait state is inserted
1
0 1
2 program wait states are inserted 3 program wait states are inserted
Area 7 wait control 1 and 0 0 No program wait is inserted 0 1 1 program wait state is inserted
1
0 1
2 program wait states are inserted 3 program wait states are inserted
Rev.5.00 Sep. 12, 2007 Page 656 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
WCRLWait Control Register L
Bit 7 W31 Initial value Read/Write 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3
H'EE023
2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W
Bus controller
W11 1 R/W
Area 0 wait control 1 and 0 0 0 1 0 1 1 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted
Area 1 wait control 1 and 0 0 0 1 0 1 1 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted
Area 2 wait control 1 and 0 0 0 1 0 1 1 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted
Area 3 wait control 1 and 0 0 0 1 0 1 1 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted
Rev.5.00 Sep. 12, 2007 Page 657 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
BCRBus Control Register
Bit 7 ICIS1 Initial value Read/Write 1 R/W 6 ICIS0 1 R/W 5 4 3
H'EE024
2 1 1 RDEA 1 R/W 0 WAITE 0 R/W Wait pin enable 0 1
Bus controller
BROME BRSTS1 BRSTS0 0 R/W 0 R/W 0 R/W
WAIT pin wait input is disabled WAIT pin wait input is enabled
Area division unit select 0 Area divisions are as follows: Area 0: 2 Mbytes Area 4: 1.93 Mbytes Area 1: 2 Mbytes Area 5: 4 kbytes Area 2: 8 Mbytes Area 6: 23.75 kbytes Area 3: 2 Mbytes Area 7: 22 bytes 1 Areas 0 to 7 are the same size (2 Mbytes )
Burst cycle select 0 0 1 Max. 4 words in burst access Max. 8 words in burst access
Burst cycle select 1 0 1 Burst access cycle comprises 2 states Burst access cycle comprises 3 states
Burst ROM enable 0 1 Area 0 is a basic bus interface area Area 0 is a burst ROM interface area
Idle cycle insertion 0 0 1 No idle cycle is inserted in case of consecutive external read and write cycles Idle cycle is inserted in case of consecutive external read and write cycles
Idle cycle insertion 1 0 1 No idle cycle is inserted in case of consecutive external read cycles for different areas Idle cycle is inserted in case of consecutive external read cycles for different areas
Rev.5.00 Sep. 12, 2007 Page 658 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
DRCRADRAM Control Register A
Bit 7 6 5 4 1
H'EE026
3 BE 0 R/W 2 1
DRAM interface
0
DRAS2 DRAS1 DRAS0 Initial value Read/Write 0 R/W 0 R/W 0 R/W
RDM SRFMD RFSHE 0 R/W 0 R/W 0 R/W
Refresh pin enable 0 1 RFSH pin refresh signal output is disabled RFSH pin refresh signal output is enabled
Self-refresh mode 0 1 DRAM self-refreshing is disabled in software standby mode DRAM self-refreshing is enabled in software standby modeV
RAS down mode 0 1 DRAM interface: RAS up mode selected DRAM interface: RAS down mode selected
Burst access enable 0 1 DRAM area select DRAS2 DRAS1 DRAS0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Area 5 Normal Normal Normal Normal Normal Area 4 Normal Normal Normal Normal Area 3 Normal Normal Area 2 Normal DRAM space (CS2) Burst disabled (always full access) DRAM space access performed in fast page mode
DRAM space DRAM space (CS3) (CS2) DRAM space(CS2)*
DRAM space DRAM space DRAM space (CS4) (CS3) (CS2)
DRAM space DRAM space DRAM space DRAM space (CS5) (CS4) (CS3) (CS2) DRAM space(CS4)* DRAM space(CS2)*
DRAM space(CS2)*
Note: * A single CSn pin serves as a common RAS output pin for a number of areas. Unused CSn pins can be used as input/output ports.
Rev.5.00 Sep. 12, 2007 Page 659 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
DRCRBDRAM Control Register B
Bit 7 MXC1 Initial value Read/Write 0 R/W 6 MXC0 0 R/W 5 4
H'EE027
3 1 2 TPC 0 R/W 1 RCW 0 R/W 0 CSEL RCYCE 0 R/W 0 R/W
DRAM interface
RLW 0 R/W
Refresh cycle wait control 0 1 Wait state (TRW) insertion is disabled 1 wait state (TRW) is inserted
RAS-CAS wait 0 1 Wait state (TrW) insertion is disabled 1 wait state (TrW) is inserted
TP cycle control 0 1 1-state precharge cycle is inserted 2-state precharge cycle is inserted
Refresh cycle enable 0 1 Refresh cycles are disabled DRAM refresh cycles are enabled
CAS output pin select 0 1 PB4 and PB5 selected as UCAS and LCAS output pins HWR and LWR selected as UCAS and LCAS output pins
Multiplex control 1 and 0 MXC1 0 MXC0 0 Description Column address: 8 bits Compared address: Modes 1, 2 8-bit access space 16-bit access space Modes 3, 4 8-bit access space 16-bit access space Column address: 9 bits Compared address: Modes 1, 2 8-bit access space 16-bit access space Modes 3, 4 8-bit access space 16-bit access space Column address: 10 bits Compared address: Modes 1, 2 8-bit access space 16-bit access space Modes 3, 4 8-bit access space 16-bit access space Illegal setting
A19 to A8 A19 to A9 A23 to A8 A23 to A9
1
A19 to A9 A19 to A10 A23 to A9 A23 to A10
1
0
A19 to A10 A19 to A11 A23 to A10 A23 to A11
1
Rev.5.00 Sep. 12, 2007 Page 660 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
RTMCSRRefresh Timer Control/Status Register
Bit 7 CMF Initial value Read/Write 0 R/(W)* 6 CMIE 0 R/W 5 CKS2 0 R/W 4 CKS1 0 R/W 3
H'EE028
2 1 1 1 0 1
DRAM interface
CKS0 0 R/W
Refresh counter clock select CKS2 0 CKS1 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Compare match interrupt enable 0 1 The CMI interrupt requested by the CMF flag is disabled The CMI interrupt requested by the CMF flag is enabled Description Count operation halted /2 used as counter clock /8 used as counter clock /32 used as counter clock /128 used as counter clock /512 used as counter clock /2048 used as counter clock /4096 used as counter clock
Compare match flag 0 [Clearing conditions] * Cleared by a reset and in standby mode * Cleared by reading CMF when CMF = 1, then writing 0 in CMF 1 [Setting condition] When RTCNT = RTCOR Note: * Only 0 can be written to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 661 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
RTCNTRefresh Timer Counter
Bit 7 6 5 4
H'EE029
3 2 1
DRAM interface
0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Incremented by internal clock selected by bits CKS2 to CKS0 in RTMCSR
RTCORRefresh Time Constant Register
Bit 7 6 5 4
H'EE02A
3 2 1
DRAM interface
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
RTCNT compare match period
Note: Only byte access should be used with this register.
P4PCRPort 4 Input Pull-Up Control Register H'EE03E
Bit 7 6 5 4 3 2 1 0
Port 4
P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR P41PCR P40PCR Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Port 4 input pull-up control 7 to 0 0 1 Input pull-up transistor is off Input pull-up transistor is on
Note: Valid when the corresponding P4DDR bit is cleared to 0 (designating generic input).
Rev.5.00 Sep. 12, 2007 Page 662 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
MAR0A R/E/H/LMemory Address Register 0A R/E/H/L
H'FFF20 H'FFF21 H'FFF22 H'FFF23
21 20 19 18
DMAC0
Bit
31
30
29
28
27
26
25
24
23
22
17
16
Initial value Read/Write
1
1
1
1
1
1
1
1
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W MAR0AE
MAR0AR Bit 15 14 13 12 11 10 9 8 7 6 5
4
3
2
1
0
Initial value Read/Write
Undetermined
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR0AH MAR0AL
Source or destination address
Rev.5.00 Sep. 12, 2007 Page 663 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
ETCR0A H/LExecute Transfer Count Register 0A H/L * Short address mode I/O mode and idle mode
Bit 15 14 13 12 11 10 9 8 7 6
H'FFF24 H'FFF25
DMAC0
5
4
3
2
1
0
Initial value Read/Write
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Transfer counter
Repeat mode
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Initial value Read/Write
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR0AH
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR0AL
Transfer counter
Initial count
* Full address mode Normal mode
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value Read/Write
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Transfer counter
Block transfer mode
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Initial value Read/Write
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR0AH
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR0AL
Block size counter
Initial block size
Rev.5.00 Sep. 12, 2007 Page 664 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
IOAR0AI/O Address Register 0A
Bit 7 6 5 4 3
H'FFF26
2 1
DMAC0
0
Initial value Read/Write
R/W
R/W
R/W
Undetermined R/W R/W
R/W
R/W
R/W
Short address mode : source or destination address Full address mode : not used
Rev.5.00 Sep. 12, 2007 Page 665 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
DTCR0AData Transfer Control Register 0A * Short address mode
Bit 7 DTE Initial value Read/Write 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W 2 DTS2 0 R/W
H'FFF27
DMAC0
1 DTS1 0 R/W
0 DTS0 0 R/W
Data transfer select Bit 2 Bit 1 Bit 0 DTS2 DTS1 DTS0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 Data Transfer Activation Source Compare match/input capture A interrupt from 16-bit timer channel 0 Compare match/input capture A interrupt from 16-bit timer channel 1 Compare match/input capture A interrupt from 16-bit timer channel 2 A/D converter conversion end interrupt SCI0 transmit-data-empty interrupt SCI0 receive-data-full interrupt Transfer in full address mode Transfer in full address mode
Data transfer interrupt enable Interrupt requested by 0 DTE bit is disabled Interrupt requested by 1 DTE bit is enabled Repeat enable RPE DTIE Description 0 0 I/O mode 1 0 Repeat mode 1 1 Idle mode Data transfer increment/decrement 0 1 Incremented: If DTSZ = 0, MAR is incremented by 1 after each transfer If DTSZ = 1, MAR is incremented by 2 after each transfer Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer If DTSZ = 1, MAR is decremented by 2 after each transfer
Data transfer size 0 1 0 1 Byte-size transfer Word-size transfer
Data transfer enable Data transfer is disabled Data transfer is enabled
Rev.5.00 Sep. 12, 2007 Page 666 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
DTCR0AData Transfer Control Register 0A (cont) * Full address mode
Bit 7 DTE Initial value Read/Write 0 R/W 6 DTSZ 0 R/W 5 SAID 0 R/W 4 SAIDE 0 R/W 3 DTIE 0 R/W 2
H'FFF27
DMAC0
1 DTS1A 0 R/W
0 DTS0A 0 R/W
DTS2A 0 R/W
Data transfer select 0A 0 1 Set both bits to 1 Data transfer interrupt enable 0 1 Interrupt requested by DTE bit is disabled Interrupt requested by DTE bit is enabled Normal mode Block transfer mode
Data transfer select 2A and 1A
Source address increment/decrement (bit 5) Source address increment/decrement enable (bit 4) Bit 5 Bit 4 Increment/Decrement Enable SAID SAIDE 0 MARA is held fixed 0 Incremented: If DTSZ = 0, MARA is incremented by 1 after each transfer 1 If DTSZ = 1, MARA is incremented by 2 after each transfer 0 MARA is held fixed 1 Decremented: If DTSZ = 0, MARA is decremented by 1 after each transfer 1 If DTSZ = 1, MARA is decremented by 2 after each transfer Data transfer size 0 1 Byte-size transfer Word-size transfer
Data transfer enable 0 1 Data transfer is disabled Data transfer is enabled
Rev.5.00 Sep. 12, 2007 Page 667 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
MAR0B R/E/H/LMemory Address Register 0B R/E/H/L
H'FFF28 H'FFF29 H'FFF2A H'FFF2B
21 20 19 18
DMAC0
Bit
31
30
29
28
27
26
25
24
23
22
17
16
Initial value Read/Write
1
1
1
1
1
1
1
1
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W MAR0BE
MAR0BR Bit 15 14 13 12 11 10 9 8 7 6 5
4
3
2
1
0
Initial value Read/Write
Undetermined
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR0BH MAR0BL
Source or destination address
Rev.5.00 Sep. 12, 2007 Page 668 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
ETCR0B H/LExecute Transfer Count Register 0B H/L * Short address mode I/O mode and idle mode
Bit 15 14 13 12 11 10 9 8 7 6
H'FFF2C, H'FFF2D
DMAC0
5
4
3
2
1
0
Initial value Read/Write
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Transfer counter
Repeat mode
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Initial value Read/Write :
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR0BH
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR0BL
Transfer counter
Initial count
* Full address mode Normal mode
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value Read/Write
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Not used
Block transfer mode
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value Read/Write
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Block transfer counter
Rev.5.00 Sep. 12, 2007 Page 669 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
IOAR0BI/O Address Register 0B
Bit 7 6 5 4
H'FFF2E
3 2 1
DMAC0
0
Initial value Read/Write
R/W
R/W
R/W
Undetermined R/W R/W
R/W
R/W
R/W
Short address mode : source or destination address Full address mode : not used
Rev.5.00 Sep. 12, 2007 Page 670 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
DTCR0BData Transfer Control Register 0B * Short address mode
Bit 7 DTE Initial value Read/Write 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W
H'FFF2F
DMAC0
2 DTS2 0 R/W
1 DTS1 0 R/W
0 DTS0 0 R/W
Data transfer select Bit 2 Bit 1 Bit 0 DTS2 DTS1 DTS0 0 0 1 0 1 0 1 0 1 0 1 0 1 Data Transfer Activation Source Compare match/input capture A interrupt from 16-bit timer channel 0 Compare match/input capture A interrupt from 16-bit timer channel 1 Compare match/input capture A interrupt from 16-bit timer channel 2 A/D converter conversion end interrupt SCI0 transmit-data-empty interrupt SCI0 receive-data-full interrupt Falling edge of DREQ input Low level of DREQ input
1
Data transfer interrupt enable 0 1 Repeat enable Description RPE DTIE 0 0 I/O mode 1 0 Repeat mode 1 1 Idle mode Data transfer increment/decrement 0 1 Incremented: If DTSZ = 0, MAR is incremented by 1 after each transfer If DTSZ = 1, MAR is incremented by 2 after each transfer Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer If DTSZ = 1, MAR is decremented by 2 after each transfer Interrupt requested by DTE bit is disabled Interrupt requested by DTE bit is enabled
Data transfer size 0 1 0 1 Byte-size transfer Word-size transfer
Data transfer enable Data transfer is disabled Data transfer is enabled
Rev.5.00 Sep. 12, 2007 Page 671 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
DTCR0BData Transfer Control Register 0B (cont) H'FFF2F * Full address mode
Bit 7 DTME Initial value Read/Write 0 R/W 6 0 R/W 5 DAID 0 R/W 4 DAIDE 0 R/W 3 TMS 0 R/W 2 DTS2B 0 R/W 1 DTS1B 0 R/W 0 DTS0B 0 R/W
DMAC0
Data transfer master enable 0 1 Data transfer is disabled Data transfer is enabled
Data transfer select 2B to 0B Bit 2 Bit 1 Bit 0 DTS2B DTS1B DTS0B 0 0 0 1 1 0 1 0 1 0 1 Data Transfer Activation Source Normal Mode Block Transfer Mode Auto-request (burst mode) Compare match/input capture A interrupt from 16-bit timer channel 0 Not available Auto-request (cycle-steal mode) Not available Not available Not available Falling edge of DREQ input Low level input at DREQ input Compare match/input capture A interrupt from 16-bit timer channel 1 Compare match/input capture A interrupt from 16-bit timer channel 2 A/D converter conversion end interrupt Not available Not available Falling edge of DREQ input Not available
0 1 1
Transfer mode select 0 1 Destination address increment/decrement (bit 5) Destination address increment/decrement enable (bit 4) Bit 4 Bit 5 Increment/Decrement Enable DAID DAIDE 0 MARB is held fixed 0 Incremented: If DTSZ = 0, MARB is incremented by 1 after each transfer 1 If DTSZ = 1, MARB is incremented by 2 after each transfer 0 MARB is held fixed 1 Decremented: If DTSZ = 0, MARB is decremented by 1 after each transfer 1 If DTSZ = 1, MARB is decremented by 2 after each transfer Destination is the block area in block transfer mode Source is the block area in block transfer mode
Rev.5.00 Sep. 12, 2007 Page 672 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
MAR1A R/E/H/LMemory Address Register 1A R/E/H/L
H'FFF30 H'FFF31 H'FFF32 H'FFF33
21 20 19 18
DMAC1
Bit
31
30
29
28
27
26
25
24
23
22
17
16
Initial value Read/Write
1
1
1
1
1
1
1
1
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W MAR1AE
MAR1AR Bit 15 14 13 12 11 10 9 8 7 6 5
4
3
2
1
0
Initial value Read/Write
Undetermined
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR1AH MAR1AL
Note: Bit functions are the same as for DMAC0.
ETCR1A H/LExecute Transfer Count Register 1A H/L
Bit 15 14 13 12 11 10 9 8 7 6
H'FFF34 H'FFF35
5 4 3 2
DMAC1
1 0
Initial value Read/Write
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Initial value Read/Write
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR1AH
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR1AL
Note: Bit functions are the same as for DMAC0.
Rev.5.00 Sep. 12, 2007 Page 673 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
IOAR1AI/O Address Register 1A
7 6 5 4
H'FFF36
3 2 1
DMAC1
0
Bit
Initial value Read/Write
R/W
R/W
R/W
Undetermined R/W R/W
R/W
R/W
R/W
Note: Bit functions are the same as for DMAC0.
DTCR1AData Transfer Control Register 1A * Short address mode
Bit 7 DTE Initial value Read/Write 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W
H'FFF37
DMAC1
3 DTIE 0 R/W
2 DTS2 0 R/W
1 DTS1 0 R/W
0 DTS0 0 R/W
* Full address mode
Bit 7 DTE Initial value Read/Write 0 R/W 6 DTSZ 0 R/W 5 SAID 0 R/W 4 SAIDE 0 R/W 3 DTIE 0 R/W 2 DTS2A 0 R/W 1 DTS1A 0 R/W 0 DTS0A 0 R/W
Note: Bit functions are the same as for DMAC0.
Rev.5.00 Sep. 12, 2007 Page 674 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
MAR1B R/E/H/LMemory Address Register 1B R/E/H/L
H'FFF38 H'FFF39 H'FFF3A H'FFF3B
21 20 19 18
DMAC1
Bit
31
30
29
28
27
26
25
24
23
22
17
16
Initial value Read/Write
1
1
1
1
1
1
1
1
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W MAR1BE
MAR1BR Bit 15 14 13 12 11 10 9 8 7 6 5
4
3
2
1
0
Initial value Read/Write
Undetermined
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR1BH MAR1BL
Note: Bit functions are the same as for DMAC0.
ETCR1B H/LExecute Transfer Count Register 1B H/L
Bit 15 14 13 12 11 10 9 8 7 6
H'FFF3C H'FFF3D
5 4 3 2
DMAC1
1 0
Initial value Read/Write
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Initial value Read/Write
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR1BH
Undetermined R/W R/W R/W R/W R/W R/W R/W R/W ETCR1BL
Note: Bit functions are the same as for DMAC0.
Rev.5.00 Sep. 12, 2007 Page 675 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
IOAR1BI/O Address Register 1B
Bit 7 6 5 4
H'FFF3E
3 2 1
DMAC1
0
Initial value Read/Write
R/W
R/W
R/W
Undetermined R/W R/W
R/W
R/W
R/W
Note: Bit functions are the same as for DMAC0.
DTCR1BData Transfer Control Register 1B * Short address mode
Bit 7 DTE Initial value Read/Write 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W
H'FFF3F
DMAC1
3 DTIE 0 R/W
2 DTS2 0 R/W
1 DTS1 0 R/W
0 DTS0 0 R/W
* Full address mode
Bit 7 DTME Initial value Read/Write 0 R/W 6 0 R/W 5 DAID 0 R/W 4 DAIDE 0 R/W 3 TMS 0 R/W 2 DTS2B 0 R/W 1 DTS1B 0 R/W 0 DTS0B 0 R/W
Note: Bit functions are the same as for DMAC0.
Rev.5.00 Sep. 12, 2007 Page 676 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
TSTRTimer Start Register
Bit 7 Initial value Read/Write 1 6 1 5 1 Reserved bits 4 1
H'FFF60
3 1 2
16-Bit Timer (Common)
1 STR1 0 R/W 0 STR0 0 R/W
STR2 0 R/W
Counter start 0 0 1 Counter start 1 0 1 Counter start 2 0 1 16TCNT2 count halted (Initial value) 16TCNT2 countIng 16TCNT1 count halted 16TCNT1 counting (Initial value) 16TCNT0 count halted 16TCNT0 counting (Initial value)
Rev.5.00 Sep. 12, 2007 Page 677 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
TSNCTimer Syncro Register
Bit 7 Initial value Read/Write 1 6 1 5 1 Reserved bits 4 1
H'FFF61
3 1 2 SYNC2 0 R/W
16-Bit Timer (Common)
1 SYNC1 0 R/W 0 SYNC0 0 R/W
Timer sync 0 0 1 Channel 0 timer counter (16TCNT0) operates independently (16TCNT0 presetting/clearing unrelated to other channels) (Initial value) Channel 0 operates synchronously 16TCNT0 synchronous presetting/synchronous clearing possible
Timer sync 1 0 1 Channel 1 timer counter (16TCNT1) operates independently (16TCNT1 presetting/clearing unrelated to other channels) (Initial value) Channel 1 operates synchronously 16TCNT1 synchronous presetting/synchronous clearing possible
Timer sync 2 0 1 Channel 2 timer counter (16TCNT2) operates independently (16TCNT2 presetting/clearing unrelated to other channels) (Initial value) Channel 2 operates synchronously 16TCNT2 synchronous presetting/synchronous clearing possible
Rev.5.00 Sep. 12, 2007 Page 678 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
TMDRTimer Mode Register
Bit 7 Initial value Read/Write 1 6 MDF 0 R/W 5 FDIR 0 R/W 4 1
H'FFF62
3 1 2
16-Bit Timer (Common)
1 PWM1 0 R/W 0 PWM0 0 R/W
PWM2 0 R/W
PWM mode 0 0 1 PWM mode 1 0 1 PWM mode 2 0 1 Flag direction 0 1 TISRC OVF flag set to 1 when 16TCNT2 overflows or underflows TISRC OVF flag set to 1 when 16TCNT2 overflows (Initial value) Normal operation selected for channel 2 PWM mode selected for channel 2 (Initial value) Normal operation selected for channel 1 PWM mode selected for channel 1 (Initial value) Normal operation selected for channel 0 PWM mode selected for channel 0 (Initial value)
Phase counting mode 0 1 Normal operation selected for channel 2 (Initial value)
Phase counting mode selected for channel 2
Rev.5.00 Sep. 12, 2007 Page 679 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
TOLRTimer Output Level Setting Register
Bit 7 Initial value Read/Write 1 6 1 5 TOB2 0 W 4 TOA2 0 W
H'FFF63
3 TOB1 0 W 2
16-Bit Timer (Common)
1 TOB0 0 W 0 TOA0 0 W
TOA1 0 W
Output level setting A0 0 1 Output level setting B0 0 1 TIOCB0 set to 0 output TIOCB0 set to 1 output (Initial value) TIOCA0 set to 0 output TIOCA0 set to 1 output (Initial value)
Output level setting A1 0 1 TIOCA1 set to 0 output TIOCA1 set to 1 output (Initial value)
Output level setting B1 0 1 TIOCB1 set to 0 output TIOCB1 set to 1 output (Initial value)
Output level setting A2 0 1 TIOCA2 set to 0 output TIOCA2 set to 1 output (Initial value)
Output level setting B2 0 1 TIOCB2 set to 0 output TIOCB2 set to 1 output (Initial value)
Rev.5.00 Sep. 12, 2007 Page 680 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
TISRATimer Interrupt Status Register A
Bit 7 Initial value Read/Write 1 6 5 4 3 1
H'FFF64
2 1 0
16-Bit Timer (Common)
IMIEA2 IMIEA1 IMIEA0 0 R/W 0 R/W 0 R/W
IMFA2 IMFA1 IMFA0 0 0 0
R/(W)* R/(W)* R/(W)*
Input capture/compare match flag A0
0
[Clearing conditions] (Initial value) * Read IMFA0 when IMFA0 =1, then write 0 in IMFA0 * DMAC activated by IMIA0 interrupt [Setting conditions] * 16TCNT0 = GRA0 when GRA0 functions as an output compare register. * 16TCNT0 value is transferred to GRA0 by an input capture signal when GRA0 functions as an input capture register.
1
Input capture/compare match flag A1
0
[Clearing conditions] (Initial value) * Read IMFA1 when IMFA1 =1, then write 0 in IMFA1 * DMAC activated by IMIA1 interrupt [Setting conditions] * 16TCNT1 = GRA1 when GRA1 functions as an output compare register * 16TCNT1 value is transferred to GRA1 by an input capture signal when GRA1 functions as an input capture register
1
Input capture/compare match flag A2
0
[Clearing conditions] (Initial value) * Read IMFA2 when IMFA2 =1, then write 0 in IMFA2 * DMAC activated by IMIA2 interrupt [Setting conditions] * 16TCNT2 = GRA2 when GRA2 functions as an output compare register * 16TCNT2 value is transferred to GRA2 by an input capture signal when GRA2 functions as an input capture register
1
Input capture/compare match interrupt enable A0
0 1
IMIA0 interrupt requested by IMFA0 flag is disabled IMIA0 interrupt requested by IMFA0 flag is enabled
(Initial value)
Input capture/compare match interrupt enable A1
0 1
IMIA1 interrupt requested by IMFA1 flag is disabled IMIA1 interrupt requested by IMFA1 flag is enabled
(Initial value)
Input capture/compare match interrupt enable A2
0 1
IMIA2 interrupt requested by IMFA2 flag is disabled IMIA2 interrupt requested by IMFA2 flag is enabled
(Initial value)
Note: * Only 0 can be written, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 681 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
TISRBTimer Interrupt Status Register B
Bit 7 Initial value Read/Write 1 6 5 4 3 1
H'FFF65
2 1 0
16-Bit Timer (Common)
IMIEB2 IMIEB1 IMIEB0 0 R/W 0 R/W 0 R/W
IMFB2 IMFB1 IMFB0 0 0 0
R/(W)* R/(W)* R/(W)*
Input capture/compare match flag B0
0
[Clearing condition] (Initial value) Read IMFB0 when IMFB0 =1, then write 0 in IMFB0 [Setting conditions] * 16TCNT0 = GRB0 when GRB0 functions as an output compare register. * 16TCNT0 value is transferred to GRB0 by an input capture signal when GRB0 functions as an input capture register.
1
Input capture/compare match flag B1
0
[Clearing condition] (Initial value) Read IMFB1 when IMFB1 =1, then write 0 in IMFB1 [Setting conditions] * 16TCNT1 = GRB1 when GRB1 functions as an output compare register * 16TCNT1 value is transferred to GRB1 by an input capture signal when GRB1 functions as an input capture register
1
Input capture/compare match flag B2
0
[Clearing condition] (Initial value) Read IMFB2 when IMFB2 =1, then write 0 in IMFB2 [Setting conditions] * 16TCNT2 = GRB2 when GRB2 functions as an output compare register * 16TCNT2 value is transferred to GRB2 by an input capture signal when GRB2 functions as an input capture register
1
Input capture/compare match interrupt enable B0
0 1
IMIB0 interrupt requested by IMFB0 flag is disabled IMIB0 interrupt requested by IMFB0 flag is enabled
(Initial value)
Input capture/compare match interrupt enable B1
0 1
IMIB1 interrupt requested by IMFB1 flag is disabled IMIB1 interrupt requested by IMFB1 flag is enabled
(Initial value)
Input capture/compare match interrupt enable B2
0 1
IMIB2 interrupt requested by IMFB2 flag is disabled IMIB2 interrupt requested by IMFB2 flag is enabled
(Initial value)
Note: * Only 0 can be written, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 682 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
TISRCTimer Interrupt Status Register C
Bit 7 Initial value Read/Write 1 6 5 4 3 1
H'FFF66
2 OVF2 0 1 OVF1 0 0 OVF0 0
16-Bit Timer (Common)
OVIE2 OVIE1 OVIE0 0 R/W 0 R/W 0 R/W
R/(W)* R/(W)* R/(W)*
Overflow flag 0
0
[Clearing condition] (Initial value) Read OVF0 when OVF0 =1, then write 0 in OVF0 [Setting condition] 16TCNT0 overflowed from H'FFFF to H'0000
1
Overflow flag 1
0
[Clearing condition] (Initial value) Read OVF1 when OVF1 =1, then write 0 in OVF1 [Setting condition] 16TCNT1 overflowed from H'FFFF to H'0000
1
Overflow flag 2
0
[Clearing condition] (Initial value) Read OVF2 when OVF2 =1, then write 0 in OVF2 [Setting condition] 16TCNT2 overflowed from H'FFFF to H'0000 or underflowed from H'0000 to H'FFFF
1
Overflow interrupt enable 0
0 1
OVI0 interrupt requested by OVF0 flag is disabled OVI0 interrupt requested by OVF0 flag is enabled
(Initial value)
Overflow interrupt enable 1
0 1
OVI1 interrupt requested by OVF1 flag is disabled OVI1 interrupt requested by OVF1 flag is enabled
(Initial value)
Overflow interrupt enable 2
0 1
OVI2 interrupt requested by OVF2 flag is disabled OVI2 interrupt requested by OVF2 flag is enabled
(Initial value)
Note: * Only 0 can be written, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 683 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
16TCR0Timer Control Register 0
Bit 7 Initial value Read/Write 1 6 5 4
H'FFF68
3 2 1
16-Bit Timer Channel 0
0
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Timer prescaler 2 to 0 Bit 2 TPSC2 Bit 1 TPSC1 0 0 1 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: Counts on (Initial value) Internal clock: Counts on /2 Internal clock: Counts on /4 Internal clock: Counts on /8 External clock A: Counts on TCLKA pin input External clock B: Counts on TCLKB pin input External clock C: Counts on TCLKC pin input External clock D: Counts on TCLKD pin input
Clock edge 1 and 0 Bit 4 CKEG1 0 0 1 Counter clear 1 and 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 0 1 Description 16TCNT clearing disabled (Initial value) 16TCNT cleared by GRA compare match/input capture 16TCNT cleared by GRB compare match/input capture Synchronous clear. 16TCNT cleared in synchronization with counter clearing of other timers operating synchronously. Bit 3 CKEG0 0 1 Description Counts on rising edge Counts on falling edge Counts on both rising and falling edges (Initial value)
1
Rev.5.00 Sep. 12, 2007 Page 684 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
TIOR0Timer I/O Control Register 0
Bit 7 Initial value Read/Write 1 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W
H'FFF69
3 1 2 IOA2 0 R/W 1 IOA1 0 R/W
16-Bit Timer Channel 0
0 IOA0 0 R/W
I/O control A2 to A0 Bit 2 IOA2 Bit 1 IOA1 0 0 1 Bit 0 IOA0 0 1 0 1 0 1 0 1 Description GRA is output Pin output at compare match disabled (Initial value) compare register 0 output at GRA compare match 1 output at GRA compare match Toggle output at GRA compare match (1 output on channel 2 only) GRA is input capture register Input capture in GRA at rising edge Input capture in GRA at falling edge Input capture at both rising and falling edges
0 1 1 I/O control B2 to B0 Bit 6 IOB2 Bit 5 IOB1 0 0 1 Bit 4 IOB0 0 1 0 1 0 1 0 1
Description GRB is output Pin output at compare match disabled (Initial value) compare register 0 output at GRB compare match 1 output at GRB compare match Toggle output at GRB compare match (1 output on channel 2 only) GRB is input capture register Input capture in GRB at rising edge Input capture in GRB at falling edge Input capture at both rising and falling edges
0 1 1
16TCNT0H/LTimer Counter 0H/L
H'FFF6A H'FFF6B
10 9 8 7 6 5
16-Bit Timer Channel 0
Bit
15
14
13
12
11
4
3
2
1
0
Initial value Read/Write
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter
Rev.5.00 Sep. 12, 2007 Page 685 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
GRA0H/LGeneral Register A0 H/L
H'FFF6C H'FFF6D
10 9 8 7 6 5
16-Bit Timer Channel 0
Bit
15
14
13
12
11
4
3
2
1
0
Initial value Read/Write
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Output compare/input capture dual-function register
GRB0H/LGeneral Register B0 H/L
H'FFF6E H'FFF6F
10 9 8 7 6 5
16-Bit Timer Channel 0
Bit
15
14
13
12
11
4
3
2
1
0
Initial value Read/Write
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Output compare/input capture dual-function register
16TCR1Timer Control Register 1
Bit 7 Initial value Read/Write 1 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4
H'FFF70
3 CKEG0 0 R/W 2
16-Bit Timer Channel 1
1 TPSC1 0 R/W 0 TPSC0 0 R/W
CKEG1 0 R/W
TPSC2 0 R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
TIOR1Timer I/O Control Register 1
Bit 7 Initial value Read/Write 1 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W
H'FFF71
3 1 2
16-Bit Timer Channel 1
1 IOA1 0 R/W 0 IOA0 0 R/W
IOA2 0 R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
Rev.5.00 Sep. 12, 2007 Page 686 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
16TCNT1H/LTimer Counter 1H/L
H'FFF72 H'FFF73
10 9 8 7 6 5 4
16-Bit Timer Channel 1
Bit
15
14
13
12
11
3
2
1
0
Initial value Read/Write
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
GRA1H/LGeneral Register A1 H/L
H'FFF74 H'FFF75
10 9 8 7 6 5 4
16-Bit Timer Channel 1
Bit
15
14
13
12
11
3
2
1
0
Initial value Read/Write
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
GRB1H/LGeneral Register B1 H/L
H'FFF76 H'FFF77
10 9 8 7 6 5 4
16-Bit Timer Channel 1
Bit
15
14
13
12
11
3
2
1
0
Initial value Read/Write
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
16TCR2Timer Control Register 2
Bit 7 Initial value Read/Write 1 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4
H'FFF78
3 CKEG0 0 R/W 2
16-Bit Timer Channel 2
1 TPSC1 0 R/W 0 TPSC0 0 R/W
CKEG1 0 R/W
TPSC2 0 R/W
Notes: 1. Bit functions are the same as for 16-bit timer channel 0. 2. The settings of bits CKEG1 and CKEG0 and bits TPSC2 to TPSC0 in 16TCR2 are invalid when phase counting mode is selected for channel 2.
Rev.5.00 Sep. 12, 2007 Page 687 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
TIOR2Timer I/O Control Register 2
Bit 7 Initial value Read/Write 1 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W
H'FFF79
3 1 2 IOA2 0 R/W
16-Bit Timer Channel 2
1 IOA1 0 R/W 0 IOA0 0 R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
16TCNT2H/LTimer Counter 2H/L
H'FFF7A H'FFF7B
10 9 8 7 6 5
16-Bit Timer Channel 2
Bit
15
14
13
12
11
4
3
2
1
0
Initial value Read/Write
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Phase counting mode: Up/down-counter Other modes: Up-counter
GRA2H/LGeneral Register A2 H/L
H'FFF7C H'FFF7D
10 9 8 7 6 5 4
16-Bit Timer Channel 2
Bit
15
14
13
12
11
3
2
1
0
Initial value Read/Write
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
GRB2H/LGeneral Register B2 H/L
H'FFF7E H'FFF7F
10 9 8 7 6 5 4
16-Bit Timer Channel 2
Bit
15
14
13
12
11
3
2
1
0
Initial value Read/Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
Rev.5.00 Sep. 12, 2007 Page 688 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
8TCR0Timer Control Register 0 8TCR1Timer Control Register 1
Bit 7 CMIEB Initial value Read/Write 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W
H'FFF80 H'FFF81
3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W
8-bit timer channel 0 8-bit timer channel 1
0 CKS0 0 R/W
Clock select 2 to 0 0 0 0 1 1 1 0 Clock input is disabled Internal clock, counted on rising edge of /8 Internal clock, counted on rising edge of /64 Internal clock, counted on rising edge of /8192 Channel 0: Count on 8TCNT1 overflow signal* Channel 1: Count on 8TCNT0 compare match A* External clock, counted on falling edge External clock, counted on rising edge External clock, counted on both rising and falling edges
0 1
0
1 0 1 1
Note: * If the clock input of channel 0 is the 8TCNT1 overflow signal and that of channel 1 is the 8TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. Counter clear 1 and 0 0 0 1 1 0 1 Clearing is disabled Cleared by compare match A Cleared by compare match B/input capture B Cleared by input capture B
Timer overflow interrupt enable 0 1 OVI interrupt requested by OVF is disabled OVI interrupt requested by OVF is enabled
Compare match interrupt enable A 0 1 CMIA interrupt requested by CMFA is disabled CMIA interrupt requested by CMFA is enabled
Compare match interrupt enable B 0 1 CMIB interrupt requested by CMFB is disabled CMIB interrupt requested by CMFB is enabled
Rev.5.00 Sep. 12, 2007 Page 689 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
8TCSR0Timer Control/Status Register 0
Bit 7 CMFB Initial value Read/Write 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ADTE 0 R/W 3 OIS3 0 R/W
H'FFF82
2 OIS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W
8-bit timer channel 0
Output select A1 and A0 Bit 1 Bit 0 Description
OS1 OS0
0
0 1 0
No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare match A
1 1
Output/input capture edge select B3 and B2 ICE in Bit 3 8TCSR1 OIS3 0 0 1 Bit 2
OIS2
Description No change at compare match B 0 output at compare match B 1 output at compare match B Output toggles at compare match B TCORB input capture on rising edge TCORB input capture on falling edge TCORB input capture on both rising and falling edges
0 1 0 1 0
0 1 1
1 0 1
A/D trigger enable
TRGE*
Bit 4
ADTE
Description A/D converter start requests by compare match A or an external trigger are disabled A/D converter start requests by compare match A or an external trigger are enabled A/D converter start requests by an external trigger are enabled, and A/D converter start requests by compare match A are disabled A/D converter start requests by compare match A are enabled, and A/D converter start requests by an external trigger are disabled
0 0 1 0 1 1
Note: * TRGE is bit 7 of the A/D control register (ADCR). Timer overflow flag 0 1 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF. [Setting condition] 8TCNT overflows from H'FF to H'00.
Compare match flag A 0 1 [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA. [Setting condition] 8TCNT = TCORA
Compare match/input capture flag B 0 [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB. [Setting conditions] * 8TCNT = TCORB * The 8TCNT value is transferred to TCORB by an input capture signal when TCORB functions as an input capture register.
1
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Rev.5.00 Sep. 12, 2007 Page 690 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
8TCSR1Timer Control/Status Register 1
Bit 7 CMFB Initial value Read/Write 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ICE 0 R/W
H'FFF83
3 OIS3 0 R/W 2 OIS2 0 R/W 1 OS1 0 R/W 0
8-bit timer channel 1
OS0 0 R/W
Output select A1 and A0 Bit 1 Bit 0 Description
OS1 OS0
0
0 1 0
No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare match A
1 1
Output/input capture edge select B3 and B2
ICE in Bit 3 8TCSR1 OIS3
Bit 2
OIS2
Description No change at compare match B 0 output at compare match B 1 output at compare match B Output toggles at compare match B TCORB input capture on rising edge TCORB input capture on falling edge TCORB input capture on both rising and falling edges
0 0 1
0 1 0 1 0
0 1 1 Input capture enable 0 1 1 0 1
TCORB is a compare match register TCORB is an input capture register
Timer overflow flag 0 1 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF. [Setting condition] 8TCNT overflows from H'FF to H'00.
Compare match flag A 0 1 [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA. [Setting condition] 8TCNT = TCORA
Compare match/input capture flag B 0 [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB. [Setting conditions] * 8TCNT = TCORB * The 8TCNT value is transferred to TCORB by an input capture signal when TCORB functions as an input capture register.
1
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Rev.5.00 Sep. 12, 2007 Page 691 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
TCORA0Timer Constant Register A0 TCORA1Timer Constant Register A1
TCORA0 Bit 15 14 13 12 11 10 9
H'FFF84 H'FFF85
8-bit timer channel 0 8-bit timer channel 1
TCORA1
8
7
6
5
4
3
2
1
0
Initial value Read/Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORB0Timer Constant Register B0 TCORB1Timer Constant Register B1
TCORB0 Bit 15 14 13 12 11 10 9
H'FFF86 H'FFF87
8-bit timer channel 0 8-bit timer channel 1
TCORB1
8
7
6
5
4
3
2
1
0
Initial value Read/Write
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
8TCNT0Timer Counter 0 8TCNT1Timer Counter 1
8TCNT0 Bit 15 14 13 12 11 10 9
H'FFF88 H'FFF89
8-bit timer channel 0 8-bit timer channel 1
8TCNT1
8
7
6
5
4
3
2
1
0
Initial value Read/Write
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev.5.00 Sep. 12, 2007 Page 692 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
TCSRTimer Control/Status Register
Bit 7 OVF Initial value Read/Write 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 1
H'FFF8C
3 1 2 CKS2 0 R/W 1 CKS1 0 R/W
WDT
0 CKS0 0 R/W
Clock select 2 to 0 CKS2 CKS1 CKS0 0 0 0 1 1 0 1 0 0 1 1 Timer enable Timer disabled 0 * TCNT is initialized to H'00 and halted Timer enabled 1 * TCNT is counting 1 0 1 Description /2 /32 /64 /128 /256 /512 /2048 /4096
Timer mode select 0 Interval timer: requests interval timer interrupts Watchdog timer: 1 Overflow flag 0 1 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF [Setting condition] TCNT changes from H'FF to H'00 generates a reset signal
Note: * Only 0 can be written, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 693 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
TCNTTimer Counter
Bit 7 6 5
H'FFF8D (read), H'FFF8C (write)
4 3 2 1
WDT
0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Count value
RSTCSRReset Control/Status Register
Bit 7 WRST Initial value Read/Write 0 R/(W)* 6 RSTOE 0 R/W 5 1 4 1
H'FFF8F (read), H'FFF8E (write)
3 1 2 1 1 1
WDT
0 1
Reset output enable 0 1 External output of reset signal is disabled External output of reset signal is enabled
Watchdog timer reset 0 [Clearing conditions] * Reset signal at RES pin * Read WRST when WRST = 1, then write 0 in WRST [Setting condition] 1 TCNT overflow generates a reset signal
Note: * Only 0 can be written in bit 7, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 694 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
8TCR2Timer Control Register 2 8TCR3Timer Control Register 3
Bit 7 CMIEB Initial value Read/Write 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3
H'FFF90 H'FFF91
2 CKS2 0 R/W 1 CKS1 0 R/W 0
8-bit timer channel 2 8-bit timer channel 3
CCLR0 0 R/W
CKS0 0 R/W
Clock select 2 to 0 CKS2 CKS1 CKS0 0 0 1 0 0 1 1 Description Clock input is disabled Internal clock, counted on rising edge of /8 Internal clock, counted on rising edge of /64 Internal clock, counted on rising edge of /8192 Channel 2: Count on 8TCNT3 overflow signal* Channel 3: Count on 8TCNT2 compare match A* External clock, counted on falling edge External clock, counted on rising edge External clock, counted on both rising and falling edges
0 1 1
0
1 0 1
Note: * If the clock input of channel 2 is the 8TCNT3 overflow signal and that of channel 3 is the 8TCNT2 compare match signal, no incrementing clock is generated. Do not use this setting. Counter clear 1 and 0 0 0 1 0 1 Clearing is disabled Cleared by compare match A Cleared by compare match B/input capture B Cleared by input capture B
1
Timer overflow interrupt enable 0 1 OVI interrupt requested by OVF is disabled OVI interrupt requested by OVF is enabled
Compare match interrupt enable A 0 1 CMIA interrupt requested by CMFA is disabled CMIA interrupt requested by CMFA is enabled
Compare match interrupt enable B 0 1 CMIB interrupt requested by CMFB is disabled CMIB interrupt requested by CMFB is enabled
Rev.5.00 Sep. 12, 2007 Page 695 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
8TCSR2Timer Control/Status Register 2 8TCSR3Timer Control/Status Register 3
8TCSR2 Bit 7 CMFB Initial value Read/Write 8TCSR3 Bit 0 R/(W)* 7 CMFB Initial value Read/Write 0 R/(W)* 6 CMFA 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 5 OVF 0 R/(W)* 4 1 4 ICE 0 R/W
H'FFF92 H'FFF93
3 OIS3 0 R/W 3 OIS3 0 R/W 2 OIS2 0 R/W 2 OIS2 0 R/W 1 OS1 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W 0 OS0 0 R/W
8-bit timer channel 2 8-bit timer channel 3
Output select A1 and A0 Bit 1 Bit 0 Description
OS1 OS0
0
0 1 0
No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare match A
1 1
Output/input capture edge select B3 and B2
ICE in Bit 3 8TCSR3 OIS3
Bit 2
OIS2
Description No change at compare match B 0 output at compare match B 1 output at compare match B Output toggles at compare match B TCORB input capture on rising edge TCORB input capture on falling edge TCORB input capture on both rising and falling edges
0 0 1
0 1 0 1 0
0 1 1 Input capture enable 0 1 1 0 1
TCORB is a compare match register TCORB is an input capture register
Timer overflow flag 0 1 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF. [Setting condition] 8TCNT overflows from H'FF to H'00.
Compare match/input capture flag A 0 1 [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA. [Setting condition] 8TCNT = TCORA
Compare match/input capture flag B 0 [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB. [Setting conditions] * 8TCNT = TCORB * The 8TCNT value is transferred to TCORB by an input capture signal when TCORB functions as an input capture register.
1
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Rev.5.00 Sep. 12, 2007 Page 696 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
TCORA2Timer Constant Register A2 TCORA3Timer Constant Register A3
TCORA2 Bit 15 14 13 12 11 10 9
H'FFF94 H'FFF95
8-bit timer channel 2 8-bit timer channel 3
TCORA3
8
7
6
5
4
3
2
1
0
Initial value Read/Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORB2Timer Constant Register B2 TCORB3Timer Constant Register B3
TCORB2 Bit 15 14 13 12 11 10 9
H'FFF96 H'FFF97
8-bit timer channel 2 8-bit timer channel 3
TCORB3
8
7
6
5
4
3
2
1
0
Initial value Read/Write
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
8TCNT2Timer Counter 2 8TCNT3Timer Counter 3
8TCNT2 Bit 15 14 13 12 11 10 9
H'FFF98 H'FFF99
8-bit timer channel 2 8-bit timer channel 3
8TCNT3
8
7
6
5
4
3
2
1
0
Initial value Read/Write
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DADR0D/A Data Register 0
Bit 7 6 5 4
H'FFF9C
3 2 1 0
D/A
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
D/A conversion data
Rev.5.00 Sep. 12, 2007 Page 697 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
DADR1D/A Data Register 1
Bit 7 6 5 4
H'FFF9D
3 2 1 0
D/A
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
D/A conversion data
Rev.5.00 Sep. 12, 2007 Page 698 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
DACRD/A Control Register
Bit 7 DAOE1 Initial value Read/Write 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 1
H'FFF9E
3 1 2 1 1 1 0 1
D/A
D/A enable Bit 7 DAOE1 0 Bit 6 DAOE0 0 Bit 5 Description DAE D/A conversion is disabled in channels 0 and 1 D/A conversion is enabled in channel 0 0 1 0 D/A conversion is disabled in channel 1 0 1 1 D/A conversion is enabled in channels 0 and 1 D/A conversion is disabled in channel 0 D/A conversion is enabled in channel 1 1 0 1 D/A conversion is enabled in channels 0 and 1 D/A conversion is enabled in channels 0 and 1
1
0
0
1
1
D/A output enable 0 0 1 DA0 analog output is disabled Channel-0 D/A conversion and DA0 analog output are enabled
D/A output enable 1 0 1 DA1 analog output is disabled Channel-1 D/A conversion and DA1 analog output are enabled
Rev.5.00 Sep. 12, 2007 Page 699 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
TPMRTPC Output Mode Register
Bit 7 Initial value Read/Write 1 6 1 5 1 4 1
H'FFFA0
3 G3NOV 0 R/W 2 G2NOV 0 R/W 1 G1NOV 0 R/W
TPC
0 G0NOV 0 R/W
Group 0 non-overlap 0 Normal TPC output in group 0. Output values change at compare match A in the selected 16-bit timer channel Non-overlapping TPC output in group 0, controlled by compare match A and B in the selected 16-bit timer channel
1
Group 1 non-overlap 0 1 Normal TPC output in group 1. Output values change at compare match A in the selected 16-bit timer channel Non-overlapping TPC output in group 1, controlled by compare match A and B in the selected 16-bit timer channel
Group 2 non-overlap 0 1 Normal TPC output in group 2. Output values change at compare match A in the selected 16-bit timer channel Non-overlapping TPC output in group 2, controlled by compare match A and B in the selected 16-bit timer channel
Group 3 non-overlap 0 1 Normal TPC output in group 3. Output values change at compare match A in the selected 16-bit timer channel Non-overlapping TPC output in group 3, controlled by compare match A and B in the selected 16-bit timer channel
Rev.5.00 Sep. 12, 2007 Page 700 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
TPCRTPC Output Control Register
Bit 7 G3CMS1 Initial value Read/Write 1 R/W 6 G3CMS0 1 R/W 5 G2CMS1 1 R/W 4 G2CMS0 1 R/W 3
H'FFFA1
2 G1CMS0 1 R/W 1 G0CMS1 1 R/W 0 G0CMS0 1 R/W G1CMS1 1 R/W
TPC
Group 0 compare match select 1 and 0 Bit 1 Bit 0 G0CMS1 G0CMS0 0 0 1 1 0 1 16-Bit Timer Channel Selected as Output Trigger TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 0 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 1 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 2
Group 1 compare match select 1 and 0 Bit 3 Bit 2 G1CMS1 G1CMS0 0 0 1 1 0 1 16-Bit Timer Channel Selected as Output Trigger TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 0 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 1 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 2
Group 2 compare match select 1 and 0 Bit 5 Bit 4 0 1 0 1 G2CMS1 G2CMS0 0 1 16-Bit Timer Channel Selected as Output Trigger TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 0 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 1 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 2
Group 3 compare match select 1 and 0 Bit 7 Bit 6 0 1 0 1 G3CMS1 G3CMS0 0 1 16-Bit Timer Channel Selected as Output Trigger TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 0 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 1 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 2
Rev.5.00 Sep. 12, 2007 Page 701 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
NDERBNext Data Enable Register B
Bit 7 NDER15 Initial value Read/Write 0 R/W 6 NDER14 0 R/W 5 NDER13 0 R/W 4
H'FFFA2
3 NDER11 0 R/W 2 NDER10 0 R/W 1 NDER9 0 R/W
TPC
0 NDER8 0 R/W
NDER12 0 R/W
Next data enable 15 to 8 Bits 7 to 0 NDER15 to NDER8 0 Description
TPC outputs TP15 to TP8 are disabled (NDR15 to NDR8 are not transferred to PB7 to PB0) TPC outputs TP15 to TP8 are enabled (NDR15 to NDR8 are transferred to PB7 to PB0)
1
NDERANext Data Enable Register A
Bit 7 NDER7 Initial value Read/Write 0 R/W 6 NDER6 0 R/W 5 NDER5 0 R/W 4
H'FFFA3
3 NDER3 0 R/W 2 NDER2 0 R/W 1 NDER1 0 R/W
TPC
0 NDER0 0 R/W
NDER4 0 R/W
Next data enable 7 to 0 Bits 7 to 0 NDER7 to NDER0 0 Description
TPC outputs TP7 to TP0 are disabled (NDR7 to NDR0 are not transferred to PA7 to PA0) TPC outputs TP7 to TP0 are enabled (NDR7 to NDR0 are transferred to PA7 to PA0)
1
Rev.5.00 Sep. 12, 2007 Page 702 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
NDRBNext Data Register B * Same trigger for TPC output groups 2 and 3 Address H'FFFA4
Bit 7 NDR15 Initial value Read/Write 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W
H'FFFA4/H'FFFA6
TPC
3 NDR11 0 R/W
2 NDR10 0 R/W
1 NDR9 0 R/W
0 NDR8 0 R/W
Store the next output data for TPC output group 3
Store the next output data for TPC output group 2
Address H'FFFA6
Bit 7 Initial value Read/Write 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
* Different triggers for TPC output groups 2 and 3 Address H'FFFA4
Bit 7 NDR15 Initial value Read/Write 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 1 2 1 1 1 0 1
Store the next output data for TPC output group 3
Address H'FFFA6
Bit 7 Initial value Read/Write 1 6 1 5 1 4 1 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W
Store the next output data for TPC output group 2
Rev.5.00 Sep. 12, 2007 Page 703 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
NDRANext Data Register A * Same trigger for TPC output groups 0 and 1 Address H'FFFA5
Bit 7 NDR7 Initial value Read/Write 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W
H'FFFA5/H'FFFA7
TPC
3 NDR3 0 R/W
2 NDR2 0 R/W
1 NDR1 0 R/W
0 NDR0 0 R/W
Store the next output data for TPC output group 1
Store the next output data for TPC output group 0
Address H'FFFA7
Bit 7 Initial value Read/Write 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
* Different triggers for TPC output groups 0 and 1 Address H'FFFA5
Bit 7 NDR7 Initial value Read/Write 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 1 2 1 1 1 0 1
Store the next output data for TPC output group 1
Address H'FFFA7
Bit 7 Initial value Read/Write 1 6 1 5 1 4 1 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W
Store the next output data for TPC output group 0
Rev.5.00 Sep. 12, 2007 Page 704 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
SMRSerial Mode Register
Bit 7 C/A Initial value Read/Write 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W
H'FFFB0
3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
SCI0
Clock select 1 and 0 Bit 1 Bit 0
CKS1 CKS0
Clock Source clock /4 clock /16 clock /64 clock
0
0 1 0
1
1
Multiprocessor mode 0 1 Multiprocessor function disabled Multiprocessor function selected
Stop bit length 0 1 Parity mode 0 1 Parity enable 0 1 Character length 0 1 8-bit data 7-bit data Parity bit is not added or checked Parity bit is added and checked Even parity Odd parity One stop bit Two stop bits
Communication mode (for serial communication interface) 0 1 Asynchronous mode Synchronous mode
GSM mode (for smart card interface) 0 1 TEND flag is set 12.5 etu* after start bit TEND flag is set 11.0 etu* after start bit
Note: * etu: Elementary time unit (time required to transmit one bit)
Rev.5.00 Sep. 12, 2007 Page 705 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
BRRBit Rate Register
Bit 7 6 5 4
H'FFFB1
3 2 1
SCI0
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Serial communication bit rate setting
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Appendix B Internal I/O Registers
SCRSerial Control Register
Bit 7 TIE Initial value Read/Write 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W
H'FFFB2
2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W
SCI0
Receive enable 0 1 Receiving is disabled Receiving is enabled
Transmit enable 0 1 Transmitting is disabled Transmitting is enabled
Clock enable 1 and 0 (for serial communication interface) Bit 1 Bit 0 Description CKE1 CKE0 Internal clock, SCK pin Asynchronous mode available for generic I/O 0 Internal clock, SCK pin Synchronous mode used for serial clock output 0 Internal clock, SCK pin Asynchronous mode used for clock output 1 Internal clock, SCK pin Synchronous mode used for serial clock output External clock, SCK pin Asynchronous mode used for clock input 0 External clock, SCK pin Synchronous mode used for serial clock input 1 External clock, SCK pin Asynchronous mode used for clock input 1 External clock, SCK pin Synchronous mode used for serial clock input Clock enable 1 and 0 (for smart card interface) SMR Bit 1 Bit 0 Description GM CKE1 CKE0 SCK pin available for generic I/O 0 0 0 SCK pin used for clock output 1 SCK pin output fixed low 0 0 SCK pin used for clock output 1 1 SCK pin output fixed high 0 1 SCK pin used for clock output 1 Transmit-end interrupt enable 0 1 Transmit-end interrupt requests (TEI) are disabled Transmit-end interrupt requests (TEI) are enabled
Multiprocessor interrupt enable 0 1 Receive interrupt enable 0 1 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled Multiprocessor interrupts are disabled (normal receive operation) Multiprocessor interrupts are enabled
Transmit interrupt enable 0 1 Transmit-data-empty interrupt request (TXI) is disabled Transmit-data-empty interrupt request (TXI) is enabled
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Appendix B Internal I/O Registers
TDRTransmit Data Register
Bit 7 6 5 4
H'FFFB3
3 2 1
SCI0
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Serial transmit data
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Appendix B Internal I/O Registers
SSRSerial Status Register
Bit 7 TDRE Initial value Read/Write 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER/ERS 0 R/(W)* 3 PER 0 R/(W)*
H'FFFB4
2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor bit transfer
SCI0
0 Multiprocessor bit value in transmit data is 0 1 Multiprocessor bit value in transmit data is 1 Multiprocessor bit Multiprocessor bit value in receive data is 1 Transmit end (for serial communication interface) 0 [Clearing conditions] * Read TDRE when TDRE = 1, then write 0 in TDRE. * The DMAC writes data in TDR. [Setting conditions] * Reset or transition to standby mode * TE is cleared to 0 in SCR. * TDRE is 1 when last bit of 1-byte serial character is transmitted. 0 1 Multiprocessor bit value in receive data is 0
1
Transmit end (for smart card interface) 0 [Clearing conditions] * Read TDRE when TDRE = 1, then write 0 in TDRE. * The DMAC writes data in TDR. [Setting conditions] * Reset or transition to standby mode * TE is cleared to 0 in SCR and FER/ERS is cleared to 0. * TDRE is 1 and FER/ERS is 0 (normal transmission) 2.5 etu* (when GM = 0) or 1.0 etu (when GM = 1) after 1-byte serial character is transmitted.
1
Note: * etu: Elementary time unit (time required to transmit one bit) Parity error 0 1 [Clearing conditions] * Reset or transition to standby mode * Read PER when PER = 1, then write 0 in PER. [Setting condition] Parity error (parity of receive data does not match parity setting of O/E bit in SMR)
Framing error (for serial communication interface) 0 1 [Clearing conditions] * Reset or transition to standby mode * Read FER when FER = 1, then write 0 in FER. [Setting condition] Framing error (stop bit is 0) [Clearing conditions] * Reset or transition to standby mode * Read ERS when ERS = 1, then write 0 in ERS. [Setting condition] A low error signal is received.
Error signal status (for smart card interface) 0 1 Overrun error 0 1 [Clearing conditions] * Reset or transition to standby mode * Read ORER when ORER = 1, then write 0 in ORER. [Setting condition] Overrun error (reception of the next serial data ends when RDRF = 1)
Receive data register full 0 1 [Clearing conditions] * Reset or transition to standby mode * Read RDRF when RDRF = 1, then write 0 in RDRF. * The DMAC reads data from RDR. [Setting condition] Serial data is received normally and transferred from RSR to RDR. Read TDRE when TDRE = 1, then write 0 in TDRE. The DMAC writes data in TDR. Reset or transition to standby mode TE is 0 in SCR. Data is transferred from TDR to TSR, enabling new data to be written in TDR
Transmit data register empty 0 1 [Clearing conditions] * * [Setting conditions] * * *
Note: * Only 0 can be written, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 709 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
RDRReceive Data Register
Bit 7 6 5 4
H'FFFB5
3 2 1
SCI0
0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Serial receive data
SCMRSmart Card Mode Register
Bit 7 Initial value Read/Write 1 6 1 5 1 4 1 3 SDIR 0 R/W
H'FFFB6
2 SINV 0 R/W 1 1 0 SMIF 0 R/W
SCI0
Smart card interface mode select 0 1 Smart card interface function is disabled (Initial value) Smart card interface function is enabled
Smart card data invert Unmodified TDR contents are transmitted 0 Receive data is stored unmodified in RDR Inverted TDR contents are transmitted Received data are inverted before storage in RDR (Initial value)
1
Smart card data transfer direction TDR contents are transmitted LSB-first 0 Receive data is stored LSB-first in RDR TDR contents are transmitted MSB-first Receive data is stored MSB-first in RDR (Initial value)
1
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Appendix B Internal I/O Registers
SMRSerial Mode Register
Bit 7 C/A Initial value Read/Write 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W
H'FFFB8
3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W
SCI1
0 CKS0 0 R/W
Note: Bit functions are the same as for SCI0.
BRRBit Rate Register
Bit 7 6 5 4
H'FFFB9
3 2 1
SCI1
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Bit functions are the same as for SCI0.
SCRSerial Control Register
Bit 7 TIE Initial value Read/Write 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W
H'FFFBA
3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W
SCI1
0 CKE0 0 R/W
Note: Bit functions are the same as for SCI0.
TDRTransmit Data Register
Bit 7 6 5 4
H'FFFBB
3 2 1
SCI1
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Bit functions are the same as for SCI0.
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Appendix B Internal I/O Registers
SSRSerial Status Register
Bit 7 TDRE Initial value Read/Write 0 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4
H'FFFBC
3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R
SCI1
0 MPBT 0 R/W
FER/ERS 0 R/(W)*
Notes: Bit functions are the same as for SCI0. * Only 0 can be written, to clear the flag.
RDRReceive Data Register
Bit 7 6 5 4
H'FFFBD
3 2 1
SCI1
0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Note: Bit functions are the same as for SCI0.
SCMRSmart Card Mode Register
Bit 7 Initial value Read/Write 1 6 1 5 1 4 1
H'FFFBE
3 SDIR 0 R/W 2 SINV 0 R/W 1 1
SCI1
0 SMIF 0 R/W
Note: Bit functions are the same as for SCI0.
SMRSerial Mode Register
Bit 7 C/A Initial value Read/Write 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W
H'FFFC0
3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W
SCI2
0 CKS0 0 R/W
Note: Bit functions are the same as for SCI0.
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Appendix B Internal I/O Registers
BRRBit Rate Register
Bit 7 6 5 4
H'FFFC1
3 2 1
SCI2
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Bit functions are the same as for SCI0.
SCRSerial Control Register
Bit 7 TIE Initial value Read/Write 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W
H'FFFC2
3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W
SCI2
0 CKE0 0 R/W
Note: Bit functions are the same as for SCI0.
TDRTransmit Data Register
Bit 7 6 5 4
H'FFFC3
3 2 1
SCI2
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Bit functions are the same as for SCI0.
SSRSerial Status Register
Bit 7 TDRE Initial value Read/Write Notes: 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4
H'FFFC4
3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R
SCI2
0 MPBT 0 R/W
FER/ERS 0 R/(W)*
Bit functions are the same as for SCI0. * Only 0 can be written, to clear the flag.
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Appendix B Internal I/O Registers
RDRReceive Data Register
Bit 7 6 5 4
H'FFFC5
3 2 1
SCI2
0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Note: Bit functions are the same as for SCI0.
SCMRSmart Card Mode Register
Bit 7 Initial value Read/Write 1 6 1 5 1 4 1
H'FFFC6
3 SDIR 0 R/W 2 SINV 0 R/W 1 1
SCI2
0 SMIF 0 R/W
Note: Bit functions are the same as for SCI0.
P4DRPort 4 Data Register
Bit 7 P47 Initial value Read/Write 0 R/W 6 P46 0 R/W 5 P45 0 R/W 4 P44 0 R/W
H'FFFD3
3 P43 0 R/W 2 P42 0 R/W 1 P41 0 R/W
Port 4
0 P40 0 R/W
Data for port 4 pins
P6DRPort 6 Data Register
Bit 7 P67 Initial value Read/Write * R 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W
H'FFFD5
3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W
Port 6
0 P60 0 R/W
Data for port 6 pins Note: * Determined by pin P67.
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Appendix B Internal I/O Registers
P7DRPort 7 Data Register
Bit 7 P77 Initial value Read/Write * R 6 P76 * R 5 P75 * R 4 P74 * R
H'FFFD6
3 P73 * R 2 P72 * R 1 P71 * R
Port 7
0 P70 * R
Data for port 7 pins Note: * Determined by pins P77 to P70.
P8DRPort 8 Data Register
Bit 7 Initial value Read/Write 1 6 1 5 1 4 P84 0 R/W
H'FFFD7
3 P83 0 R/W 2 P82 0 R/W Data for port 8 pins 1 P81 0 R/W
Port 8
0 P80 0 R/W
P9DRPort 9 Data Register
Bit 7 Initial value Read/Write 1 6 1 5 P95 0 R/W 4 P94 0 R/W
H'FFFD8
3 P93 0 R/W 2 P92 0 R/W 1 P91 0 R/W
Port 9
0 P90 0 R/W
Data for port 9 pins
PADRPort A Data Register
Bit 7 PA7 Initial value Read/Write 0 R/W 6 PA6 0 R/W 5 PA5 0 R/W 4 PA4 0 R/W
H'FFFD9
3 PA3 0 R/W 2 PA2 0 R/W 1 PA1 0 R/W
Port A
0 PA0 0 R/W
Data for port A pins
Rev.5.00 Sep. 12, 2007 Page 715 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
PBDRPort B Data Register
Bit 7 PB7 Initial value Read/Write 0 R/W 6 PB6 0 R/W 5 PB5 0 R/W 4 PB4 0 R/W
H'FFFDA
3 PB3 0 R/W 2 PB2 0 R/W 1 PB1 0 R/W
Port B
0 PB0 0 R/W
Data for port B pins
ADDRA H/LA/D Data Register A H/L
Bit 15 14 13 12 11 10 9
H'FFFE0, H'FFFE1
8 7 6 5 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R
A/D
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
ADDRAH
ADDRAL
A/D conversion data 10-bit data giving an A/D conversion result
ADDRB H/LA/D Data Register B H/L
Bit 15 14 13 12 11 10 9
H'FFFE2, H'FFFE3
8 7 6 5 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R
A/D
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
ADDRBH
ADDRBL
A/D conversion data 10-bit data giving an A/D conversion result
Rev.5.00 Sep. 12, 2007 Page 716 of 764 REJ09B0396-0500
Appendix B Internal I/O Registers
ADDRC H/LA/D Data Register C H/L
Bit 15 14 13 12 11 10 9
H'FFFE4, H'FFFE5
8 7 6 5 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R
A/D
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
ADDRCH
ADDRCL
A/D conversion data 10-bit data giving an A/D conversion result
ADDRD H/LA/D Data Register D H/L
Bit 15 14 13 12 11 10 9
H'FFFE6, H'FFFE7
8 7 6 5 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R
A/D
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
ADDRDH
ADDRDL
A/D conversion data 10-bit data giving an A/D conversion result
ADCRA/D Control Register
Bit 7 TRGE Initial value Read/Write 0 R/W 6 1 5 1 4 1
H'FFFE9
3 1 2 1 1 1 0 0 R/W
A/D
Trigger Enable 0 1 A/D conversion start by external trigger or 8-bit timer compare match is disabled A/D conversion is started by falling edge of external trigger signal (ADTRG) or 8-bit timer compare match
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Appendix B Internal I/O Registers
ADCSRA/D Control/Status Register
Bit 7 ADF Initial value Read/Write 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W
H'FFFE8
1 CH1 0 R/W 0 CH0 0 R/W
A/D
Channel select Clock select Conversion time = Group Selection Channel Selection Description 0 134 states (maximum) CH2 CH1 CH0 Single Mode Scan Mode AN0 0 AN0 Conversion time = 1 0 1 AN1 AN0, AN1 70 states (maximum) 0 0 AN2 AN0 to AN2 1 1 AN3 AN0 to AN3 0 AN4 AN4 0 Scan mode 1 AN5 AN4, AN5 1 Single mode 0 0 AN6 AN4 to AN6 1 1 Scan mode 1 AN7 AN4 to AN7 A/D start 0 A/D conversion is stopped 1. Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends 1 2. Scan mode: A/D conversion starts and continues, cycling among the selected channels ADST is cleared to 0 by software, by a reset, or by a transition to standby mode A/D interrupt enable 0 1 A/D end flag 0 1 [Clearing conditions] * Read ADF when ADF = 1, then write 0 in ADF * The DMAC is activated by an ADI interrupt [Setting conditions] * Single mode: A/D conversion ends * Scan mode: A/D conversion ends in all selected channels A/D end interrupt request is disabled A/D end interrupt request is enabled
Note: * Only 0 can be written, to clear the flag.
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Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams
C.1 Port 4 Block Diagram
8-bit bus mode 16-bit bus mode Reset
Internal data bus (upper) Internal data bus (lower)
R Q P4 n PCR RP4P C WP4P Reset R Write to external address Q P4 n DDR C WP4D Reset R P4n Q P4n DR C WP4 D D D
RP4
Read external address Legend: WP4P: Write to P4PCR RP4P: Read P4PCR WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Note: n = 0 to 7
Figure C.1 Port 4 Block Diagram
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Appendix C I/O Port Block Diagrams
C.2
Port 6 Block Diagrams
Reset
Q P60 DDR C WP6D
D
Internal data bus
R
Bus controller WAIT input enable
Reset R P60 Q P60 DR C WP6 D
RP6 Bus controller WAIT input Legend: WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6
Figure C.2 (a) Port 6 Block Diagram (Pin P60)
Rev.5.00 Sep. 12, 2007 Page 720 of 764 REJ09B0396-0500
Appendix C I/O Port Block Diagrams
Reset
Internal data bus
R Q P6 1 DDR C WP6D Reset R P61 Q P61 DR C WP6 D D
Bus controller
Bus release enable
RP6
BREQ input Legend: WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6
Figure C.2 (b) Port 6 Block Diagram (Pin P61)
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Appendix C I/O Port Block Diagrams
Reset R Q P6 2 DDR C WP6D Reset R P62 Q P62 DR C WP6 D Bus controller Bus release enable BACK output D
RP6
Legend: WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6
Figure C.2 (c) Port 6 Block Diagram (Pin P62)
Rev.5.00 Sep. 12, 2007 Page 722 of 764 REJ09B0396-0500
Internal data bus
Appendix C I/O Port Block Diagrams
Hardware standby output enable
Internal data bus
P67
output
RP6
Legend: RP6: Read port 6
Figure C.2 (d) Port 6 Block Diagram (Pin P67)
C.3
Port 7 Block Diagrams
Internal data bus
RP7 P7 n
A/D converter
Analog input Legend: RP7: Read port 7 Note: n = 0 to 5 Input enable Channel select signal
Figure C.3 (a) Port 7 Block Diagram (Pins P70 to P75)
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Appendix C I/O Port Block Diagrams
RP7 P7 n
Internal data bus
A/D converter
Analog input Input enable Channel select signal D/A converter Output enable Analog output
Legend: RP7: Read port 7 Note: n = 6 and 7
Figure C.3 (b) Port 7 Block Diagram (Pins P76 and P77)
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Appendix C I/O Port Block Diagrams
C.4
Port 8 Block Diagrams
Reset R Q D P80DDR C WP8D Reset
P80
R Q D P80DR C WP8
Internal data bus
Refresh controller Output enable RFSH output Interrupt controller IRQ0 input
RP8
Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8
Figure C.4 (a) Port 8 Block Diagram (Pin P80)
Rev.5.00 Sep. 12, 2007 Page 725 of 764 REJ09B0396-0500
Appendix C I/O Port Block Diagrams
Internal data bus
Bus controller CS2 CS3 output Interrupt controller IRQ1 IRQ2 input Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 SSOE: Software standby output port enable Note: n = 1 and 2
SSOE Software standby
Reset R Q D P8nDDR C WP8D Reset
P8n
R Q D P8nDR C WP8
RP8
Figure C.4 (b) Port 8 Block Diagram (Pins P81, P82)
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Appendix C I/O Port Block Diagrams
Internal data bus
SSOE Software standby
Reset R Q D P83DDR C WP8D
Bus controller CS1 output
Reset P83 R Q D P83DR C WP8
RP8
Interrupt controller IRQ3 input A/D converter ADTRG input
Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 SSOE: Software standby output port enable
Figure C.4 (c) Port 8 Block Diagram (Pin P83)
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Appendix C I/O Port Block Diagrams
Internal data bus
SSOE Software standby
Reset R Q D P84DDR C WP8D
Bus controller
CS0 output Reset P84 R Q D P84DR C WP8
RP8
Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 SSOE: Software standby output port enable
Figure C.4 (d) Port 8 Block Diagram (Pin P84)
Rev.5.00 Sep. 12, 2007 Page 728 of 764 REJ09B0396-0500
Appendix C I/O Port Block Diagrams
C.5
Port 9 Block Diagrams
Reset R Q P9 0 DDR C WP9D Reset R P90 Q P90 DR C WP9 D SCI Output enable Serial transmit data Guard time RP9 D
Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9
Figure C.5 (a) Port 9 Block Diagram (Pin P90)
Rev.5.00 Sep. 12, 2007 Page 729 of 764 REJ09B0396-0500
Internal data bus
Appendix C I/O Port Block Diagrams
Reset R Q D P91DDR C WP9D Reset P91 R Q D P91DR C WP9
Internal data bus
SCI Output enable Serial transmit data Guard time
RP9
Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9
Figure C.5 (b) Port 9 Block Diagram (Pin P91)
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Appendix C I/O Port Block Diagrams
Reset R Q P9 2 DDR C WP9D Reset R P92 Q P9 2 DR C WP9 D D
Internal data bus
SCI Input enable
RP9
Serial receive data Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9
Figure C.5 (c) Port 9 Block Diagram (Pin P92)
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Appendix C I/O Port Block Diagrams
Reset R Q D P93DDR C WP9D Reset P93 R Q D P93DR C WP9
Internal data bus
SCI Input enable
RP9
Serial receive data
Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9
Figure C.5 (d) Port 9 Block Diagram (Pin P93)
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Appendix C I/O Port Block Diagrams
Reset R Q P9 4DDR C WP9D Reset R P94 Q P9 4 DR C WP9 Clock output enable Clock output D D
Internal data bus
SCI Clock input enable
RP9
Clock input Interrupt controller IRQ 4 input Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9
Figure C.5 (e) Port 9 Block Diagram (Pin P94)
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Appendix C I/O Port Block Diagrams
Reset R Q P9 5DDR C WP9D Reset R P95 Q P9 5 DR C WP9 Clock output enable Clock output D D
Internal data bus
SCI Clock input enable
RP9
Clock input Interrupt controller IRQ 5 input Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9
Figure C.5 (f) Port 9 Block Diagram (Pin P95)
Rev.5.00 Sep. 12, 2007 Page 734 of 764 REJ09B0396-0500
Appendix C I/O Port Block Diagrams
C.6
Port A Block Diagrams
Reset R Q PA n DDR C WPAD Reset R D
Internal data bus
WPA
TPC
PA n
Q PA n DR C
D
TPC output enable Next data
Output trigger DMA controller Output enable Transfer end output
RPA
16-bit timer Counter clock input 8-bit timer Counter clock input
Legend: WPAD: Write to PADDR WPA: Write to port A RPA: Read port A Note: n = 0 and 1
Figure C.6 (a) Port A Block Diagram (Pins PA0, PA1)
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Appendix C I/O Port Block Diagrams
Reset R Q PA n DDR C WPAD Reset R PA n Q PA n DR C D D
Internal data bus
WPA
TPC
TPC output enable Next data
Output trigger 16-bit timer Output enable Compare match output
RPA
Input capture Counter clock input 8-bit timer Counter clock input
Legend: WPAD: Write to PADDR WPA: Write to port A RPA: Read port A Note: n = 2 and 3
Figure C.6 (b) Port A Block Diagram (Pins PA2, PA3)
Rev.5.00 Sep. 12, 2007 Page 736 of 764 REJ09B0396-0500
Appendix C I/O Port Block Diagrams
Software standby Bus released SSOE
R Q PAnDDR C WPAD Reset R PA n Q PAnDR C D D
Internal address bus
Internal data bus
Address output enable Mode 3/4 Reset
TPC
TPC output enable Next data
WPA
Output trigger 16-bit timer Output enable Compare match output
PRA Input capture Legend: WPAD: Write to PADDR WPA: Write to port A RPA: Read port A SSOE: Software standby output port enable Notes: 1. n = 4 to 7 2. PA7 address output enable is fixed at 1 in modes 3 and 4.
Figure C.6 (c) Port A Block Diagram (Pins PA4 to PA7)
Rev.5.00 Sep. 12, 2007 Page 737 of 764 REJ09B0396-0500
Appendix C I/O Port Block Diagrams
C.7
Port B Block Diagrams
Internal data bus
Bus controller CS7 CS5 output CS output enable TPC TPC output enable Next data WPB Output trigger 8-bit timer Output enable Compare match output
Software standby SSOE Reset R Q D PBnDDR C
Bus released
WPBD Reset
PBn
R Q D PBnDR C
RPB
Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B SSOE: Software standby output port enable Note: n = 0 and 2
Figure C.7 (a) Port B Block Diagram (Pins PB0, PB2)
Rev.5.00 Sep. 12, 2007 Page 738 of 764 REJ09B0396-0500
Appendix C I/O Port Block Diagrams
Internal data bus
Software standby Reset SSOE R Q D PBnDDR C
Bus released
Bus controller CS6 CS4 output CS output enable TPC TPC output enable Next data WPB Output trigger 8-bit timer Output enable Compare match output
WPBD Reset
PBn
R Q D PBnDR C
RPB TMO2 TMO3 input DMAC DREQ0 DREQ1 input Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B SSOE: Software standby output port enable Note: n = 1 and 3
Figure C.7 (b) Port B Block Diagram (Pins PB1, PB3)
Rev.5.00 Sep. 12, 2007 Page 739 of 764 REJ09B0396-0500
Appendix C I/O Port Block Diagrams
R Q PB 4 DDR C WPBD Reset R PB4 Q PB 4 DR C D D
Internal data bus
WPB
Reset
TPC
TPC output enable Next data
Output trigger Bus controller CAS output enable CAS output
RPB Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B
Figure C.7 (c) Port B Block Diagram (Pin PB4)
Rev.5.00 Sep. 12, 2007 Page 740 of 764 REJ09B0396-0500
Appendix C I/O Port Block Diagrams
Internal data bus
Reset R Q D PB5DDR C WPBD Reset R Q PB5 D PB5DR C WPB
SCI Clock input enable TPC TPC output enable
Next data
Output trigger Bus controller CAS output enable CAS output SCI Clock output enable Clock output
RPB
Clock input Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B
Figure C.7 (d) Port B Block Diagram (Pin PB5)
Rev.5.00 Sep. 12, 2007 Page 741 of 764 REJ09B0396-0500
Appendix C I/O Port Block Diagrams
Reset R Q PB 6 DDR C WPBD Reset R PB6 Q PB6 DR C D Next data TPC output enable D
Internal data bus
WPB
TPC
Output trigger
SCI Output enable Serial transmit data Guard time
RPB
Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B
Figure C.7 (e) Port B Block Diagram (Pin PB6)
Rev.5.00 Sep. 12, 2007 Page 742 of 764 REJ09B0396-0500
Appendix C I/O Port Block Diagrams
Reset R Q PB 7 DDR C WPBD Reset R PB7 Q PB7 DR C D Next data D
Internal data bus
SCI Input enable TPC TPC output enable
WPB Output trigger
RPB SCI Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Serial receive data
Figure C.7 (f) Port B Block Diagram (Pin PB7)
Rev.5.00 Sep. 12, 2007 Page 743 of 764 REJ09B0396-0500
Appendix D Pin States
Appendix D Pin States
D.1 Port States in Each Mode
Port States in Each Processing State
Hardware Standby Mode T T Program Execution State T*1 A19 to A0
Table D.1
Port Name Pin Name RESO A19 to A0
Mode 1 to 4
Reset T* L
1
Software Standby Mode T [SSOE = 0] T [SSOE = 1] Keep
Bus-Released State T*1 T
D15 to D8 AS, RD, HWR, LWR
1 to 4 1 to 4
T H
T T
T [SSOE = 0] T [SSOE = 1] H
T T
D15 to D8 AS, RD, HWR, LWR
P47 to P40
1, 3 2, 4
T T T T
T T T T
Keep T Keep [BRLE = 0] Keep [BRLE = 1] T
Keep T Keep T
I/O port D7 to D0 I/O port WAIT I/O port BREQ
P60 P61
1 to 4 1 to 4
P62
1 to 4
T
T
[BRLE = 0] Keep [BRLE = 1] H
L
[BRLE = 0] I/O port [BRLE = 1] BACK
P67
1 to 4
Clock output
T
[PSTOP = 0] H [PSTOP = 1] Keep
[PSTOP = 0] [PSTOP = 1] Keep T
[PSTOP = 0] [PSTOP = 1] Input port Input port
P77 to P70
1 to 4
T
T
T
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Appendix D Pin States
Hardware Standby Mode T Program Execution State
Port Name Pin Name P80
Mode 1 to 4
Reset T
Software Standby Mode * When DRAM space is not selected*2 [RFSHE = 0] Keep [RFSHE = 1] Illegal setting * When DRAM space is selected*3 [RFSHE = 0] Keep [RFSHE = 1, SRFMD = 0, SSOE = 0] T [RFSHE = 1, SRFMD = 0, SSOE = 1] H [RFSHE = 1, SRFMD = 1] RFSH
Bus-Released State
* When DRAM space [RFSHE = 0] I/O port is not selected*2 [RFSHE = 0] Keep [RFSHE = 1] Illegal setting * When DRAM space is selected*3 [RFSHE = 0] Keep [RFSHE = 1] T [RFSHE = 1] RFSH
P81
1 to 4
T
T
* RAS3 output*4 [SSOE = 0] T [SSOE = 1] H * Otherwise*5 [DDR = 0] T [DDR = 1, SSOE = 0] T [DDR = 1, SSOE = 1] H
* RAS3 output*4 T * Otherwise* [DDR = 0] Keep [DDR = 1] T
5
* RAS3 output RAS3 * Otherwise [DDR = 0] Input port
[DDR = 1]
CS3
Rev.5.00 Sep. 12, 2007 Page 745 of 764 REJ09B0396-0500
Appendix D Pin States
Hardware Standby Mode T Program Execution State * RAS2 output RAS2
2
Port Name Pin Name P82
Mode 1 to 4
Reset T
Software Standby Mode * RAS2 output* [SSOE = 0] T [SSOE = 1] H * Otherwise*2 [DDR = 0] T [DDR = 1, SSOE = 0] T [DDR = 1, SSOE = 1] H
3
Bus-Released State * RAS2 output*3 T * Otherwise* [DDR = 0] Keep [DDR = 1] T
* Otherwise [DDR = 0] Input port [DDR = 1] CS2
P83
1 to 4
T
T
[DDR = 0] T [DDR = 1, SSOE = 0] T [DDR = 1, SSOE = 1] H
[DDR = 0] Keep [DDR = 1] T
[DDR = 0] Input port [DDR = 1] CS1
P84
1 to 4
H
T
[DDR = 0] T [DDR = 1, SSOE = 0] T [DDR = 1, SSOE = 1] H
[DDR = 0] Keep [DDR = 1] T
[DDR = 0] Input port [DDR = 1] CS0
P95 to P90 PA3 to PA0 PA6 to PA4
1 to 4 1 to 4 1, 2 3, 4
T T T T
T T T T
Keep Keep Keep * Address output* [SSOE = 0] T [SSOE = 1] Keep * Otherwise*7 Keep
6
Keep Keep Keep * Address output* T * Otherwise*7 Keep
6
I/O port I/O port I/O port * Address output A23 to A21 * Otherwise * I/O port
Rev.5.00 Sep. 12, 2007 Page 746 of 764 REJ09B0396-0500
Appendix D Pin States
Hardware Standby Mode T T Program Execution State I/O port A20
Port Name Pin Name PA7
Mode 1, 2 3, 4
Reset T L
Software Standby Mode Keep [SSOE = 0] T [SSOE = 1] Keep
Bus-Released State Keep T
PB1, PB0
1 to 4
T
T
* CS output*8 [SSOE = 0] T [SSOE = 1] H * Otherwise*9 Keep
* CS output*8 T * Otherwise*9 Keep
* CS output CS7, CS6 * Otherwise I/O port
PB2
1 to 4
T
T
* RAS5 output*10 [SSOE = 0] T [SSOE = 1] H * CS output*11 [SSOE = 0] T [SSOE = 1] H * Otherwise*12 Keep
* RAS5 output*10 T * CS output *11 T * Otherwise* Keep
12
* RAS5 output RAS5 * CS output CS5 * Otherwise I/O port
PB3
1 to 4
T
T
* RAS4 output*13 [SSOE = 0] T [SSOE = 1] H * CS output*14 [SSOE = 0] T [SSOE = 1] H * Otherwise*15 Keep
* RAS4 output*13 T * CS output *14 T * Otherwise*15 Keep
* RAS4 output RAS4 * CS output CS4 * Otherwise I/O port
Rev.5.00 Sep. 12, 2007 Page 747 of 764 REJ09B0396-0500
Appendix D Pin States
Hardware Standby Mode T Program Execution State * CAS output UCAS, LCAS * Otherwise I/O port
Port Name Pin Name PB5, PB4
Mode 1 to 4
Reset T
Software Standby Mode * CAS output* [SSOE = 0] T [SSOE = 1] H * Otherwise*17 Keep
16
Bus-Released State * CAS output*16 T * Otherwise* Keep
17
PB7, PB6
1 to 4
T
T
Keep
Keep
I/O port
Legend: H: High L: Low T: High-impedance state Keep: Input pins are in the high-impedance state; output pins maintain their previous state. DDR: Data direction register Notes: 1. Low only when WDT overflow causes a reset. 2. When bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) are all cleared to 0. 3. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is set to 1. 4. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is 010, 100, or 101. 5. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 010, 100, or 101. 6. When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is cleared to 0. 7 When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is set to 1. 8. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is set to 1. 9. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is cleared to 0. 10. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is 101. 11. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 101, and bit CS5E in CSCR (chip select control register) is set to 1. 12. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 101, and bit CS5E in CSCR (chip select control register) is cleared to 0.
Rev.5.00 Sep. 12, 2007 Page 748 of 764 REJ09B0396-0500
Appendix D Pin States 13. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is 100, 101, or 110. 14. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 100, 101, or 110, and bit CS4E in CSCR (chip select control register) is set to 1. 15. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 100, 101, or 110, and bit CS4E in CSCR (chip select control register) is cleared to 0. 16. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is set to 1, and bit CSEL in DRCRB (DRAM control register B) is cleared to 0. 17. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is set to 1, and bit CSEL in DRCRB (DRAM control register B) is set to 1; or, when bits DRAS2, DRAS1, and DRAS0 are cleared to 0.
Rev.5.00 Sep. 12, 2007 Page 749 of 764 REJ09B0396-0500
Appendix D Pin States
D.2
Pin States at Reset
Modes 1 and 2: Figure D.1 is a timing diagram for the case in which RES goes low during an external memory access in mode 1 or 2. As soon as RES goes low, all ports are initialized to the input state. AS, RD, HWR, LWR, and CS0 go high, and D15 to D0 go to the high-impedance state. The address bus is initialized to the low output level 2.5 clock cycles after the low level of RES is sampled. Clock pin P67/ goes to the output state at the next rise of after RES goes low.
Access to external memory T1 P67/ RES Internal reset signal A19 to A0 CS0 AS, RD (read) HWR, LWR (write) D15 to D0 (write) I/O port, CS7 to CS1 High impedance High impedance H'00000 T2 T3
Figure D.1 Reset during Memory Access (Modes 1 and 2)
Rev.5.00 Sep. 12, 2007 Page 750 of 764 REJ09B0396-0500
Appendix D Pin States
Modes 3 and 4: Figure D.2 is a timing diagram for the case in which RES goes low during an external memory access in mode 3 or 4. As soon as RES goes low, all ports are initialized to the input state. AS, RD, HWR, LWR, and CS0 go high, and D15 to D0 go to the high-impedance state. The address bus is initialized to the low output level 2.5 clock cycles after the low level of RES is sampled. However, when PA4 to PA6 are used as address bus pins, or when P83 to P81 and PB0 to PB3 are used as CS output pins, they go to the high-impedance state at the same time as RES goes low. Clock pin P67/ goes to the output state at the next rise of after RES goes low.
Access to external memory T1 P67/ RES Internal reset signal A20 to A0 CS0 AS, RD (read) HWR, LWR (write) D15 to D0 (write) I/O port, PA4/A23 to PA6/ A21, CS7 to CS1 High impedance H'000000 T2 T3
High impedance
Figure D.2 Reset during Memory Access (Modes 3 and 4)
Rev.5.00 Sep. 12, 2007 Page 751 of 764 REJ09B0396-0500
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
STBY t1 10tcyc RES t2 0 ns
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained, RES does not have to be driven low as in (1). Timing of Recovery from Hardware Standby Mode: Drive the RES signal low approximately 100 ns before STBY goes high.
STBY t 100 ns RES tOSC
Rev.5.00 Sep. 12, 2007 Page 752 of 764 REJ09B0396-0500
Appendix F List of Product Codes
Appendix F List of Product Codes
Table F.1
Part No. H8/3007 5.0 V 10% (5 V)
H8/3007, H8/3006 Product Code Lineup
Product Code HD6413007F HD6413007TE HD6413007FP 2.7 to 5.5 V HD6413007VF (Low voltage) HD6413007VTE HD6413007VFP Mark Code HD6413007F HD6413007TE HD6413007FP HD6413007VF HD6413007VTE HD6413007VFP HD6413006F HD6413006TE HD6413006FP HD6413006VF HD6413006VTE HD6413006VFP Package Code 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100A) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100A) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100A) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100A)
H8/3006 5.0 V 10% (5 V)
HD6413006F HD6413006TE HD6413006FP
2.7 to 5.5 V HD6413006VF (Low voltage) HD6413006VTE HD6413006VFP
Rev.5.00 Sep. 12, 2007 Page 753 of 764 REJ09B0396-0500
Appendix G Package Dimensions
Appendix G Package Dimensions
The package dimention that is shown in the Renesas Semiconductor Package Data Book has priority.
JEITA Package Code P-QFP100-14x14-0.50 RENESAS Code PRQP0100KA-A Previous Code FP-100B/FP-100BV MASS[Typ.] 1.2g
HD
*1
D
75
51
76
50 bp b1
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
c1
*2
HE
E
c
Terminal cross section
ZE
100 26
Reference Dimension in Millimeters Symbol
1 ZD
25
F
A1
L L1
Detail F
e
*3
y
bp
x
M
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
Nom Max 14 14 2.70 15.7 16.0 16.3 15.7 16.0 16.3 3.05 0.00 0.12 0.25 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0 8 0.5 0.08 0.10 1.0 1.0 0.3 0.5 0.7 1.0
Min
A
A2
Figure G.1 Package Dimensions (FP-100B)
Rev.5.00 Sep. 12, 2007 Page 754 of 764 REJ09B0396-0500
c
Appendix G Package Dimensions
JEITA Package Code P-TQFP100-14x14-0.50 RENESAS Code PTQP0100KA-A Previous Code TFP-100B/TFP-100BV MASS[Typ.] 0.5g
HD
*1
D 51
75
76
50
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp b1
c1
*2
HE
E
c
Terminal cross section
ZE
Reference Dimension in Millimeters Symbol
100
26
A2
1 ZD Index mark
25
F
A1
L L1
Detail F
e
*3
y
bp
x
M
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
Nom Max 14 14 1.00 15.8 16.0 16.2 15.8 16.0 16.2 1.20 0.00 0.10 0.20 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 8 0 0.5 0.08 0.10 1.00 1.00 0.4 0.5 0.6 1.0
Min
Figure G.2 Package Dimensions (TFP-100B)
A
Rev.5.00 Sep. 12, 2007 Page 755 of 764 REJ09B0396-0500
c
Appendix G Package Dimensions
JEITA Package Code P-QFP100-14x20-0.65 RENESAS Code PRQP0100JE-B Previous Code FP-100A/FP-100AV MASS[Typ.] 1.7g
HD
*1
D 51
80
81
50
bp b1
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
c1
ZE
*2
HE
E
Terminal cross section
c
100
31
Reference Dimension in Millimeters Symbol
1 ZD
30
F
A1
L L1
Detail F
e
*3
y
bp
x
M
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
Nom Max 20 14 2.70 24.4 24.8 25.2 18.4 18.8 19.2 3.10 0.00 0.20 0.30 0.24 0.32 0.40 0.30 0.12 0.17 0.22 0.15 0 10 0.65 0.13 0.15 0.58 0.83 1.0 1.2 1.4 2.4
Min
A
A2
Figure G.3 Package Dimensions (FP-100A)
Rev.5.00 Sep. 12, 2007 Page 756 of 764 REJ09B0396-0500
c
Appendix H Comparison of H8/300H Series Product Specifications
Appendix H Comparison of H8/300H Series Product Specifications
H.1 Differences between H8/3067 and H8/3062 Group, H8/3048 Group, H8/3006 and H8/3007, and H8/3002
H8/3067, H8/3062 Group 16 MB ROM enabled expanded mode H8/3048 Group 1 MB ROM enabled expanded mode H8/3006, H8/3007 H8/3002
Item 1 Operating Mode 5 mode
Mode 6
64 KB single-chip mode 16 MB ROM enabled expanded mode 30 36 30
2
Interrupt Internal interrupt 36 (H8/3067) controller sources 27 (H8/3062) Bus Burst ROM controller interface Yes (H8/3067) No (H8/3062)
3
No
Yes
No
Idle cycle Yes insertion function Wait mode 2 modes
No 4 modes
Yes 2 modes
No 4 modes Common to all areas Fixed
Wait state numberPer area setting Address output method
Common Per area to all areas Fixed
Choice of address update Fixed mode (mask ROM and flash memory R versions only) Area 2/3/4/5 (H8/3067 only) Area 3 No No 8 bit/9 bit
4
DRAM interface
Connectable areas
Area 2/3/4/5 Yes Yes 8 bit/9 bit/10 bit
Area 3 No No 8 bit/9 bit
Precharge cycle Yes (H8/3067 only) insertion function Fast page mode Yes (H8/3067 only) Address shift amount 8 bit/9 bit/10 bit (H8/3067 only)
Rev.5.00 Sep. 12, 2007 Page 757 of 764 REJ09B0396-0500
Appendix H Comparison of H8/300H Series Product Specifications
H8/3067, H8/3062 Group 16-bit timers 16 bits x 3 6 pins 6 8-bit timers H8/3048 Group ITU
Item 5 Timer functions Number of channels Pulse output Input capture External clock Internal clock Complementary PWM function Resetsynchronous PWM function
H8/3006, H8/3007 16-bit timers 16 bits x 3 6 pins 6 8-bit timers
H8/3002 ITU
8 bits x 4 16 bits x 5 (16 bits x 2) 4 pins (2 pins) 2 12 pins 10
8 bits x 4 16 bits x 5 (16 bits x 2) 4 pins (2 pins) 2 12 pins 10 4 systems (selectable) , /2, /4, /8 Yes Yes
4 systems 4 systems (selectable) (fixed) , /2, /4, /8 No No /8, /64, /8192 No No
4 systems 4 systems 4 systems (selectable) (selectable) (fixed) , /2, /4, /8 Yes Yes , /2, /4, /8 No No /8, /64, /8192 No No
Buffer operation No Output initialization function PWM output Yes
No No
Yes No
No Yes
No No
Yes No
3
4 (2)
5
3
4 (2)
5 4 channels
DMAC activation 3 channels No (H8/3067 only) A/D conversion activation No Yes 8 sources
4 channels 3 channels No
No 3 sources x5 4 kinds, ITU base Yes
No 3 sources x3
Yes 8 sources
No 3 sources x5 4 kinds, ITU base Yes
Interrupt sources 3 sources x3 6 7 TPC WDT Time base Reset signal external output function Number of channels Smart card interface
3 kinds, 16-bit timer base Yes (except products with on-chip flash memory) 3 channels (H8/3067) 2 channels (H8/3062) Supported on all channels
3 kinds, 16-bit timer base Yes
8
SCI
2 channels 3 channels
2 channels
Supported on SCI0 only
Supported on all channels
No
Rev.5.00 Sep. 12, 2007 Page 758 of 764 REJ09B0396-0500
Appendix H Comparison of H8/300H Series Product Specifications
H8/3067, H8/3062 Group H8/3048 Group External trigger 134/266
Item 9
H8/3006, H8/3007 External trigger/8-bit timer compare match 70/134
H8/3002 External trigger 134/266
A/D Conversion start External trigger/8-bit converter trigger input timer compare match Conversion states 70/134
10
Pin control
pin
/input port multiplexing output only
/input port multiplexing output only
A20 in 16 MB ROM A20 / I/O port multiplexing A20 output enabled expanded mode Address bus, High-level output/highAS, RD, HWR, impedance selectable LWH, CS7 to CS0, (RFSH: H8/3067 only) RFSH in software standby state CS7 to CS0 in bus- High-impedance released state 11 Flash memory functions Program/erase voltage 12 V application unnecessary. Single-power-supply programming. 8 blocks High-level High-level output/highimpedance selectable output (except CS0) Low-level output (CS0) High-level output 12 V application from off-chip 16 blocks High-impedance High-level output (except CS0) Low-level output (CS0) High-level output
Block divisions
Rev.5.00 Sep. 12, 2007 Page 759 of 764 REJ09B0396-0500
Appendix H Comparison of H8/300H Series Product Specifications
H.2
Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B)
Pin Arrangement of Each Product (FP-100B, TFP-100B)
On-chip-ROM Products H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group Vcc PB0/TP8/TMO0/ CS7 Vcc PB0/TP8/TMO0/ CS7 Vcc PB0/TP8/ TIOCA3 Vcc PB0/TP8/ TIOCA3 PB1/TP9/ TIOCB3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOC4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 PB6/TP14/ DREQ0 ROMless Products H8/3006, H8/3007 H8/3002 Vcc PB0/TP8/TMO0/ CS7 PB1/TP9/TMIO1/ DREQ0/CS6 PB2/TP10/TMO2/ CS5 PB3/TP11/ TMIO3/DREQ1/ CS4 PB4/TP12/ UCAS PB5/TP13/ LCAS/SCK2 PB6/TP14/TxD2 PB7/TP15/RxD2 RESO Vss P90/TxD0 P91/TxD1 P92/RXD0 P93/RXD1 P94/SCK0/IRQ4 P95/SCK1/IRQ5 P40/D0 P41/D1 P42/D2 P43/D3 Vss P44/D4 P45/D5 Vcc PB0/TP8/ TIOCA3 PB1/TP9/ TIOCB3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 PB6/TP14/ DREQ0 PB7/TP15/ DREQ1/ADTRG RESO Vss P90/TxD0 P91/TxD1 P92/RXD0 P93/RXD1 P94/SCK0/IRQ4 P95/SCK1/IRQ5 P40/D0 P41/D1 P42/D2 P43/D3 Vss P44/D4 P45/D5
Table H.1
Pin No. 1 2 3 4 5
PB1/TP9/TMIO1/ PB1/TP9/TMIO1/ PB1/TP9/ DREQ0/CS6 CS6 TIOCB3 PB2/TP10/TMO2/ PB2/TP10/TMO2/ PB2/TP10/ CS5 CS5 TIOCA4 PB3/TP11/ TMIO3/DREQ1/ CS4 PB4/TP12/ UCAS PB5/TP13/ LCAS/SCK2 PB6/TP14/TxD2 PB7/TP15/RxD2 RESO/FWE* Vss P90/TxD0 P91/TxD1 P92/RXD0 P93/RXD1 P94/SCK0/IRQ4 P95/SCK1/IRQ5 P40/D0 P41/D1 P42/D2 P43/D3 Vss P44/D4 P45/D5 PB3/TP11/ TMIO3/CS4 PB4/TP12 PB5/TP13 PB6/TP14 PB7/TP15 RESO/FWE* Vss P90/TxD0 P91/TxD1 P92/RXD0 P93/RXD1 P94/SCK0/IRQ4 P95/SCK1/IRQ5 P40/D0 P41/D1 P42/D2 P43/D3 Vss P44/D4 P45/D5 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 PB6/TP14/ DREQ0/CS7
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
PB7/TP15/ PB7/TP15/ DREQ1/ADTRG DREQ1/ADTRG RESO/VPP* Vss P90/TxD0 P91/TxD1 P92/RXD0 P93/RXD1 P94/SCK0/IRQ4 P95/SCK1/IRQ5 P40/D0 P41/D1 P42/D2 P43/D3 Vss P44/D4 P45/D5 RESO Vss P90/TxD0 P91/TxD1 P92/RXD0 P93/RXD1 P94/SCK0/IRQ4 P95/SCK1/IRQ5 P40/D0 P41/D1 P42/D2 P43/D3 Vss P44/D4 P45/D5
Rev.5.00 Sep. 12, 2007 Page 760 of 764 REJ09B0396-0500
Appendix H Comparison of H8/300H Series Product Specifications
Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 On-chip-ROM Products H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group P46/D6 P47/D7 P30/D8 P31/D9 P32/D10 P33/D11 P34/D12 P35/D13 P36/D14 P37/D15 Vcc P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 Vss P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P50/A16 P51/A17 P52/A18 P53/A19 P46/D6 P47/D7 P30/D8 P31/D9 P32/D10 P33/D11 P34/D12 P35/D13 P36/D14 P37/D15 Vcc P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 Vss P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P50/A16 P51/A17 P52/A18 P53/A19 P46/D6 P47/D7 P30/D8 P31/D9 P32/D10 P33/D11 P34/D12 P35/D13 P36/D14 P37/D15 Vcc P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 Vss P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P50/A16 P51/A17 P52/A18 P53/A19 P46/D6 P47/D7 P30/D8 P31/D9 P32/D10 P33/D11 P34/D12 P35/D13 P36/D14 P37/D15 Vcc P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 Vss P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P50/A16 P51/A17 P52/A18 P53/A19 ROMless Products H8/3006, H8/3007 H8/3002 P46/D6 P47/D7 D8 D9 D10 D11 D12 D13 D14 D15 Vcc A0 A1 A2 A3 A4 A5 A6 A7 Vss A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 P46/D6 P47/D7 D8 D9 D10 D11 D12 D13 D14 D15 Vcc A0 A1 A2 A3 A4 A5 A6 A7 Vss A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Rev.5.00 Sep. 12, 2007 Page 761 of 764 REJ09B0396-0500
Appendix H Comparison of H8/300H Series Product Specifications
Pin No. 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 On-chip-ROM Products H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group Vss P60/WAIT P61/BREQ P62/BACK P67/ STBY RES NMI Vss EXTAL XTAL Vcc P63/AS P64/RD P65/HWR P66/LWR MD0 MD1 MD2 AVcc VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVss Vss P60/WAIT P61/BREQ P62/BACK P67/ STBY RES NMI Vss EXTAL XTAL Vcc P63/AS P64/RD P65/HWR P66/LWR MD0 MD1 MD2 AVcc VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVss Vss P60/WAIT P61/BREQ P62/BACK STBY RES NMI Vss EXTAL XTAL Vcc P63/AS P64/RD P65/HWR P66/LWR MD0 MD1 MD2 AVcc VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVss Vss P60/WAIT P61/BREQ P62/BACK STBY RES NMI Vss EXTAL XTAL Vcc P63/AS P64/RD P65/HWR P66/LWR MD0 MD1 MD2 AVcc VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVss ROMless Products H8/3006, H8/3007 H8/3002 Vss P60/WAIT P61/BREQ P62/BACK P67/ STBY RES NMI Vss EXTAL XTAL Vcc AS RD HWR LWR MD0 MD1 MD2 AVcc VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVss P80/RFSH/IRQ0 P81/CS3/IRQ1 Vss P60/WAIT P61/BREQ P62/BACK STBY RES NMI Vss EXTAL XTAL Vcc AS RD HWR LWR MD0 MD1 MD2 AVcc VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVss P80/RFSH/IRQ0 P81/CS3/IRQ1
P80/RFSH/IRQ0 P80/IRQ0 P81/CS3/IRQ1 P81/CS3/IRQ1
P80/RFSH/IRQ0 P80/RFSH/IRQ0 P81/CS3/IRQ1 P81/CS3/IRQ1
Rev.5.00 Sep. 12, 2007 Page 762 of 764 REJ09B0396-0500
Appendix H Comparison of H8/300H Series Product Specifications
Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 On-chip-ROM Products H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group P82/CS2/IRQ2 P83/CS1/IRQ3/ ADTRG P84/CS0 Vss PA0/TP0/ TEND0/TCLKA PA1/TP1/ TEND1/TCLKB P82/CS2/IRQ2 P83/CS1/IRQ3/ ADTRG P84/CS0 Vss P82/CS2/IRQ2 P83/CS1/IRQ3 P84/CS0 Vss P82/CS2/IRQ2 P83/CS1/IRQ3 P84/CS0 Vss PA0/TP0/ TEND0/TCLKA PA1/TP1/ TEND1/TCLKB ROMless Products H8/3006, H8/3007 H8/3002 P82/CS2/IRQ2 P83/CS1/IRQ3/ ADTRG P84/CS0 Vss PA0/TP0/ TEND0/TCLKA PA1/TP1/ TEND1/TCLKB PA2/TP2/ TIOCA0/TCLKC PA3/TP3/ TIOCB0/TCLKD PA4/TP4/ TIOCA1/A23 PA5/TP5/ TIOCB1/A22 PA6/TP6/ TIOCA2/A21 PA7/TP7/ TIOCB2/A20 P82/CS2/IRQ2 P83/CS1/IRQ3 P84/CS0 Vss PA0/TP0/ TEND0/TCLKA PA1/TP1/ TEND1/TCLKB PA2/TP2/ TIOCA0/TCLKC PA3/TP3/ TIOCB0/TCLKD PA4/TP4/ TIOCA1/A23 PA5/TP5/ TIOCB1/A22 PA6/TP6/ TIOCA2/A21 PA7/TP7/ TIOCB2/A20
PA0/TP0/TCLKA PA0/TP0/ TEND0/TCLKA PA1/TP1/TCLKB PA1/TP1/ TEND1/TCLKB
PA2/TP2/ PA2/TP2/ PA2/TP2/ PA2/TP2/ TIOCA0/TCLKC TIOCA0/TCLKC TIOCA0/TCLKC TIOCA0/TCLKC PA3/TP3/ PA3/TP3/ PA3/TP3/ PA3/TP3/ TIOCB0/TCLKD TIOCB0/TCLKD TIOCB0/TCLKD TIOCB0/TCLKD PA4/TP4/ TIOCA1/A23 PA5/TP5/ TIOCB1/A22 PA6/TP6/ TIOCA2/A21 PA7/TP7/ TIOCB2/A20 PA4/TP4/ TIOCA1/A23 PA5/TP5/ TIOCB1/A22 PA6/TP6/ TIOCA2/A21 PA7/TP7/ TIOCB2/A20 PA4/TP4/ PA4/TP4/ TIOCA1/CS6/A23 TIOCA1/A23 PA5/TP5/ PA5/TP5/ TIOCB1/CS5/A22 TIOCB1/A22 PA6/TP6/ PA6/TP6/ TIOCA2/CS4/A21 TIOCA2/A21 PA7/TP7/ TIOCB2/A20 PA7/TP7/ TIOCB2/A20
Note:
*
Functions as RESO in the mask ROM versions, and as FWE in the flash memory and flash memory R versions.
Rev.5.00 Sep. 12, 2007 Page 763 of 764 REJ09B0396-0500
Appendix H Comparison of H8/300H Series Product Specifications
Rev.5.00 Sep. 12, 2007 Page 764 of 764 REJ09B0396-0500
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/3006, H8/3007
Publication Date: 1st Edition, December 1997 Rev.5.00, September 12, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.
(c) 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
Colophon 6.0
H8/3006, H8/3007 Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan

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